KR940012572A - Contact Forming Method in Semiconductor Device - Google Patents

Contact Forming Method in Semiconductor Device Download PDF

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Publication number
KR940012572A
KR940012572A KR1019920020682A KR920020682A KR940012572A KR 940012572 A KR940012572 A KR 940012572A KR 1019920020682 A KR1019920020682 A KR 1019920020682A KR 920020682 A KR920020682 A KR 920020682A KR 940012572 A KR940012572 A KR 940012572A
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KR
South Korea
Prior art keywords
layer
insulating layer
insulating
forming
mask layer
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KR1019920020682A
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Korean (ko)
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KR100230353B1 (en
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신헌종
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김광호
삼성전자 주식회사
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Priority to KR1019920020682A priority Critical patent/KR100230353B1/en
Publication of KR940012572A publication Critical patent/KR940012572A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

Abstract

본 발명은 반도체 장치에 있어서 주위 배선과의 단락불량이 없도록 자체정렬 (self-align)적으로 콘택트(contact)를 형성하는 방법에 관한 것으로서, 표면에 제1절연층이 형성되어 있는 반도체 기판상에 일정한 간격으로 두 개의 제1전도층을 패턴형성시키는 제1공정과, 상기 결과물 전면에 제2절연층을 평탄하게 형성시키고 그 위에 식각 마스크막을 형성시키는 제2공정과, 상기 제1전도층들 사이에 형성될 예정인 콘택홀 보다 크게 상기 식각 마스크막을 제거하고 남아있는 식각 마스크막과 상기 제1전도층을 마스크로 하여 상기 제2절연층과 제1절연층을 연속제거해주는 제3공정과, 상기 결과물상에 제3절연층과 제4절연층을 차례로 형성시켜준 후 상기 식각 마스크막의 표면이 노출되도록 표면을 평탄화시키는 제4공정과, 상기 식각 마스크막을 마스크로 하여 상기 3, 4절연층의 일부를 제거한 후 노출된 상기 제2절연층 측벽에 절연 스페이서를 형성시켜주는 제5공정과, 상기 잔존하는 제4절연층과 식각 마스크막을 제거하고 전면 식각하여 콘택트홀을 형성하고 제2전도층을 충진시켜주는 제6공정을 구비하여 이루어진 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of forming a self-aligned contact in a semiconductor device such that a short circuit with a peripheral wiring is not performed. A first step of patterning two first conductive layers at regular intervals, a second step of forming a second insulating layer evenly on the entire surface of the resultant, and forming an etch mask layer thereon; and between the first conductive layers A third process of removing the etch mask layer larger than a contact hole to be formed in the semiconductor substrate, and continuously removing the second insulating layer and the first insulating layer using the remaining etch mask layer and the first conductive layer as a mask; A fourth step of forming a third insulating layer and a fourth insulating layer on the substrate, and then planarizing the surface to expose the surface of the etching mask layer; and using the etching mask layer as a mask. Removing a part of the third and fourth insulating layers, and forming an insulating spacer on the exposed sidewalls of the second insulating layer; and removing the remaining fourth insulating layer and the etching mask layer and etching the entire surface to form a contact hole. And a sixth step of forming and filling the second conductive layer.

본 발명에 의하면 배선층과 단락불량없이 자체정렬적으로 콘택트를 형성할 수 있게 된다.According to the present invention, it is possible to form contacts in self-alignment without a short circuit defect with the wiring layer.

Description

반도체 장치에서의 콘택트 형성방법Contact Forming Method in Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도의 (가-(바)는 본 발명에 의한 콘택트홀 형성과정을 나타내는 단면도.2 is a cross-sectional view showing a process for forming a contact hole according to the present invention.

Claims (10)

표면에 제1절연층이 형성되어 있는 반도체 기판상에 제1전도층들을 패턴형성시키는 제1공정과, 상기 결과물 전면에 제2절연층을 평탄하게 형성시키고 그 위에 식각 마스크막을 형성시키는 제2공정과, 상기 제1전도층간 간격보다 크게 상기 식각 마스크막을 제거하고 남아있는 식각 마스크막과 상기 제1전도층을 마스크로 하여 상기 제2절연층과 제1절연층을 연속 제거해주는 제3공정과, 상기 결과물상에 제3절연층과 제4절연층을 차례로 형성시켜준 후 상기 식각 마스크막의 표면이 노출되도록 표면을 평탄화시키는 제4공정과, 상기 제3, 4절연층의 일부를 제거할 상기 제2절연층 측벽에 절연 스페이서를 형성시켜주는 제5공정과, 상기 잔존하는 제4절연층과 식각 마스크막을 제거하고 전면 식각하여 콘택트홀을 형성하고 제2전도층을 충진시켜주는 제6공정을 구비하여 이루어진 것을 특징으로 하는 콘택트 형성방법.A first step of patterning first conductive layers on a semiconductor substrate having a first insulating layer formed on a surface thereof, and a second step of forming a second insulating layer evenly on the entire surface of the resultant and forming an etching mask layer thereon And a third process of removing the etch mask layer larger than the gap between the first conductive layers and continuously removing the second insulating layer and the first insulating layer using the remaining etch mask layer and the first conductive layer as masks. Forming a third insulating layer and a fourth insulating layer sequentially on the resultant and then planarizing the surface to expose the surface of the etching mask layer; and removing the part of the third and fourth insulating layers. A fifth step of forming an insulating spacer on sidewalls of the insulating layer, and a sixth hole of removing the remaining fourth insulating layer and the etching mask layer and etching the entire surface to form contact holes and filling the second conductive layer. The method for forming the contact, characterized in that having been made in the. 제1항에 있어서, 상기 제1전도층은 폴리 실리콘층 또는 폴리사이드 구조인 것을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the first conductive layer is a polysilicon layer or a polyside structure. 제1항에 잇어서, 상기 제2전도층은 폴리 실리콘층, 폴리사이드 구조 또는 알루미늄층인 것을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the second conductive layer is a polysilicon layer, a polyside structure, or an aluminum layer. 제1항에 있어서, 상기 제2,3절연층은 산화막 또는 질화막으로 이루어진 것임을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the second and third insulating layers are formed of an oxide film or a nitride film. 제1항에 있어서, 상기 스페이서는 산화막 또는 질화막으로 이루어진 것임을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the spacer is formed of an oxide film or a nitride film. 제1항에 있어서, 상기 스페이서는 상기 제2, 3절연층보다 식각선택비가 큰 것으로 이루어지는 것을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the spacer has an etching selectivity greater than that of the second and third insulating layers. 제1항에 있어서, 상기 제2공정의 식각 마스크막은 상기 제2절연층보다 식각 선택비가 큰 것임을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the etching mask layer of the second process has an etching selectivity greater than that of the second insulating layer. 제7항에 있어서, 상기 제2공정의 식각 마스크막은 폴리 실리콘 또는 티타늄나이트라이드로 된 것임을 특징으로 하는 콘택트 형성방법.8. The method of claim 7, wherein the etching mask layer of the second process is made of polysilicon or titanium nitride. 제1항에 있어서, 상기 제4절연층은 상기 제3절연층 및 절연스페이서보다 식각 선택비가 큰 것임을 특징으로 하는 콘택트 형성방법.The method of claim 1, wherein the fourth insulating layer has an etching selectivity greater than that of the third insulating layer and the insulating spacer. 제9항에 있어서, 상기 제4절연층은 BPSG막, SOG막 또는 PR막중 어느 하나인 것임을 특징으로 하는 콘택트 형성방법.The method of claim 9, wherein the fourth insulating layer is any one of a BPSG film, an SOG film, and a PR film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020682A 1992-11-05 1992-11-05 Method of forming a contact hole in a semiconductor device KR100230353B1 (en)

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KR1019920020682A KR100230353B1 (en) 1992-11-05 1992-11-05 Method of forming a contact hole in a semiconductor device

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KR1019920020682A KR100230353B1 (en) 1992-11-05 1992-11-05 Method of forming a contact hole in a semiconductor device

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KR940012572A true KR940012572A (en) 1994-06-23
KR100230353B1 KR100230353B1 (en) 1999-11-15

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KR100507869B1 (en) * 1998-06-29 2005-11-03 주식회사 하이닉스반도체 Contact hole formation method of semiconductor device
KR100645841B1 (en) * 1998-12-30 2007-03-02 주식회사 하이닉스반도체 Polysilicon Plug Forming Method Using Abrasive Stopping Film

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