KR960009014A

KR960009014A - Contact formation method of semiconductor device

Info

Publication number: KR960009014A
Application number: KR1019940020696A
Authority: KR
Inventors: 권태우
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1994-08-22
Filing date: 1994-08-22
Publication date: 1996-03-22

Abstract

본 발명은 소정 간격을 갖는 제2전도층 배선사이의 최하부 제1전도층 상에 제3전도층을 콘택시키는 반도체소자의 콘택 형성 방법에 있어서, 최하부 전도층(4), 상기 최하부 전도층(4)상의 제1절연막(2), 상기 제1절연막(2)상에 소정크기를 패터닝된 제2전도층(3)배선이 기형성된 전체구조상부에 제2절연막(5)을 얇게 형성하는 단계; 상기 제2절연막(5)상에 평탄화 절연막인 제3절연막(6)을 형성하는 단계; 콘택 마스크(7)를 사용하여 제3절연막(5) 및 제2절연막(5)을 차례로 식각하는 단계; 드러난 제2전도층(3)을 식각하는 단계; 상기 제2전도층(3) 측벽에 스페이서 제4절연막(8)을 형성하는 동시에 제1절연막(2)을 식각하여 콘택하고자 하는 부위의 최하부 전도층(4)을 오픈시키는 단계; 전체 구조상부에 제3전도층(9)을 형성하는 단계를 포함하여 이루지는 것을 특징으로 하는 반도체 소자의 콘택 형성방법에 관한 것으로, 콘택형성시 트랜지스터 소오스/드레인 자기정렬 및 채널길이를 유지하면서 콘택은 합선없게 이룰수 있으며, 스페이스 절연막의 두께를 최소화 시킴으로써 넓은 콘택 영역확보 및 콘택 에스펙트 비를 개선 할 수 있고, 식각시간 감소에 따른 웨이퍼 내 균일도 개선과 기판손상을 감소 시키는 등 여러 효과를 가져온다.The present invention provides a contact forming method of a semiconductor device for contacting a third conductive layer on a lowermost first conductive layer between second conductive layer wirings having a predetermined interval, the lower conductive layer 4 and the lower conductive layer 4. Forming a thin second insulating film (5) on the first structure of the first insulating film (2) and the entire structure where the second conductive layer (3) patterned with a predetermined size is formed on the first insulating film (2); Forming a third insulating film (6) which is a planarization insulating film on the second insulating film (5); Etching the third insulating film 5 and the second insulating film 5 in sequence using the contact mask 7; Etching the exposed second conductive layer 3; Forming a spacer fourth insulating film (8) on the sidewalls of the second conductive layer (3) and etching the first insulating film (2) to open the lowermost conductive layer (4) at the portion to be contacted; A method for forming a contact of a semiconductor device, comprising forming a third conductive layer 9 over an entire structure, wherein the contact is formed while maintaining the transistor source / drain self-alignment and the channel length. It can be achieved without short circuit, and by minimizing the thickness of the space insulating film, it is possible to secure wide contact area and improve the contact aspect ratio, and improve the uniformity in the wafer and reduce the damage of the substrate due to the reduction of etching time.

Description

Contact formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1d도는 본 발명의 일실시예에 따른 콘택 형성공정도.Figure 1d is a contact forming process according to an embodiment of the present invention.

Claims

A method for forming a contact of a semiconductor device, comprising: contacting a third conductive layer on a lowermost second conductive layer between second conductive layer wirings having a predetermined interval; Forming a thinner second insulating layer on an upper structure of a lower conductive layer, a first insulating layer of the lower conductive layer, and a second conductive layer wiring patterned on a predetermined size on the first insulating layer; Forming a third insulating film, which is a planarization insulating film, on the second insulating film; Etching the third insulating layer and the second insulating layer in sequence using a contact mask; Etching the exposed second conductive layer; Forming a spacer fourth insulating layer on the sidewalls of the second conductive layer and etching the first insulating layer to open a lowermost conductive layer of a portion to be contacted; And forming a third conductive layer over the entire structure.

The method of claim 1, wherein etching the exposed second conductive layer is inclinedly etched so that the lower portion of the second conductive layer has an original size.

※ Note: The disclosure is based on the initial application.