KR960035899A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR960035899A
KR960035899A KR1019950006071A KR19950006071A KR960035899A KR 960035899 A KR960035899 A KR 960035899A KR 1019950006071 A KR1019950006071 A KR 1019950006071A KR 19950006071 A KR19950006071 A KR 19950006071A KR 960035899 A KR960035899 A KR 960035899A
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KR
South Korea
Prior art keywords
forming
gate
film
junction region
conductive film
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KR1019950006071A
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Korean (ko)
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KR0147714B1 (en
Inventor
인성욱
이윤종
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김주용
현대전자산업 주식회사
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Priority to KR1019950006071A priority Critical patent/KR0147714B1/en
Publication of KR960035899A publication Critical patent/KR960035899A/en
Application granted granted Critical
Publication of KR0147714B1 publication Critical patent/KR0147714B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 기판 상에 게이트 산화막 및 게이트 제1전도막을 차례로 형성하는 단계; 상기 게이트 제1전도막의 소정부위를 전체두께중 소정두께 식각하는 단계; 게이트 마스크를 사용하여 상기 게이트 제1전도막, 게이트 산화막을 차례로 식각하는 단계; 저농도 불순물 접합영역을 형성하는 단계; 전체구조 상부 표면을 따라 얇은 질화막을 형성하는 단계; 전체구조 상부에 제1절연막을 형성하고 다시 비등방성 전면식각하여 스페이서 제1절연막을 형성하는 동시에 노출되는 질화막을 식각하는 단계; 고농도 불순물 접합영역을 형성하여 소오스/드레인 접합영역을 완성하는 단계; 전체 구조 상부에 평탄화 절연막을 형성하는 단계; 및 상기 소오스/드레인 접합영역에 상기 게이트 전도막 패턴 사이의 공간을 통과하는 제2전도막을 콘택시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법에 관한 것으로, 게이트 패턴의 변형으로, 게이트 및 비트라인간의 공간을 증가시켜, 비트라인 또는 Vss라인 콘택 마스크 작업시의 오정렬에 관련된 공정 마진을 확보하여 누설전류 방지와 소자의 제조 수율을 향상시키는 효과가 있다.The present invention comprises the steps of sequentially forming a gate oxide film and a gate first conductive film on a semiconductor substrate; Etching a predetermined portion of the gate first conductive film to a predetermined thickness of the entire thickness; Etching the gate first conductive layer and the gate oxide layer sequentially using a gate mask; Forming a low concentration impurity junction region; Forming a thin nitride film along the entire upper surface of the structure; Forming a spacer first insulating film by forming an insulating layer on the entire structure, and then anisotropically etching the entire surface to etch the nitride film exposed at the same time; Forming a high concentration impurity junction region to complete the source / drain junction region; Forming a planarization insulating film over the entire structure; And contacting the second conductive film that passes through the space between the gate conductive film pattern to the source / drain junction region. By increasing the space between the lines, process margins related to misalignment during bit line or Vss line contact mask operation are secured, thereby preventing leakage current and improving device manufacturing yield.

Description

반도체 소자 제조 방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1G도는 본 발명의 일실시예 따른 버퍼용 비트라인 콘택 형성 공정도.1A to 1G are diagrams illustrating a process of forming a bit line contact for a buffer according to an embodiment of the present invention.

Claims (3)

반도체 기판 상에 게이트 산화막 및 게이트 제1전도막을 차례로 형성하는 단계; 상기 게이트 제1전도막의 소정부위를 전체두께중 소정두께 식각하는 단계; 게이트 마스크를 사용하여 상기 게이트 제1전도막, 게이트 산화막을 차례로 식각하는 단계; 저농도 불순물 접합영역을 형성하는 단계; 전체구조 상부 표면을 따라 얇은 질화막을 형성하는 단계; 전체구조 상부에 제1절연막을 형성하고 다시 비등방성 전면식각하여 스페이서 제1절연막을 형성하는 동시에 노출되는 질화막을 식각하는 단계; 고농도 불순물 접합영역을 형성하여 소오스/드레인 접합영역을 완성하는 단계; 전체 구조 상부에 평탄화 절연막을 형성하는 단계; 및 상기 소오스/드레인 접합영역에 상기 게이트 전도막 패턴 사이의 공간을 통과하는 제2전도막을 콘택시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.Sequentially forming a gate oxide film and a gate first conductive film on the semiconductor substrate; Etching a predetermined portion of the gate first conductive film to a predetermined thickness of the entire thickness; Etching the gate first conductive layer and the gate oxide layer sequentially using a gate mask; Forming a low concentration impurity junction region; Forming a thin nitride film along the entire upper surface of the structure; Forming a spacer first insulating film by forming an insulating layer on the entire structure, and then anisotropically etching the entire surface to etch the nitride film exposed at the same time; Forming a high concentration impurity junction region to complete the source / drain junction region; Forming a planarization insulating film over the entire structure; And contacting the second conductive film passing through the space between the gate conductive film pattern to the source / drain junction region. 제1항에 있어서; 상기 제2전도막 콘택 단계는 제2전도막 콘택 마스크 및 상기 평탄화 제2절연막 식각공정으로 접합영역을 오픈시켜 콘택홀을 형성하는 단계; 상기 콘택홀 측벽에 스페이서 제3절연막을 형성하는 단계; 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1; The second conductive layer contacting step may include forming a contact hole by opening a junction region through a second conductive layer contact mask and the planarized second insulating layer etching process; Forming a spacer third insulating layer on the sidewalls of the contact hole; A method of manufacturing a semiconductor device comprising the step of forming a second conductive film. 제1항에 있어서, 상기 제2전도막 콘택 단계는 제2전도막 콘택 마스크를 사용하여 상기 평탄화 제2연막의 전체두께중 소정 두께를 식각하는 단계; 상기 평탄화 제2절연막이 식각된 부위의 측벽에 스페이서 제3절연막을 형성하는 동시에 제2절연막을 식각하여 접합영역을 오픈시키는 단계; 제2전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the second conductive film contacting step comprises: etching a predetermined thickness of the entire thickness of the planarized second flexible film using a second conductive film contact mask; Forming a spacer third insulating film on a sidewall of the portion where the planarized second insulating film is etched and simultaneously etching the second insulating film to open a junction region; A method of manufacturing a semiconductor device comprising the step of forming a second conductive film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006071A 1995-03-22 1995-03-22 Method for manufacturing a semiconductor device KR0147714B1 (en)

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KR1019950006071A KR0147714B1 (en) 1995-03-22 1995-03-22 Method for manufacturing a semiconductor device

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KR1019950006071A KR0147714B1 (en) 1995-03-22 1995-03-22 Method for manufacturing a semiconductor device

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KR960035899A true KR960035899A (en) 1996-10-28
KR0147714B1 KR0147714B1 (en) 1998-11-02

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