KR960026288A - Micro contact hole formation method of semiconductor device - Google Patents

Micro contact hole formation method of semiconductor device Download PDF

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Publication number
KR960026288A
KR960026288A KR1019940032799A KR19940032799A KR960026288A KR 960026288 A KR960026288 A KR 960026288A KR 1019940032799 A KR1019940032799 A KR 1019940032799A KR 19940032799 A KR19940032799 A KR 19940032799A KR 960026288 A KR960026288 A KR 960026288A
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South Korea
Prior art keywords
conductive layer
forming
contact hole
entire surface
etching
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KR1019940032799A
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Korean (ko)
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KR100291824B1 (en
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940032799A priority Critical patent/KR100291824B1/en
Publication of KR960026288A publication Critical patent/KR960026288A/en
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Publication of KR100291824B1 publication Critical patent/KR100291824B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 미세콘택홀 형성방법에 관한 것으로, 반도체 기판 상부에 소자분리절연막, 불순물접합영역 및 게이트전극을 순차적으로 형성하고 전체표면상부에 일정두께 제1도전층을 형성한 다음, 전체표면 상부에 감광막을 두껍게 형성하고 상기 제1도전층의 상부가 노출되도록 상기 감광막을 플라즈마를 이용하여 전면식각한 다음, 상기 게이트전극의 측면에 남아있는 감광막을 식각장벽으로하여 상기 제1도전층을 전면식각하고 상기 감광막을 제거함으로써 상기 게이트전극 사이에 제1도전층패드를 형성한 다음, 제2도전층을 콘택시킴으로써 콘택공정시 미스얼라인이 발생시에도 접합누설을 방지할 수 있어 반도체소자의 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a micro contact hole of a semiconductor device, and sequentially forming a device isolation insulating film, an impurity junction region, and a gate electrode on a semiconductor substrate, and forming a first conductive layer with a predetermined thickness on the entire surface, and then A thick photoresist layer is formed on the upper surface of the surface, and the photoresist layer is etched using plasma to expose the upper portion of the first conductive layer. Then, the first conductive layer is formed by using the photoresist layer remaining on the side of the gate electrode as an etching barrier. By etching the entire surface and removing the photoresist, a first conductive layer pad is formed between the gate electrodes, and then a second conductive layer is contacted to prevent junction leakage even when misalignment occurs during the contact process. It is a technology that can improve.

Description

반도체소자의 미세콘택홀 형성방법.Method for forming a fine contact hole of a semiconductor device.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자의 미세콘택홀 형성방법을 도시한 단면도.1A to 2D are cross-sectional views illustrating a method for forming a micro contact hole in a semiconductor device according to an embodiment of the present invention.

Claims (4)

반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 게이트 전극을 순차적으로 형성하는 공정과, 상기 제이트전극의 측벽에 절연막 스페이서를 형성하는 공정과, 전체표면상부에 일정두께 제1도전층을 형성하는 공정과, 전체표면상부에 감광막을 두껍게 형성하는 공정과, 상기 감광막을 상기 제1도전층이 노출되도록 전면식각하는 공정과, 상기 남아있는 감광막을 식각장벽으로하여 상기 제1도전층을 전면식각하는 공정과, 상기 남아있는 감광막을 제거함으로써 상기 게이트전극 간에만 제1도전층패드를 형성하는 공정과, 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 상기 제1도전층패드를 노출시키는 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 제1도전층패드에 접속되도록 제2도전층을 형성하는 공정을 포함하는 반도체소자의 미세콘택홀 형성방법.Forming a device isolation insulating film, an impurity junction region, and a gate electrode on the semiconductor substrate sequentially; forming an insulating film spacer on the sidewall of the first electrode; and forming a first conductive layer on the entire surface of the semiconductor substrate. Forming a photoresist film thickly over the entire surface, etching the entire photoresist film to expose the first conductive layer, and etching the entire first photoconductive layer using the remaining photoresist film as an etch barrier. Forming the first conductive layer pad only between the gate electrodes by removing the remaining photoresist film; forming a lower insulating layer to planarize the entire upper surface; and an etching process using a contact mask. (1) forming a contact hole exposing the conductive layer pad, and connecting the first conductive layer pad to the first conductive layer pad through the contact hole; Forming fine contact hole, a semiconductor device including a step of forming a layer. 제1항에 있어서, 상기 제1도전층은 다결정실리콘 형성된 특징으로 하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the first conductive layer is formed of polycrystalline silicon. 제1항에 있어서, 상기 감광막의 전면식각은 산소분위기의 플라즈마를 이용하여 실시하는 것을 특징으로 하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the entire surface of the photoresist is etched using a plasma in an oxygen atmosphere. 제1항에 있어서, 상기 제2도전층은 다결정실리콘으로 형성된 것을 특징으로 하는 반도체소자의 미세콘택홀 형성방법.The method of claim 1, wherein the second conductive layer is formed of polycrystalline silicon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032799A 1994-12-05 1994-12-05 Method for forming fine contact hole of semiconductor device KR100291824B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032799A KR100291824B1 (en) 1994-12-05 1994-12-05 Method for forming fine contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032799A KR100291824B1 (en) 1994-12-05 1994-12-05 Method for forming fine contact hole of semiconductor device

Publications (2)

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KR960026288A true KR960026288A (en) 1996-07-22
KR100291824B1 KR100291824B1 (en) 2001-12-01

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