KR930015013A - Semiconductor device having buried contact region and forming method thereof - Google Patents

Semiconductor device having buried contact region and forming method thereof Download PDF

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Publication number
KR930015013A
KR930015013A KR1019910023013A KR910023013A KR930015013A KR 930015013 A KR930015013 A KR 930015013A KR 1019910023013 A KR1019910023013 A KR 1019910023013A KR 910023013 A KR910023013 A KR 910023013A KR 930015013 A KR930015013 A KR 930015013A
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South Korea
Prior art keywords
buried contact
region
oxide film
polysilicon layer
gate
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KR1019910023013A
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Korean (ko)
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KR950000853B1 (en
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성진모
윤종섭
양종열
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정몽헌
현대전자산업 주식회사
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Priority to KR1019910023013A priority Critical patent/KR950000853B1/en
Publication of KR930015013A publication Critical patent/KR930015013A/en
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Publication of KR950000853B1 publication Critical patent/KR950000853B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 매립형 콘택영역을 구비하는 반도체소자 및 그 형성방법에 관한 것으로, 폴리실리콘게이트가 매립형 콘택영역을 충분히 오버랩되도록 하여 폴리실리콘게이트를 식각할 때 매립형 콘택영역에 트렌치가 형성되지 않도록 하며, 매립형 콘택패턴을 오버사이즈되게 한 마스크를 허용하여 이온주입함으로써, 폴리실리콘게이트와 확산영역과의 전기적인 연결특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a buried contact region and a method of forming the buried contact region so that the polysilicon gate sufficiently overlaps the buried contact region so that a trench is not formed in the buried contact region when the polysilicon gate is etched. The present invention relates to a technique for improving electrical connection characteristics between a polysilicon gate and a diffusion region by allowing ion implantation by allowing a mask with an oversize contact pattern.

Description

매립형 콘택영역을 구비하는 반도체소자 및 그 형성방법Semiconductor device having buried contact region and forming method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 매립형 콘택영역을 가진 반도체소자의 레이웃도,3 is a layout diagram of a semiconductor device having a buried contact region according to the present invention;

제4도 제3도에 도시된 바와같은 본 발명에 따른 매립형 콘택영역을 가진 반도체소자에서 B-B' 부분을 절단하여 나타낸 제조공정단면도.4 is a cross-sectional view of the manufacturing process of a semiconductor device having a buried contact region according to the present invention as shown in FIG.

Claims (4)

게이트 전극과 확산영역을 직접 연결시키기 위한 매립형 콘택영역 형성 방법에 있어서, 실리콘기판(1)을 제공하는 단계와, 상기 실리콘 기판(1) 상부에 소자분리용 필드산화막(2) 및 게이트 산화막(3)을 형성하는 단계와, 상기 필드산화막(2) 및 게이트 산화막(3) 상부에 제1폴리실리콘층(4)을 증착하는 단계와, 상기 제1폴리실리콘층(4) 상부에 매립형 콘택마스크를 사용하여 매립형 콘택(10)을 형성하는 단계와, 상기 매립형 콘택(10) 및 잔존하는 제1폴리실리콘층(4) 상부에 제2폴리실리콘층(5)을 증착하는 단계와, 상기 제2폴리실리콘층(5) 상부에 포토레지스트층(6)을 도포한 후 콘택마스크를 형성하여 이온주입하는 단계와, 상기 포토레이지스터층(6)을 제거한 후, 상기 필드산화막(2) 및 게이트 산화막(3) 소정부분 상부의 제1폴리실리콘층(4) 및 제2폴리실리콘층(5)을 식각하여, 폴리실리콘게이트(11)를 형성하고 실리콘기판(1) 소정부에 LDD 영역을 형성하는 단계와, 상기 폴리실리콘게이트(11) 측벽에 스페이서(7)를 형성한 후 이온주입공정을 거쳐 불순물 확산영역을 형성하는 단계를 포함하는 것을 특징으로 하는 매립형 콘택영역 형성방법.A method of forming a buried contact region for directly connecting a gate electrode and a diffusion region, the method comprising: providing a silicon substrate 1, and forming a field oxide film 2 and a gate oxide film 3 on top of the silicon substrate 1; ), Depositing a first polysilicon layer (4) on the field oxide film (2) and the gate oxide film (3), and a buried contact mask on the first polysilicon layer (4) Forming a buried contact 10 using the same, depositing a second polysilicon layer 5 over the buried contact 10 and the remaining first polysilicon layer 4, and After applying the photoresist layer 6 on the silicon layer 5 to form a contact mask and ion implantation, and after removing the photoresist layer 6, the field oxide film 2 and the gate oxide film ( 3) a first polysilicon layer 4 and a second polysilicon layer over a predetermined portion Etching (5) to form a polysilicon gate (11) and forming an LDD region in a predetermined portion of the silicon substrate (1), forming a spacer (7) on the sidewall of the polysilicon gate (11), and then A buried contact region forming method comprising the step of forming an impurity diffusion region through an implantation process. 제1항에 있어서, 폴리실리콘게이트(11)를 매립형 콘택(10) 영역에 충분히 오버랩시키는 것을 특징으로 하는 매립형 콘택영역 형성방법.The method for forming a buried contact region according to claim 1, wherein the polysilicon gate (11) is sufficiently overlapped with the buried contact (10) region. 제2항에 있어서, 폴리실리콘게이트(11)의 매립형 콘택(10) 영역에 대한 오버랩 지역을 원하는 불순물로 확산시키기 위해 매립형 콘택패턴을 오버사이즈시킨 마스크 패턴을 사용하는 것을 특징으로 하는 매립형 콘택영역 형성방법.3. The buried contact region formation according to claim 2, wherein a mask pattern in which the buried contact pattern is oversized is used to diffuse the overlap region with respect to the buried contact 10 region of the polysilicon gate 11 with desired impurities. Way. 게이트 전극과 확산영역을 직접 연결시키기 위한 매립형 콘택영역을 구비하는 반도체소자에 있어서, 실리콘기판(1)과, 상기 실리콘기판(1) 상부에 형성되는 소자분리용 필드산화막(2) 및 게이트 산화막(3)의 소정부분과, 상기 소자분리용 필드산화막(2) 및 게이트 산화막(3)의 소정부분 상부의 형성되는 제1폴리실리콘층(4)과, 상기 제1폴리실리콘층(4) 상부에 형성되는 제2폴리실리콘층(5)과, 상기 제1폴리실리콘층(4)과 제2폴리실리콘층(5)의 소정부분을 식각하여 형성되는 폴리실리콘게이트(11)와, 상기 폴리실리콘게이트(11) 측벽에 형성되는 스페이서(7)와, 이온주입공정에 의해 형성되는 불순물 확산영역(8)을 구비하는 것을 특징으로 하는 매립형 콘택영역을 구비하는 반도체소자.A semiconductor device having a buried contact region for directly connecting a gate electrode and a diffusion region, comprising: a silicon substrate 1, a field isolation film 2 and a gate oxide film formed over the silicon substrate 1; 3), the first polysilicon layer 4 formed over the predetermined portion of the device isolation field oxide film 2 and the gate oxide film 3, and the upper portion of the first polysilicon layer 4 A second polysilicon layer 5 formed, a polysilicon gate 11 formed by etching a predetermined portion of the first polysilicon layer 4 and the second polysilicon layer 5, and the polysilicon gate (11) A semiconductor device having a buried type contact region comprising a spacer (7) formed on a sidewall and an impurity diffusion region (8) formed by an ion implantation process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910023013A 1991-12-14 1991-12-14 Fabricating method of semiconductor device KR950000853B1 (en)

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KR1019910023013A KR950000853B1 (en) 1991-12-14 1991-12-14 Fabricating method of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019910023013A KR950000853B1 (en) 1991-12-14 1991-12-14 Fabricating method of semiconductor device

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KR930015013A true KR930015013A (en) 1993-07-23
KR950000853B1 KR950000853B1 (en) 1995-02-02

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