KR960009204A - How to prepare pyrom - Google Patents

How to prepare pyrom Download PDF

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Publication number
KR960009204A
KR960009204A KR1019940021319A KR19940021319A KR960009204A KR 960009204 A KR960009204 A KR 960009204A KR 1019940021319 A KR1019940021319 A KR 1019940021319A KR 19940021319 A KR19940021319 A KR 19940021319A KR 960009204 A KR960009204 A KR 960009204A
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KR
South Korea
Prior art keywords
polysilicon layer
layer
ion
gate electrode
forming
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Application number
KR1019940021319A
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Korean (ko)
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KR100310415B1 (en
Inventor
김태훈
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문정환
금성일렉트론 주식회사
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Priority to KR1019940021319A priority Critical patent/KR100310415B1/en
Publication of KR960009204A publication Critical patent/KR960009204A/en
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Publication of KR100310415B1 publication Critical patent/KR100310415B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명에서는 이피롬의 게이트전극을 형성하는 방법에 있어서, 하나의 폴리실리콘층에 이온주입 및 아닐링 공정으로 절연막을 형성시켜서 콘트롤게이트와 플로팅게이트를 구분하여 형성시켜서 이피롬의 제조공정을 단순솨시키고, 주변회로와 이피롬의 게이트전극을 함께 형성하여 폴리시리콘층의 증착 및 식각공정에 대한 반도체기판의 주변회로 영역에 대한 악영향을 방지한다.In the present invention, in the method for forming a gate electrode of epipyrom, an insulating film is formed on one polysilicon layer by ion implantation and annealing to separate the control gate and the floating gate, thereby simplifying the manufacturing process of epipyrom. In addition, the peripheral circuit and the gate electrode of the pyrom are formed together to prevent adverse effects on the peripheral circuit region of the semiconductor substrate during the deposition and etching of the polysilicon layer.

Description

이피롬의 제조방법How to prepare pyrom

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 이피롬에서 게이트전극의 형성단계를 도시한 도면.2 is a view showing a step of forming a gate electrode in a pyrom according to the present invention.

Claims (3)

필드산화막으로 소자형성영역이 정의된 반도체기판에 주변회로의 트랜지스터와 이피롬셀의 게이트전극을 형성시키는 방법에 있어서, 1)소자 형성영역에 제1절연막을 형성시킨 후에, 기판 전면에 폴리실리콘층을 형성시키는 단계와, 2)상기 폴리실리콘층에 포토레지스터로 주변회로부분은 덮고 이피롬영역은 노출시키는 마스크 패턴을 형성시킨 후에, 노출된 상기 폴리실리콘층에 소정 이온을 이온주입하여 이온메몰층을 형성시키는 단계와, 3)상기 포토레지스터를 제거한 후에, 상기 폴리실리콘층을 사진식각하여 기판상의 소정영역에 이온메몰층을 형성시킨 게이트전극용 폴리실리콘층을 형성시키는 단계와, 4)상기 게이트전극용 폴리실리콘층의 이온메몰층을 아닐링공정으로 제2절연막으로 형성시키는 단계를 포함하여 이루어진 이피롬의 제조방법.A method of forming a transistor of a peripheral circuit and a gate electrode of a pyromium cell on a semiconductor substrate in which a device formation region is defined by a field oxide film, comprising: 1) forming a polysilicon layer on the entire surface of a substrate after forming a first insulating film in the device formation region; Forming a mask pattern covering the peripheral circuit portion with a photoresist and exposing the epitaxial region to the polysilicon layer, and then ion implanting predetermined ions into the exposed polysilicon layer to form an ion-method layer. 3) forming a polysilicon layer for a gate electrode in which an ion-membrane layer is formed in a predetermined region on a substrate by photo etching the polysilicon layer after removing the photoresist; and 4) the gate electrode. Formation of the pyrilomium comprising the step of forming an ion-membrane layer of the polysilicon layer for the second insulating film by an annealing process . 제1항에 있어서, 상기 2)단계에서 상기 이온메몰층은 상시 폴리실리콘층에 산소이온을 이온주입하여 형성시키고, 상기 3)단계에서는 상기 이온메몰층을 형성시킨 게이트전극용 폴리실리콘층은 상기 기판의 이피롬영역에 형성시키면서, 상기 기판의 주변회로영역에는 트랜지스터용 게이트전극을 형성시키고, 상기 4)단계에서는 상기 제2절연막은 이피롬의 플로팅게이트와 콘트롤게이트와 콘트롤게이트를 구분시키는 산화막을 형성시키는 것이 특징인 이피롬의 제조방법.The gate silicon polysilicon layer of claim 1, wherein the ion-method layer is formed by ion implanting oxygen ions into the polysilicon layer at step 2), and the ion-membrane layer is formed at step 3). A transistor gate electrode is formed in the peripheral circuit region of the substrate, and in step 4), the second insulating layer is formed of an oxide film that separates the floating gate of the pyrom and the control gate from the control gate. Method for producing epipyrrole characterized in that it is formed. 제1항에 있어서, 상기 2)단계에서 상기 이온메몰층은 상시 폴리실리콘층에 질소이온을 이온주입하여 형성시키고, 상기 3)단계에서는 상기 이온메몰층을 형성시킨 게이트전극용 폴리실리콘층은 상기 기판의 이피롬영역에 형성시키면서, 상기 기판의 주변회로영역에는 트랜지스터용 게이트전극을 형성시키고, 상기 4)단계에서는 상기 제2절연막은 이피롬의 플로팅게이트와 콘트롤게이트를 구분시키는 질화막을 형성시키는 것이 특징인 이피롬의 제조방법.The gate silicon polysilicon layer of claim 1, wherein in the step 2), the ion-memory layer is formed by ion implanting nitrogen ions into the polysilicon layer at all times, and in step 3), the polysilicon layer for the gate electrode is formed. A transistor gate electrode is formed in the peripheral circuit region of the substrate, and in step 4), the second insulating layer forms a nitride film that separates the floating gate and the control gate of the pyromium. Characterized by a method for producing pyromium. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940021319A 1994-08-29 1994-08-29 Method for fabricating eeprom KR100310415B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940021319A KR100310415B1 (en) 1994-08-29 1994-08-29 Method for fabricating eeprom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940021319A KR100310415B1 (en) 1994-08-29 1994-08-29 Method for fabricating eeprom

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KR960009204A true KR960009204A (en) 1996-03-22
KR100310415B1 KR100310415B1 (en) 2001-12-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100398039B1 (en) * 1996-06-29 2004-01-07 주식회사 하이닉스반도체 Method for manufacturing flash memory device

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