KR950021133A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR950021133A
KR950021133A KR1019930031903A KR930031903A KR950021133A KR 950021133 A KR950021133 A KR 950021133A KR 1019930031903 A KR1019930031903 A KR 1019930031903A KR 930031903 A KR930031903 A KR 930031903A KR 950021133 A KR950021133 A KR 950021133A
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South Korea
Prior art keywords
film
polysilicon
pattern
forming
etching
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KR1019930031903A
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Korean (ko)
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KR970009616B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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Publication of KR950021133A publication Critical patent/KR950021133A/en
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Publication of KR970009616B1 publication Critical patent/KR970009616B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제종방법에 관한 것으로 특히 실리콘 기판과 금속배선과의 접속을 피하기 위하여 폴리 실리콘막에 의하여 금속배선과 실리콘 기판이 연결되도록 하여, 질화막을 사용한 게이트 전극을 형성함으로써 게이트 전극용 마스크의 임계지수보다 더 작은 게이트 전극을 형성하도록 한 초고집식 반도체 소자용 트랜지스터 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating semiconductor devices, and in particular, in order to avoid the connection between the silicon substrate and the metal wiring, the metal wiring and the silicon substrate are connected by a polysilicon film, thereby forming a gate electrode using a nitride film, thereby forming a mask for the gate electrode. A method of manufacturing a transistor for an ultra-high density semiconductor device, the gate electrode of which is smaller than the critical index of.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도 내지 제2h도는 본 발명의 반도체 소자 제조방법에 따른 공정 단계를 도시한 단면도.2A to 2H are cross-sectional views showing process steps according to the method of manufacturing a semiconductor device of the present invention.

Claims (3)

반도체 소자 제조공정에 있어서, 실리콘 기판상에 Ｐ-웰과 활성영역을 설정하고 채널스톱Ｐ＋이온을 주입한 다음, 소정의 필드 산화막을 형성하는 단계와, 전체구조의 상부에 산화막과 폴리실리콘막 및 산화막을 차례로 각각 형성하고, 상기 산화막과 폴리실리콘막 및 산화막의 소정부위를 식각하여 실리콘 기판의 일정부위가 노출되게 하는 단계와, 전체구조 상부에 감광막을 증착한 후, 일정부위를 식각하여 감광막 패턴을 형성한 후, 불순물을 이온주입하여 소오스/드레인 영역을 형성하는 단계와, 감광막 패턴을 제거한 후, 전체구조 상부에 도핑된 폴리실리콘막을 증착하는 단계와, 상기 폴리실리콘막의 소정부위를 식각하여 폴리실리콘이 소오스/드레인 상부에 위치한 노출된 실리콘 기판 상부와, 산화막과 폴리실리콘막 및 산화막의 측면부에 남아 형성되는 스페이서를형성하는 단계와, 전체구조 상부에 소정 두께의 게이트 산화막과 게이트 전극용 폴리 실리콘막 및 질화막을 각각 순차적으로 중착하는 단계와, 소정의 마스크 형성공정으로 감광막 패턴이 필드 산화막 상부에 있는 폴리실리콘막이 형성되지 않은 부위에 위치하도록 감광막 패턴을 형성하는 단계와, 폴리실리콘막을 식각 정지층으로 하여 폴리실리콘막 상부에 있는 질화막의 소정부위를 건식식각하여 제 1 질화막 패턴을 형성하는 단계와, 상기 제 1 질화막 패턴을 마스크로하여 질화막 하부에 위치한 폴리 실리콘막을 습식식각하여 잔류 폴리실리콘막을 형성하는 단계와, 상기 제1질화막 패턴을 잔류 폴리 실리콘막의 상부 크기와 동일하게 식각하여 제 2 질화막 패턴을 형성하는 단계와, 상기 제 2 질화막 패턴을 마스크로 하여 잔류 폴리실리콘을 건식식각하여 게이트 전극을 형성하고 Ｎ-이온을 주입하는 단계와, 전체구조 상부에 전이금속막과 열산화막을 연속적으로 형성한 다음, 고온 열처리하여 산화막 스페이서 상부의 전이금속막을 전이금속 산화막으로 전환시키는 단계와, 전체구조 상부에 층간 절연용 산화막 및 비피에스지(ＢＰＳＧ）막을 증착한 후, 식각하여 전이금속막이 노출된 콘택흘을 형성하는 단계와, 상기 콘택흘을 통하여 전이금속막 콘택되는 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제공방법.In the semiconductor device manufacturing process, P-well and an active region are set on a silicon substrate, and channel stop P + ions are implanted, and then a predetermined field oxide film is formed, and an oxide film and a polysilicon film on the entire structure. And forming oxide films in order, and etching predetermined portions of the oxide film, the polysilicon film, and the oxide film to expose a predetermined portion of the silicon substrate, depositing a photosensitive film on the entire structure, and then etching a predetermined portion of the photosensitive film. After the pattern is formed, ion implantation of impurities to form source / drain regions; after removing the photoresist pattern, depositing a doped polysilicon layer on the entire structure; and etching a predetermined portion of the polysilicon layer. Polysilicon is placed on top of the exposed silicon substrate, located above the source / drain, and on the oxide, polysilicon and side surfaces of the oxide film. Forming a spacer to be formed; sequentially depositing a gate oxide film having a predetermined thickness, a polysilicon film for a gate electrode, and a nitride film over the entire structure; and forming a photoresist pattern on the field oxide film by a predetermined mask forming process. Forming a photoresist pattern so as to be located at a portion where the polysilicon film is not formed, and dry etching a predetermined portion of the nitride film on the polysilicon film using the polysilicon film as an etch stop layer to form a first nitride film pattern And wet etching the polysilicon film under the nitride film using the first nitride film pattern as a mask to form a residual polysilicon film, and etching the first nitride film pattern to the same size as the upper size of the residual polysilicon film. Forming a pattern and using the second nitride film pattern as a mask Dry etching the remaining polysilicon to form a gate electrode and implanting N - ions; successively forming a transition metal film and a thermal oxide film over the entire structure, and then performing a high temperature heat treatment to form a transition metal film over the oxide spacer Converting to an oxide film, depositing an interlayer insulating oxide film and a BPS film on the entire structure, and etching the same to form a contact flow in which the transition metal film is exposed, and transition metal film contact through the contact flow A semiconductor device providing method comprising the step of forming a metal wiring. 제1항에 있어서, 상기 잔류 폴리실리콘막의 상부 크기와 동일하게 제1 질화막 패턴을 식각하여 제 2 질화막 패턴을 형성함에 있어, 섭씨 160도에서 180도의 온도범위에서 인산용액으로 습식식각하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the first nitride film pattern is etched to form the second nitride film pattern by the same size as the upper size of the residual polysilicon film. A semiconductor device manufacturing method characterized in that. 제1항에 있어서, 상기 게이트 전극 측면에 스페이서를 형성하기 위해 질화막과 산화막을 동일한 식각속도로 블랭키트 식각하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the nitride film and the oxide film are blank-etched at the same etching rate to form a spacer on the side of the gate electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR93031903A 1993-12-31 1993-12-31 Fabricating method of semiconductor device KR970009616B1 (en)

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KR950021133A true KR950021133A (en) 1995-07-26
KR970009616B1 KR970009616B1 (en) 1997-06-14

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100773537B1 (en) * 2003-06-03 2007-11-07 삼성전자주식회사 Nonvolatile memory device composing one switching device and one resistant material and method of manufacturing the same
US7521704B2 (en) 2004-04-28 2009-04-21 Samsung Electronics Co., Ltd. Memory device using multi-layer with a graded resistance change

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100773537B1 (en) * 2003-06-03 2007-11-07 삼성전자주식회사 Nonvolatile memory device composing one switching device and one resistant material and method of manufacturing the same
US8101983B2 (en) 2003-06-03 2012-01-24 Samsung Electronics Co., Ltd. Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same
US8164130B2 (en) 2003-06-03 2012-04-24 Samsung Electronics Co., Ltd. Nonvolatile memory device comprising one switching device and one resistant material and method of manufacturing the same
US7521704B2 (en) 2004-04-28 2009-04-21 Samsung Electronics Co., Ltd. Memory device using multi-layer with a graded resistance change

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