KR0156787B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR0156787B1 KR0156787B1 KR1019950029806A KR19950029806A KR0156787B1 KR 0156787 B1 KR0156787 B1 KR 0156787B1 KR 1019950029806 A KR1019950029806 A KR 1019950029806A KR 19950029806 A KR19950029806 A KR 19950029806A KR 0156787 B1 KR0156787 B1 KR 0156787B1
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 엘디디(LDD : Lightly-doped drain)영역을 가지는 반도체 소자에 있어서, 소자 특성을 향상시키기에 적합하도록 반도체 기판위에 제1절연막과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 제2절연막을 선택식각하여 게이트 형성영역에 제2절연막을 잔류시키는 단계와, 제2절연막의 측면에 측벽을 형성하는 단계와, 제2절연막과 측벽을 마스크로 제1절연막이 드러나도록 식각한 후, 제2절연막과 측벽 및 제1절연막의 표면에 얇은 산화막을 형성하는 단계와, 제2절연막과 측벽을 마스크로 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 측벽을 및 제1절연막상부의 얇은 산화막을 제거하고, 제2절연막을 마스크로 반도체층을 식각하여 게이트를 형성하는 단계와, 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 일련의 단계를 진행하여, 고농도 불순물 영역의 정션 깊이를 증가하여 특성을 향상시키면서, 엘디디영역은 얇은 정션을 유지할 수 있어서, 종래와 같이 숏 채널 효과가 나타나는 문제점을 해결하였고, 이와 같이 소자 불량을 줄여 생산시 수율을 향상시킬 수 있음을 효과적인 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a semiconductor device having a lightly-doped drain (LDD) region, a first insulating film, a semiconductor layer, Stacking the second insulating film in sequence, selectively etching the second insulating film to leave the second insulating film in the gate formation region, forming sidewalls on the side surfaces of the second insulating film, and masking the second insulating film and the sidewalls. Etching to expose the first insulating layer, and forming a thin oxide film on the surface of the second insulating layer, the sidewall, and the first insulating layer, and implanting a high concentration of ions into the semiconductor substrate using the second insulating layer and the sidewall as a mask. Forming a region, removing the thin oxide film on the sidewalls and the upper portion of the first insulating film, and etching the semiconductor layer using the second insulating film as a mask to form a gate; By proceeding a series of steps including implanting low concentration ions into the substrate to form low concentration impurity regions, the LED region can maintain a thin junction while increasing the junction depth of the high concentration impurity regions to improve characteristics, As a conventional method, the short channel effect has been solved, and thus, an effective feature is that the device defect can be reduced to improve the yield in production.
Description
제1도는 종래의 반도체 소자 제조방법의 각 단계를 예시한 단면도.1 is a cross-sectional view illustrating each step of a conventional semiconductor device manufacturing method.
제2도는 본 발명의 반도체 소자 제조방법의 각 단계를 예시한 단면도.2 is a cross-sectional view illustrating each step of the method of manufacturing a semiconductor device of the present invention.
제3도는 본 발명의 다른 실시예의 각 단계를 예시한 단면도.3 is a cross-sectional view illustrating each step of another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,20 : 반도체 기판 11,21 : 제1절연막10,20: semiconductor substrate 11,21: first insulating film
12 : 다결절실리콘층 12-1,22-2 : 게이트12: polycrystalline silicon layer 12-1, 22-2: gate
13 : 절연막 13-1 : 게이트상부산화막13 insulating film 13-1 gate top oxide film
14,24 : 레지스트 15 : 저농도 불순물 영역14,24: resist 15: low concentration impurity region
15-1.27 : 엘디디 영역 16,25 : 측벽15-1.27: LED area 16, 25: side wall
17,26 : 고농도 불순물 영역 22,22-1 : 반도체층17,26: high concentration impurity region 22,22-1: semiconductor layer
23,23-1 : 제2절연막 27 : 얇은 산화막23,23-1: Second insulating film 27: Thin oxide film
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 엘디디(LDD : Lightly-doped drain)영역을 가지는 반도체 소자에 있어서, 소자 특성을 향상시키기에 적합하도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving device characteristics in a semiconductor device having an LDD (lightly-doped drain) region.
엘디디영역을 가지는 반도체 소자의 구조는 소자 제조 기술이 발전함에 따라서 대용량화와, 소자 크기의 소형화의 작업이 계속되는 가운데 발생된 문제점을 해결하기 위한 수단으로, 특히 모스 트랜지스터의 제조에 있어서 소자 크기의 소형화 작업이 계속되면서 게이트의 측면 길이가 좁아짐에 따라 핫 캐리어(hot carrier)에 의해 소자 동작이 불안정해지는 등의 문제점을 해결하기 위하여 제안된 수단이다.The structure of the semiconductor device having the LED area is a means for solving the problems caused by the development of the large capacity and the miniaturization of the device size as the device manufacturing technology is developed. In particular, the size of the device in the manufacturing of the MOS transistor is reduced. As the lateral length of the gate is narrowed as the operation continues, it is a proposed means to solve a problem such as unstable operation of the device due to a hot carrier.
종래에 이런 엘디디 영역을 가지는 반도체 소자의 제조 방법은 제1도의 (a) 내지 제1도의 (e)에서 도시한 바와 같은 각 단계를 포함하는 공정을 거쳐 제조하였다.Conventionally, a method of manufacturing a semiconductor device having such an LED area is manufactured through a process including each step as shown in FIGS. 1A to 1E.
제1도의 (a) 내지 제1도의 (e)는 종래의 반도체 소자 제조방법의 각 공정단계를 예시한 도면이다.1 (a) to 1 (e) are diagrams illustrating respective process steps of a conventional semiconductor device manufacturing method.
제1도의 (a)와 같이, 반도체 기판(10)위에 제1절연막(11), 다결정실리콘(polysilicon)층(12), 캡 HLD 등으로 형성한 절연막(13)을 차례로 적층시킨다.As shown in FIG. 1A, a first insulating film 11, a polysilicon layer 12, an insulating film 13 formed of a cap HLD, or the like is sequentially stacked on the semiconductor substrate 10.
다음으로, 제1도의(a)와 같이, 사진식각작업을 하여, 절연막(13)과, 다결정실리콘층(12)을 차례로 식각하여 게이트(12-1)와 게이트상부산화막(13-1)을 형성시킨다. 이때, 도면번호 14는 레지스트이다.Next, as shown in FIG. 1A, a photolithography process is performed to sequentially etch the insulating film 13 and the polysilicon layer 12 to form the gate 12-1 and the gate top oxide film 13-1. To form. At this time, reference numeral 14 denotes a resist.
다음으로, 제1도의(c)와 같이, 게이트상부산화막(13-1)위의 레지스트(14)을 제거하고, 반도체 기판에 저농도의 이온을 주입하여, 저농도 불순물 영역(15)을 형성시킨다. 이때, 게이트(12-1) 및 게이트상부산화막(13-1)은 이온주입에 대한 마스크로서의 역할을 하여 게이트 측부의 반도체 기판 영역에만 저농도 불순물층(15)이 형성된다.Next, as shown in FIG. 1C, the resist 14 on the gate top oxide film 13-1 is removed, and low concentration ions are implanted into the semiconductor substrate to form the low concentration impurity region 15. At this time, the gate 12-1 and the gate top oxide film 13-1 serve as a mask for ion implantation, and the low concentration impurity layer 15 is formed only in the semiconductor substrate region at the gate side.
다음으로, 제1도의 (d)와 같이, 게이트상부산화막(13-1) 및 반도체 기판(10) 상부에 제3산화막층을 형성시킨 후, 에치백(etch-back)하여 게이트 및 게이트상부산화막의 측면에 측벽스페이서(sidewall-spacer)(16)를 형성시킨다.Next, as shown in FIG. 1D, after forming the third oxide film layer on the gate top oxide film 13-1 and the semiconductor substrate 10, the gate and gate top oxide films are etched back. A sidewall spacer 16 is formed on the side of the.
다음으로, 제1도의 (e)와 같이, 반도체 기판에 고농도 이온을 주입하여, 고농도 불순물층(17)을 형성시킨다. 이때, 게이트(12-1), 게이트상부산화막(13-1) 및 측벽스페이서(16)는 이온주입에 대한 마스크 역활을 하여, 측벽스페이스(16) 하부영역 만큼의 저농도 불순물층(15-1)이 남게 되므로 엘디디 영역을 가지는 반도체 소자 구조를 형성시킨다. 다음으로, 고온 열처리(RTA : rapid temperature annealing)를 실시하여, 게이트 측부의 고농도 불순물층(17)의 정션깊이를 증가시켜, 저항특성을 높여주어 게이트 측부영역을 안정화시킨다.Next, as shown in FIG. 1E, high concentration ions are implanted into the semiconductor substrate to form the high concentration impurity layer 17. In this case, the gate 12-1, the gate top oxide layer 13-1, and the sidewall spacers 16 serve as masks for ion implantation, so that the low concentration impurity layer 15-1 as much as the lower region of the sidewall space 16 is formed. Because of this, the semiconductor device structure having the LED area is formed. Next, rapid temperature annealing (RTA) is performed to increase the junction depth of the highly doped impurity layer 17 on the gate side, thereby increasing the resistance characteristics and stabilizing the gate side region.
이와같은 종래의 제조방법을 거쳐 제도된 엘디디 영역을 가지는 반도체 소자는 고농도 불순물층의 전기적 특성을 높이기 위한 고온 열처리공정 수행시, 저농도 불순물층 즉 엘디디 영역의 정션 깊이도 증가되어 숏 채널 효과가 발생하는 문제가 있다.A semiconductor device having an LED region prepared through such a conventional manufacturing method has a short channel effect due to an increase in the junction depth of a low concentration impurity layer, that is, an LED region when a high temperature heat treatment process is performed to increase electrical characteristics of a high concentration impurity layer. There is a problem that occurs.
그래서, 본 발명의 반도체 소자 제조방법은 엘디디 영역 형성시, 발생되는 엘디디 영역의 정션 깊이 증가 등의 부효과를 제거하기 위하여, 반도체 소자 제조방법에 있어서, 반도체 기판위에 제1절연막과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 제2절연막을 선택식각하여 게이트 형성영역에 제2절연막을 잔류시키는 단계와, 제2절연막의 측면에 측벽을 형성하는 단계와, 제2절연막과 측벽을 마스크로 반도체층을 식각하여 제2절연막과 측벽하부에 반도체층을 잔류시키고, 그 이외에 영역에는 얇게 반도체층을 잔류시키는 단계와, 제2절연막과 측벽을 마스크로 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 측벽을 제거하고, 제2절연막을 마스크로 반도체층을 식각하여 게이트를 형성하는 단계와, 게이트를 마스크로 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법이다.Therefore, the semiconductor device manufacturing method of the present invention, in order to eliminate the side effects such as the increase in the junction depth of the LED area generated during the formation of the LED region, in the semiconductor device manufacturing method, the first insulating film and the semiconductor on the semiconductor substrate Stacking the layers, the second insulating film in sequence, selectively etching the second insulating film to leave the second insulating film in the gate formation region, forming sidewalls on the side surfaces of the second insulating film, and Etching the semiconductor layer with the sidewalls as a mask to leave the semiconductor layer under the second insulating film and the sidewalls, and leaving a thin layer of the semiconductor layer in the region; and applying a high concentration of ions to the semiconductor substrate with the second insulating film and the sidewall as a mask Forming a high concentration impurity region by implantation, removing sidewalls, and etching a semiconductor layer using a second insulating film as a mask to form a gate; By scrolling the semiconductor device manufacturing method comprising the steps of: forming a low concentration impurity region by implanting ions with a low concentration to the semiconductor substrate.
또한, 본 발명의 반도체 소자 제조방법은 반도체 기판위에 제1절연막과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 제2절연막을 선택 식각하여 게이트 형성영역에 제2절연막을 전류시키는 단계와, 제2절연막의 측면에 측벽을 형성하는 단계와, 제2절연막과 측벽을 마스크로 제1절연막이 드러나도록 식각한 후, 제2절연막과 측벽 및 제1절연막의 표면에 얇은 산화막을 형성하는 단계와, 제2절연막과 측벽을 마스크로 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 제2절연막과 측벽 및 제1절연막상부의 얇은 산호막을 제거하고, 제2절연막을 마스크로 반도체층을 식각하여 게이트를 형성하는 단계와, 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법이다.In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of laminating a first insulating film, a semiconductor layer, and a second insulating film on a semiconductor substrate in turn, and selectively etching the second insulating film to apply a second insulating film to the gate formation region. Forming a sidewall on the side of the second insulating film, etching the second insulating film and the sidewall to expose the first insulating film, and then forming a thin oxide film on the surface of the second insulating film, the sidewall, and the first insulating film. Forming a high concentration impurity region by implanting high concentration ions into the semiconductor substrate using the second insulating film and the sidewall as a mask, removing the second insulating film, the sidewall and the thin coral film on the first insulating film, and removing the second insulating film. Etching the semiconductor layer with a mask to form a gate; and implanting low concentration ions into the semiconductor substrate to form a low concentration impurity region. A conductor device manufacturing method.
위의 두가지 반도체 소자 제조방법은 모두 고농도 불순물 영역을 형성하는 한 후, 저농도 불순물 영역 즉, 엘디디영역을 형성하는 것이 특징인데, 이는 고농도 불순물 영역을 형성한 후, 고농도 불순물 영역의 전기적 특성(저항 특성)을 높이기 위하여 정션높이를 증가시켜주기 위하여 수행하는 고온 열처리(rapid temprature annealing)단계를 엘디디영역을 형성 단계 이전에 실시하여 주어, 고온 열처리시 부효과로 엘디디영역의 정션깊이까지 증가시키어 나타나는 숏 채널 효과를 줄일 수 있다.Both of the above semiconductor device manufacturing methods are characterized by forming a high concentration impurity region, and then forming a low concentration impurity region, that is, an LED region. In order to increase the junction height, a rapid temprature annealing step is performed prior to the formation of the LED area to increase the junction height of the LED area. Short channel effects appearing can be reduced.
본 발명의 반도체 소자 제조방법을 도면을 예시하여 설명하면 다음과 같다.The semiconductor device manufacturing method of the present invention will be described with reference to the drawings.
먼저, 제2도의 (a)에서와 같이, 반도체 기판(20)위에 제1절연막(21)과, 반도체층(22)과, 제2절연막(23)을 적층한다. 이때, 제1절연막(21)은 게이트 절연막으로 산화막으로 형성하고, 반도체층(22)은 다결정실리콘 등으로 형성한다. 또한, 반도체층(22)의 상부에 적층한 제2절연막(23)은 캡산화막으로, cap HLD 또는 cap HTO 등을 이용한다.First, as shown in FIG. 2A, the first insulating film 21, the semiconductor layer 22, and the second insulating film 23 are stacked on the semiconductor substrate 20. At this time, the first insulating film 21 is formed of an oxide film as a gate insulating film, and the semiconductor layer 22 is formed of polycrystalline silicon or the like. The second insulating film 23 stacked on the semiconductor layer 22 is a cap oxide film, and cap HLD or cap HTO is used.
다음으로, 제2도의 (c)와 같이, 제2절연막(23)의 게이트 형성 영역을 제외한 영역을 사진식각공정으로 식각제거한다. 도면상에 식각된 제2절연막(23-1)의 상부에 형성된 구조체는 레지스트(24)이다.Next, as shown in FIG. 2C, the region except for the gate forming region of the second insulating layer 23 is etched away by a photolithography process. The structure formed on the second insulating film 23-1 etched in the drawing is a resist 24.
다음으로, 제2도의 (b)와 같이, 식각된 제2절연막(23-1)과, 제2절연막에 의해 노출된 반도체층(22) 위에 제3절연막을 적층한 후, 에치백하여 제2절연막(23-1)의 측부에 측벽(25)을 형성한다. 이때, 제3절연막을 질화막을 이용하여 형성한다.Next, as illustrated in FIG. 2B, a third insulating film is laminated on the etched second insulating film 23-1 and the semiconductor layer 22 exposed by the second insulating film, and then etched back to form a second insulating film. The side wall 25 is formed in the side part of the insulating film 23-1. At this time, a third insulating film is formed using a nitride film.
다음으로, 제2도의 (d)와 같이, 식각된 제2절연막(23-1)과, 측벽(25)을 마스크로 반도체층(22)을 식각한다. 반도체층은 다결정실리콘으로 형성하였으므로, 이를 건식각한다. 식각된 반도체층(22-1)은 고농도 불순물 영역을 정의하기 위한 것이다. 이때, 제1절연막(21)상부에 얇게 반도체층을 잔류시킨다. 이는 이후 측벽 제거시, 제1절연막(21)을 보호하여, 고온 열처리시 고농도 불순물 영역을 보호할 수 있도록 한 것이다.Next, as shown in FIG. 2D, the semiconductor layer 22 is etched using the etched second insulating film 23-1 and the sidewall 25 as a mask. Since the semiconductor layer is formed of polycrystalline silicon, it is dry etched. The etched semiconductor layer 22-1 is to define a high concentration impurity region. At this time, a thin semiconductor layer is left on the first insulating film 21. This is to protect the first insulating film 21 when the sidewalls are removed afterwards, thereby protecting the high concentration impurity region during high temperature heat treatment.
다음으로, 제2도의 (e)와 같이, 반도체 기판(20)에 고농도의 이온을 주입하여 고농도 불순물 영역(26)을 형성한다. 이온주입은 반도체 기판(20)상부에 형성된 식각된 반도체층(22-1)과, 그 상부의 식각된 제2절연막(23-1)과, 식각된 제2절연막(23-1)의 측부에 형성된 측벽(25)을 마스크로 이루어진다. 이어서, 고농도 불순물층의 특성을 강화하기 위한 고온 열처리를 진행한다.Next, as shown in FIG. 2E, a high concentration of ions are implanted into the semiconductor substrate 20 to form a high concentration impurity region 26. Ion implantation is performed on the side of the etched semiconductor layer 22-1 formed on the semiconductor substrate 20, the etched second insulating film 23-1, and the etched second insulating film 23-1. The formed side wall 25 is made of a mask. Subsequently, high temperature heat treatment is performed to enhance the characteristics of the high concentration impurity layer.
다음으로, 제2도의 (f)와 같이, 측벽(25)을 제거한 후, 식각된 제2절연막(23-1)을 마스크로 식각된 반도체층(22-1)을 재식각하여 게이트(22-2)를 형성한다. 측벽(25)의 제거는 습식각작업을 이용하고, 반도체층의 식각은 건식각작업을 이용한다.Next, as shown in FIG. 2F, after the sidewalls 25 are removed, the semiconductor layer 22-1 etched using the etched second insulating layer 23-1 as a mask is etched again to form a gate 22-2. 2) form. Removal of the sidewall 25 uses a wet etching operation, and etching of the semiconductor layer uses a dry etching operation.
다음으로, 제2도의 (g)와 같이, 반도체 기판(20)에 저농도의 이온을 주입하여 저농도 불순물 영역(27)을 형성한다. 이와 같은 일련의 공정을 거쳐 반도체 기판(20)상에는 최상부에 식각된 제2절연막(23-1) 즉 게이트상부 산화막과, 그 하부에 게이트(22-2)와, 그 하부에 게이트 절연막(21)과, 게이트 측하부인 기판상에 저농도 불순물 영역(27) 즉 엘디디 영역과, 엘디디 영역의 측부에 고농도 불순물 영역(26)을 가지는 구조를 형성한다.Next, as shown in FIG. 2 (g), low concentration ions are implanted into the semiconductor substrate 20 to form the low concentration impurity region 27. Through such a series of processes, the second insulating layer 23-1, that is, the upper gate oxide layer, etched on the uppermost portion of the semiconductor substrate 20, the gate 22-2 below the gate insulating film 21, and the gate insulating layer 21 below And a structure having a low concentration impurity region 27, that is, an LED region and a high concentration impurity region 26, on the side of the LED region.
제3도는 본 발명의 다른 반도체 소자 제조방법은 먼저, 제3도의 (a)에서와 같이, 반도체 기판(20)위에 제1절연막(21)과, 반도체층(22)과, 제2절연막(23)을 적층한다. 이때, 제1절연막(21)은 게이트 절연막으로 산화막으로 형성하고, 반도체층(22)은 다결정실리콘 등으로 형성한다. 또한, 반도체층(22)의 상부에 적층한 제2절연막(23)은 캡산화막으로, cap HLD 또는 cap HTO로 형성한다.FIG. 3 shows another method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 3A, the first insulating film 21, the semiconductor layer 22, and the second insulating film 23 are formed on the semiconductor substrate 20. )). At this time, the first insulating film 21 is formed of an oxide film as a gate insulating film, and the semiconductor layer 22 is formed of polycrystalline silicon or the like. In addition, the second insulating film 23 laminated on the semiconductor layer 22 is a cap oxide film and is formed of cap HLD or cap HTO.
다음으로, 제3도의 (b)와 같이, 제2절연막(23)의 게이트 형성 영역을 제외한 영역을 사진식각공정으로 식가제거한다. 도면상에 시각된 제2절연막(23-1)의 상부에 형성된 구조체는 레지스트(24)이다.Next, as shown in (b) of FIG. 3, the region except for the gate forming region of the second insulating layer 23 is etched away by a photolithography process. The structure formed on the upper portion of the second insulating film 23-1 as shown in the drawing is a resist 24.
다음으로, 제3도의 (c)와 같이, 식각된 제2절연막(23-1)과, 제2절연막에 의해 노출된 반도체층(22) 위에 제3절연막을 적층한 후, 에치백하여 제2절연막(23-1)의 측부에 측벽(25)을 형성한다. 이때, 제3절연막은 질화막을 이용하여 형성한다.Next, as shown in FIG. 3C, the third insulating film is stacked on the etched second insulating film 23-1 and the semiconductor layer 22 exposed by the second insulating film, and then etched back to form a second insulating film. The side wall 25 is formed in the side part of the insulating film 23-1. In this case, the third insulating film is formed using a nitride film.
다음으로, 제3도의 (d)와 같이, 식각된 제2절연막(23-1)과, 측벽(25)을 마스크로 제1절연막(21)이 노출되도록 반도체층(22)을 식각한다. 반도체층은 다결정실리콘으로 형성하였으므로, 이를 건식각한다. 식각된 반도체층(22-1)은 고농도 불순물 영역을 정의하기 위한 것이다. 이때, 제1절연막(21)을 노출시킨 후, 제1절연막(21), 반도체층(22-1), 측벽(25) 및 제2절연막(23-1)의 표면에 얇은 산화막을(27)을 형성하여, 이후 측벽 제거시, 제1절연막(21)을 보호하여, 고온 열처리시 고농도 불순물 영역을 보호할 수 있도록 한 것이다.Next, as illustrated in FIG. 3D, the semiconductor layer 22 is etched such that the etched second insulating film 23-1 and the sidewall 25 are exposed as a mask. Since the semiconductor layer is formed of polycrystalline silicon, it is dry etched. The etched semiconductor layer 22-1 is to define a high concentration impurity region. In this case, after exposing the first insulating film 21, a thin oxide film 27 is formed on the surfaces of the first insulating film 21, the semiconductor layer 22-1, the sidewalls 25, and the second insulating film 23-1. After the sidewalls are removed, the first insulating layer 21 is protected to protect the high concentration impurity region during high temperature heat treatment.
다음으로, 제3도의 (e)와 같이, 반도체 기판(20)에 얇은 산화막을 통하여 고농도의 이온을 주입함으로써 고농도 불순물 영역(26)을 형성한다. 이온주입은 반도체 기판(20)상부에 형성된 식각된 반도체층(22-1)과, 그 상부의 식각된 제2절연막(23-1)과, 식각된 제2절연막(23-1)의 측부에 형성된 측벽(25)을 마스크로 이루어진다. 이어서, 고농도 불순물층의 특성을 강하하기 위한 고온 열처리를 진행한다.Next, as shown in FIG. 3E, a high concentration impurity region 26 is formed by implanting high concentration ions into the semiconductor substrate 20 through a thin oxide film. Ion implantation is performed on the side of the etched semiconductor layer 22-1 formed on the semiconductor substrate 20, the etched second insulating film 23-1, and the etched second insulating film 23-1. The formed side wall 25 is made of a mask. Next, a high temperature heat treatment is performed to lower the characteristics of the high concentration impurity layer.
다음으로, 제3도의 (f)와 같이, 얇은산화막(27)을 제거하고, 측벽(25)을 제거한 후, 식각된 제2절연막(23-1)을 마스크로 식각된 반도체층(22-1)을 재식각하여 게이트(22-2)를 형성한다. 측벽(25)의 제거는 습식각작업을 이용하고, 반도체층의 식각은 건식각작업을 이용한다.Next, as shown in FIG. 3F, after removing the thin oxide film 27 and removing the sidewall 25, the semiconductor layer 22-1 etched with the etched second insulating film 23-1 as a mask. ) Is re-etched to form the gate 22-2. Removal of the sidewall 25 uses a wet etching operation, and etching of the semiconductor layer uses a dry etching operation.
다음으로, 제3도의 (g)와 같이, 반도체 기판(20)에 저농도의 이온을 주입하여 저농도 불순물영역(27)을 형성한다. 이와 같은 일련의 공정을 거쳐 반도체 기판(20)상에는 최상부에 식각된 제2절연막(23-1) 즉 게이트상부산화막과, 그 하부에 게이트(22-2)와, 그 하부에 게이트 절연막(21)과, 게이트 측하부인 기판상에 저농도 불순물 영역(27) 즉 엘디디 영역과, 엘디디 영역의 측부에 고농도 불순물 영역(26)을 가지는 구조를 형성한다.Next, as shown in FIG. 3G, low concentration ions are implanted into the semiconductor substrate 20 to form the low concentration impurity region 27. Through such a series of processes, the second insulating layer 23-1, that is, the gate upper oxide layer, etched on the uppermost portion of the semiconductor substrate 20, the gate 22-2 at the lower portion thereof, and the gate insulating layer 21 at the lower portion thereof. And a structure having a low concentration impurity region 27, that is, an LED region and a high concentration impurity region 26, on the side of the LED region.
이와 같은 본 발명의 반도체 소자 제조방법은 고농도 불순물 영역의 정션 깊이를 증가하여 특성을 향상시키면서, 엘디디영역은 얇은 정션을 유지할 수 있어서, 종래와 같이 숏 채널 효과가 나타나는 문제점을 해결하였고, 이와 같은 소자 불량을 줄여 생산시 수율을 향상시킬 수 있음을 효과적인 특징으로 한다.The semiconductor device manufacturing method of the present invention increases the junction depth of the high concentration impurity region and improves the characteristics, while the LED region can maintain a thin junction, thereby solving the problem of the short channel effect as in the prior art. It is an effective feature that it is possible to improve the yield in production by reducing device defects.
Claims (12)
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