KR970018242A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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KR970018242A
KR970018242A KR1019950029806A KR19950029806A KR970018242A KR 970018242 A KR970018242 A KR 970018242A KR 1019950029806 A KR1019950029806 A KR 1019950029806A KR 19950029806 A KR19950029806 A KR 19950029806A KR 970018242 A KR970018242 A KR 970018242A
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insulating layer
layer
insulating
semiconductor
film
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KR1019950029806A
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KR0156787B1 (en
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윤강식
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문정환
Lg 반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 엘디디(LDD : Lightly-doped drain)영역을 가지는 반도체 소자에 있어서, 소자 특성을 향상시키기에 적합하도록 반도체 기판위에 제1절연막과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 제2절연막을 선택식각하여 게이트 형성영역에 제2절연막을 잔류시키는 단계와, 제2절연막의 측면에 측벽을 형성하는 단계와, 제2절연막과 측벽을 마스크로 제1절연막이 드러나도록 식각한 후, 제2절연막과 측벽 및 제1절연막의 표면에 얇은 산화막을 형성하는 단계와, 제2절연막과 측벽을 마스크로 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 측벽 및 제1절연막상부의 얇은 산화막을 제거하고, 제2절연막을 마스크로 반도체층을 식각하여 게이트를 형성하는 단계와, 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 일련의 단계를 진행하여, 고농도 불순물 영역의 정션 깊이를 증가하여 특성을 향상시키면서, 엘디디영역은 얕은 정션을 유지할 수 있어서, 종래와 같이 숏 채널 효과가 나타나는 문제점을 해결하였고, 이와 같이 소자 불량을 줄여 생산시 수율을 향상시킬 수 있음을 효과적인 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a semiconductor device having a lightly-doped drain (LDD) region, a first insulating film, a semiconductor layer, Stacking the second insulating film in sequence, selectively etching the second insulating film to leave the second insulating film in the gate formation region, forming sidewalls on the side surfaces of the second insulating film, and masking the second insulating film and the sidewalls. Etching to expose the first insulating layer, and forming a thin oxide film on the surface of the second insulating layer, the sidewall, and the first insulating layer, and implanting a high concentration of ions into the semiconductor substrate using the second insulating layer and the sidewall as a mask. Forming a region, removing a thin oxide film on the sidewalls and the upper portion of the first insulating layer, and etching the semiconductor layer using the second insulating layer as a mask to form a gate; By proceeding a series of steps including implanting low concentration ions into the plate to form low concentration impurity regions, the LED region can maintain a shallow junction while increasing the junction depth of the high concentration impurity regions to improve characteristics, As a conventional method, the short channel effect has been solved, and thus, an effective feature is that the device defect can be reduced to improve the yield in production.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 반도체 소자 제조방법의 각 단계를 예시한 단면도,2 is a cross-sectional view illustrating each step of the semiconductor device manufacturing method of the present invention;

제3도는 본 발명의 다른 실시예의 각 단계를 예시한 단면도.3 is a cross-sectional view illustrating each step of another embodiment of the present invention.

Claims (12)

반도체 소자 제조방법에 있어서, 1) 반도체 기판위에 제1절연마과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 2) 상기 제2절연막을 선택식각하여 게이트 형성영역에 제2절연막을 잔류시키는 단계와, 3) 상기 제2절연막의 측면에 측벽을 형성하는 단계와, 4) 상기 제2절연막과 상기 측벽을 마스크로 상기 반도체층을 식각하여 상기 제2절연막과 상기 측벽하부에 반도체층을 잔류시키고, 그 이외에 영역에는 얇게 반도체층을 잔류시키는 단계와, 5) 상기 제2절연막과 측벽을 마스크로 상기 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 6) 상기 측벽을 제거하고, 상기 제2절연막을 마스크로 상기 반도체층을 식각하여 게이트를 형성하는 단계와, 7) 상기 게이트를 마스크로 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.1. A method of fabricating a semiconductor device, comprising: 1) stacking a first insulating layer, a semiconductor layer, and a second insulating layer on a semiconductor substrate in turn; and 2) selectively etching the second insulating layer to leave a second insulating layer in a gate formation region. 3) forming sidewalls on the side surfaces of the second insulating layer, and 4) etching the semiconductor layer using the second insulating layer and the sidewalls as a mask to form a semiconductor layer under the second insulating layer and the sidewalls. Leaving a thin layer of semiconductor in the region; and 5) forming a high concentration impurity region by implanting a high concentration of ions into the semiconductor substrate using the second insulating film and the sidewall as a mask; and 6) the sidewall. Forming a gate by etching the semiconductor layer using the second insulating layer as a mask; and 7) injecting a low concentration of ions into the semiconductor substrate using the gate as a mask to FIG method of manufacturing a semiconductor device comprising the step of forming the impurity region. 제1항에 있어서, 상기 제1절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the first insulating layer is formed of an oxide film. 제1항에 있어서, 상기 반도체층은 다결정실리콘으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the semiconductor layer is formed of polycrystalline silicon. 제1항에 있어서, 상기 제2절연막은 산화막, 질화막 중 택일하여 사용하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the second insulating layer is one of an oxide film and a nitride film. 제1항에 있어서, 상기 측벽은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the sidewall is formed of a nitride film. 제1항에 있어서, 상기 제5단계 실시 후, 열처리하여 이온주입된 상기 고농도 불순물층을 확산시키는 것을 특징으로 하는 반도체 소자방법.The semiconductor device method as claimed in claim 1, wherein after the fifth step, heat treatment is performed to diffuse the high concentration impurity layer into which the ion is implanted. 반도체 소자 제조방법에 있어서, 1) 반도체 기판위에 제1절연막과, 반도체층과, 제2절연막을 차례로 적층하는 단계와, 2) 상기 제2절연막을 선택식각하여 게이트 형성영역에 제2절연막을 잔류시키는 단계와, 3) 상기 제2절연막의 측면에 측벽을 형성하는 단계와, 4) 상기 제2절연막과 상기 측벽을 마스크로 상기 제1절연막이 드러나도록 식각한 후, 상기 제2절연막과 상기 측벽 및 상기 제1절연막의 표면에 얇은 산화막을 형성하는 단계와, 5) 상기 제2절연막과 측벽을 마스크로 상기 반도체 기판에 고농도의 이온을 주입하여 고농도 불순물 영역을 형성하는 단계와, 6) 상기 얇은 산화막 및 상기 측벽을 제거하고, 상기 제2절연막을 마스크로 상기 반도체층을 식각하여 게이트를 형성하는 단계와, 7) 상기 반도체 기판에 저농도의 이온을 주입하여 저농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.1. A method of manufacturing a semiconductor device, comprising: 1) stacking a first insulating film, a semiconductor layer, and a second insulating film on a semiconductor substrate in sequence; and 2) selectively etching the second insulating film to leave a second insulating film in a gate formation region. 3) forming sidewalls on side surfaces of the second insulating layer, and 4) etching the second insulating layer and the sidewalls to expose the first insulating layer using a mask, and then etching the second insulating layer and the sidewalls. And forming a thin oxide film on the surface of the first insulating film, 5) forming a high concentration impurity region by implanting a high concentration of ions into the semiconductor substrate using the second insulating film and the sidewall as a mask, and 6) the thin film. Removing the oxide layer and the sidewalls, and etching the semiconductor layer using the second insulating layer as a mask to form a gate; and 7) injecting low concentration ions into the semiconductor substrate to form a low concentration impurity. And forming a region. 제7항에 있어서, 상기 제1절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 7, wherein the first insulating layer is formed of an oxide film. 제7항에 있어서, 상기 반도체층은 다결정실리콘으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.8. The method of claim 7, wherein the semiconductor layer is formed of polycrystalline silicon. 제7항에 있어서, 상기 제2절연막은 산화막, 질화막 중 택일하여 사용하는 것을 특징으로 하는 반도체 소자 제조방법.8. The method of claim 7, wherein the second insulating film is one of an oxide film and a nitride film. 제7항에 있어서, 상기 측벽은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 7, wherein the sidewall is formed of a nitride film. 제7항에 있어서, 상기 제5단계 실시 후, 열처리하여 이온주입된 상기 고농도 불순물층을 확산시키는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 7, wherein after the fifth step is performed, the high concentration impurity layer implanted with ions is diffused. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029806A 1995-09-13 1995-09-13 Fabrication method of semiconductor device KR0156787B1 (en)

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