KR970023888A - Manufacturing method of MOS transistor - Google Patents

Manufacturing method of MOS transistor Download PDF

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Publication number
KR970023888A
KR970023888A KR1019950038679A KR19950038679A KR970023888A KR 970023888 A KR970023888 A KR 970023888A KR 1019950038679 A KR1019950038679 A KR 1019950038679A KR 19950038679 A KR19950038679 A KR 19950038679A KR 970023888 A KR970023888 A KR 970023888A
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South Korea
Prior art keywords
oxide film
mos transistor
forming
gate
silicon substrate
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KR1019950038679A
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Korean (ko)
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KR0154303B1 (en
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김현식
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

최근, 반도체의 고집적화에 따라서 반도체상의 개별소자도 작은 면적으로 형성해야 될 필요가 발생하게 되었다. 이에따라 미세한 모스 트랜지스터 구조를 형성하게 되면, 소오스, 드레인간의 채널길이가 축소되고, 이로인한 쇼트 채널 효과, 브레이크 다운전압에 의한 펀치 쓰루 현상의 원인이 되므로 본 발명에서는 게이트 구조를 웨이퍼의 표면 위치와 동일하게 맞춤으로써, 상기에서 설명한 바와 같은 문제점을 개선하고 또한, 불순물 이온 주입시에도 실리콘 기판상에 패드산화막을 형성하고 고농도와 저농도의 이온을 주입하므로써, 별도의 마스크 레이어가 필요치 않도록 설계하였고, 트렌치내에 희생 산화막을 형성하고 이를 마스크로하여 소오스와 드레인간의 채널영역에 불순물 이온을 주입하여 채널간 특성을 조절할 수 있도록 하였다.In recent years, with the high integration of semiconductors, it is necessary to form individual elements on a semiconductor with a small area. As a result, the formation of a fine MOS transistor structure reduces the channel length between the source and the drain, which causes a short channel effect and a punch through phenomenon due to the breakdown voltage. In order to solve the problems described above, the pad oxide film is formed on the silicon substrate and the high concentration and low concentration of ions are implanted even during impurity ion implantation, so that a separate mask layer is not required. The sacrificial oxide film was formed and impurity ions were implanted into the channel region between the source and the drain to control the interchannel characteristics.

Description

모스 트랜지스터의 제조방법Manufacturing method of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2G도는 본 발명의 방법에 의하여 모스 트랜지스터를 제조하는 공정도.2A to 2G are process diagrams for manufacturing a MOS transistor by the method of the present invention.

Claims (8)

실리콘 기판(21)상에 패드 산화막(22)을 형성하는 공정과, 실리콘 기판으로 고농도의 이온을 주입하여 고농도 불순물 영역으로 형성하는 공정과, LDD구조를 형성하기 위하여, 상기 실리콘 기판으로 저농도의 이온을 주입하여 저농도 불순물 영역으로 형성하는 공정과, 상기 패드 산화막상에 질화막(25), 저온 산화막(25)을 차례로 형성하는 공정과, 상기의 구조물상에 포토 레지스트막(27)을 도포하고, 포토 레지스트막(27)을 패터닝하는 공정과, 상기 구조물상에 게이트 형성 영역(G)을 한정하는 단계와, 상기의 포토 레지스트 패턴(27)을 식각 마스크로하여 저온 산화막(26), 질화막(25), 패드 산화막(22)을 동시에 선택적인 식각 공정으로 제거한 후, 상기 포토 레지스트 패턴(27)을 식각하여 제거하는 공정과, 게이트 형성 영역상의 실리콘 기판(21)을 식각하여 트렌치(29)를 형성하는 공정과, 상기 저온 산화막(26)을 식각하여 제거하는 공정과, 상기 트렌치 영역 상에 희생 산화막(28)을 형성하는 공정과, 상기 실리콘 기판의 전면에 절연막을 형성한 후, 이방성 식각을 통하여 트렌치(29)의 측벽에 스페이서(30)를 형성하는 공정과, 상기 희생 산화막(28)을 제거하고 게이트 산화막(32)을 형성하는 공정과, 실리콘 기판의 전면에 폴리 실리콘을 침적시키고 건식식각하여 게이트(33)를 형성하는 공정과, 상기 질화막(25), 패드 산화막(23)을 차례로 식각하여 제거한 후, 소오스, 드레인, 게이트상부에 실리사이드전극(34)을 형성하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.Forming a pad oxide film 22 on the silicon substrate 21, implanting a high concentration of ions into the silicon substrate to form a high concentration impurity region, and forming a LDD structure to form a low concentration ion in the silicon substrate Forming a low-concentration impurity region by injecting the oxide, forming a nitride film 25 and a low temperature oxide film 25 sequentially on the pad oxide film, applying a photoresist film 27 on the structure, and Patterning the resist film 27, defining a gate formation region G on the structure, and using the photoresist pattern 27 as an etching mask as the low temperature oxide film 26 and the nitride film 25. And simultaneously removing the pad oxide layer 22 by a selective etching process, and then etching and removing the photoresist pattern 27, and etching the silicon substrate 21 on the gate formation region to form a trench. Forming a sacrificial oxide film 28 on the trench region; forming an insulating film on the entire surface of the silicon substrate; Forming a spacer 30 on the sidewalls of the trench 29 through anisotropic etching; removing the sacrificial oxide layer 28 and forming a gate oxide layer 32; Immersing and dry etching to form the gate 33, and sequentially etching and removing the nitride film 25 and the pad oxide film 23, and then forming a silicide electrode 34 on the source, drain, and gate. The manufacturing method of a MOS transistor. 제1항에 있어서, 트렌치(29)의 측벽에 스페이서(30)를 형성한후, 펀치 쓰루 현상을 방지하기 위하여, 스페이서(30)를 마스크로 하여 실리콘 기판(21)으로 불순물 이온을 주입하는 공정을 특징으로 하는 모스 트랜지스터의 제조방법.The method of claim 1, wherein after the spacers 30 are formed on the sidewalls of the trenches 29, impurity ions are implanted into the silicon substrate 21 using the spacers 30 as masks to prevent punch through. Method for producing a MOS transistor characterized in that. 제2항에 있어서, 펀치 쓰루 현상을 방지하기 위한 불순물 이온을 주입한 후, 저농도 불순물 영역에 채널간의 특성을 조절하기 위한 이온을 주입하고 확산을 실시하여 게이트의 특성을 조절하는 공정을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of claim 2, wherein after implanting impurity ions for preventing punch through, implanting ions for adjusting characteristics between channels in a low concentration impurity region and performing diffusion to adjust the characteristics of the gate. Method for manufacturing MOS transistor. 제1항에 있어서, 패드산화막(22)의 두께는 200∼500Å이고, 질화막(25)의 두께는 500∼2000Å인 것과, 저온 산화막(26)의 두께는 2000∼7000Å인 것을 특징으로 하는 모스트랜지스터의 제조 방법.The MOS transistor according to claim 1, wherein the thickness of the pad oxide film 22 is 200 to 500 kPa, the thickness of the nitride film 25 is 500 to 2000 kPa, and the low-temperature oxide film 26 is 2000 to 7000 kPa. Method of preparation. 제1항에 있어서, 저온 산화막(26)을 버퍼로 하여 실리콘 기판(21)을 0.05~1.0㎛의 두께로 식각하여 트렌치(29)을 형성하는 것을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of manufacturing a MOS transistor according to claim 1, wherein the trench (29) is formed by etching the silicon substrate (21) to a thickness of 0.05 to 1.0 mu m with the low temperature oxide film (26) as a buffer. 제1항에 있어서, 게이트 산화막(32)의 두께는 50~300Å이고, 상기 게이트(33)의 두께는 1000~5000Å인 것을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of manufacturing a MOS transistor according to claim 1, wherein the gate oxide film (32) has a thickness of 50 to 300 kPa, and the gate (33) has a thickness of 1000 to 5000 kPa. 제1항에 있어서, 스페이서 절연막을 사용하지 않고 고농도 이온 주입을 실시하는 것을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of manufacturing a MOS transistor according to claim 1, wherein high concentration ion implantation is performed without using a spacer insulating film. 제1항에 있어서, 게이트(33)의 상부를 실리콘 표면과 일치시켜 후속 공정에서 평탄화 공정은 용이하게 실시하는 것을 특징으로 하는 모스 트랜지스터의 제조 방법.The method of manufacturing a MOS transistor according to claim 1, wherein the top of the gate (33) is aligned with the silicon surface so that the planarization process is easily performed in a subsequent process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038679A 1995-10-31 1995-10-31 Method of fabricating mosfet KR0154303B1 (en)

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KR0154303B1 KR0154303B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465055B1 (en) * 2001-12-29 2005-01-05 매그나칩 반도체 유한회사 Method of manufacturing a transistor in a semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525114B1 (en) * 1998-12-15 2006-01-12 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
KR20030050995A (en) * 2001-12-20 2003-06-25 동부전자 주식회사 Method for fabricating high-integrated transistor
KR100679829B1 (en) * 2005-12-29 2007-02-06 동부일렉트로닉스 주식회사 Method for fabricating transistor of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465055B1 (en) * 2001-12-29 2005-01-05 매그나칩 반도체 유한회사 Method of manufacturing a transistor in a semiconductor device

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