KR20000004367A - Method for manufacturing mos field effect transistors - Google Patents

Abstract

PURPOSE: A fabrication method of an MOS field effect transistor having an LDD(lightly doped drain) structure is provided to prevent downing of threshold voltage and remove trade-off between punch-through voltage and conductivity by using double gate polysilicon and a native oxide. CONSTITUTION: The method comprises the steps of: forming a gate oxide(12) on a silicon substrate(10); forming a first polysilicon layer(14) on the gate oxide(12); growing a native oxide(16) on the first polysilicon layer(14); forming a second polysilicon layer(18) having thick thickness compared to the first polysilicon layer on the native oxide(16); exposing a portion of the first polysilicon layer(14); forming a lightly doped impurity region(22a,22b) by ion-implantation into the exposed polysilicon layer; forming a spacer(24) at both sides of the native oxide and the polysilicon layers; exposing a portion of the lightly doped impurity region(22a,22b) by blanket etching the exposed first polysilicon(14); forming an SELOCS(SELective Oxide Coating of Silicon-gate) oxide(26) at sides of the first polysilicon layer(14a); and forming highly doped impurity regions(28a,28b).

Description

Manufacturing method of MOS field effect transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technology of MOS field effect transistors, and more particularly, to a method of manufacturing a MOS field effect transistor having a LDD (Lightly Doped Drain / Source) using a natural oxide film.

As semiconductor devices are highly integrated, the formation of short channel transistors is essential. For this reason, the characteristics of a hot carrier and a punch through deteriorate. In order to solve this problem and to obtain high reliability, a transistor employing a double diffused drain (DDD) or a lightly doped drain (LDD) has been proposed. However, the drain structure of the transistor can prevent the drop of the hot carrier and the threshold voltage, but there is a problem that there is a trade off between the punch-through voltage and the transfer conductivity.

Accordingly, it is an object of the present invention to solve such a problem and to provide a method for producing a MOS field effect transistor having high reliability.

In order to achieve the object of the present invention, the gate polysilicon is formed on the secondary, and after forming the first gate polysilicon, a natural oxide film is formed and a second gate polysilicon is formed on the natural oxide film.

1 to 4 are cross-sectional views illustrating steps in manufacturing a MOS field effect transistor according to the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

In Fig. 1, an oxide film 12 is formed on the P-type substrate 10 by a known method. A 50 nm first polysilicon layer 14 is formed over the oxide film 12. Thereafter, the natural oxide film 14 of about 5 to 10 kPa is grown by air curing. The natural oxide layer 14 may be sufficient to serve as an etch stop layer during etching of the second polysilicon layer formed thereafter. The second polysilicon layer 18 is formed on the natural oxide layer 16 to complete the gate poly. Subsequently, a first insulating layer 20 is formed on the second polysilicon layer 18.

In FIG. 2, the second polysilicon layer 18 is patterned using dry etching with high selectivity, so that the second polysilicon layer 18 in the portion exposed by the insulating layer 20 is removed to obtain a thin first. Together with the polysilicon layer 14, 16a and 18a are also left. Next, phosphorus ions are implanted into the substrate using the first insulating layer as a mask to form the low concentration impurity layers 22a and 22b. The phosphorus ion implantation process uses about 80 Kev energy in consideration of the first polysilicon layer 14.

In Fig. 3, a second insulating layer 24, which is a spacer, is formed on the resultant product in which the low concentration impurity layers 22a and 22b are formed. The second insulating layer 24 is formed on the side surfaces of the first insulating layer 20, the first and second polysilicon layers, and the natural oxide film 16. The second insulating layer is composed of nitride or oxide. A portion of the impurity layer is exposed by blanket etching the first polysilicon layer 12 exposed by the second insulating layer 24 without adding a mask. A SELOCS (Selective Oxide Coating of Silicon-gate) oxide layer 26 is formed on the side of the first polysilicon layer 14a to control the overlap length between the impurity layer (source and drain) and the gate poly.

In FIG. 4, n type impurity, especially As ion, is ion-implanted to the board | substrate 10 using the said 2nd insulating layer 24, and high concentration impurity regions 28a and 28b are formed. The impurity concentration of the low concentration impurity regions 22a and 22b is lower than that of the high concentration impurity regions 28a and 28b. Therefore, the source and drain regions of the transistor are LDD structures each composed of high concentration impurity regions 28a and 28b and low concentration impurity regions 22a and 22b.

In this embodiment, the gate polysilicon is deposited in two steps to form a natural oxide film between the first gate polysilicon layer and the second gate polysilicon layer. This natural oxide film selectively etches and patternes the second polysilicon. Next, phosphorus ions are implanted to form a low concentration impurity layer to suppress hot carriers injected into the gate oxide film and the spacer. In addition, the coupling ratio between the electric field of the drain and the electron-hole is reduced to suppress the short channel effect. That is, it is possible to prevent the drop in the threshold voltage and to improve the transfer conductivity and the punch through voltage characteristics.

Claims (5)

Forming a gate oxide film on the substrate, Forming a first polysilicon layer on the gate oxide layer, Forming a natural oxide film on the first polysilicon layer, Forming a second polysilicon layer thicker than the first polysilicon layer on the oxide film, Forming a first insulating layer on the second polysilicon layer, Etching a predetermined portion of the second polysilicon layer using the first insulating layer as a mask to expose a portion of the first polysilicon layer, Implanting phosphorus ions into the exposed first polysilicon layer to form a low concentration impurity region, Forming a spacer by forming and etching a second insulating layer on the entire surface of the resultant impurity region having low concentration, Performing an etching process on the entire surface of the substrate using the first insulating layer and the spacer as a mask; Forming a SELOS (SELECTive Oxide Coating of Silicon-gate) oxide film on the side of the first polysilicon layer, and And ion-implanting impurities of the same type as the first impurity region on the entire surface of the resultant on which the SELOS oxide film is formed to form a high concentration impurity region. 10. The method of claim 1, wherein the native oxide film is about 5-10 kV. 2. The method of claim 1, wherein the thickness of the first polysilicon layer is about 50 nm. The method of claim 1, wherein the second polysilicon layer is dry etched and the first polysilicon layer is wet etched. The method of claim 1, wherein the second insulating layer is nitride or oxide.