KR0125296B1 - Fabrication method of mosfet - Google Patents

Abstract

There is provided a method for fabricating a MOSFET having an increased effective channel length. The method includes: forming a semiconductor substrate(1) having a projected portion; depositing a gate oxide layer and a polysilicon layer(3) in the named order on the substrate(1); forming a LDD region at both side of the projected portion of the substrate(1); forming a silicide layer(7) on the polysilicon layer(3); forming a spacer(5) at side walls of the projected portion by depositing a low temperature oxide layer on the silicide layer(7) and performing an anisotropic blanket etch; removing the silicide layer and the polysilicon layer on the substrate except the projected portion and adjacent portion thereof; and forming source/drain regions in the substrate.

Description

MOSFET manufacturing method

1 is a cross-sectional view of manufacturing a MOSFET by a conventional technique.

Figures 2a to 2d shows a step of manufacturing a MOSFET having an increased channel length in accordance with the present invention

Cross-section.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 gate oxide film

3: polysilicon layer for gate electrode

4: LDD region (Lightly Droped Drain Region)

5: oxide spacer

3 ': polysilicon layer pattern for gate electrode

6 source / drain region 7 silicide

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOSFET in a semiconductor device, and more particularly, to a method for manufacturing a MOSFET having an increased channel length and a self-aligned polyside structure.

As semiconductor devices have been highly integrated, gate electrodes having self-aligned polycide structures have been developed.

A MOSFET having a polyside structure manufactured by a conventional technique will be described with reference to FIG. After sequentially stacking the gate oxide film 2 and the polysilicon layer 3 on the semiconductor substrate 1, a polysilicon pattern for the gate electrode is formed through a lithography process, and ion implantation of low concentration impurities into the substrate is used to form an LDD region ( 4), an oxide spacer 5 is formed on the sidewalls of the gate electrode, and ion source implanted into the substrate to form a source / drain region 6, and then the polysilicon layer 3 is formed by selective deposition. The silicide 7 is formed in the source / drain region 6.

As the MOSFET formed by the above process is highly integrated, the channel length is shortened, and thus the electrical characteristics of the MOSFET are deteriorated due to the decrease of the threshold voltage V _T , the breakdown voltage V _BD , and the increase of the substrate current.

The present invention is to increase the channel length of the MOSFET in order to solve the above problems.

According to the MOSFET according to the present invention, a predetermined portion of the semiconductor substrate is formed to have a protruding structure, and a gate oxide film and a polysilicon pattern for the gate electrode are provided to enclose the protruding semiconductor substrate, and the polysilicon for the gate electrode is provided. The LDD region and the source / drain regions are provided on the semiconductor substrate under the edges of both sides of the pattern, and the silicide is provided on the polysilicon pattern for the gate electrode.

According to the method for manufacturing a MOSFET according to the present invention, an oxide film is formed on an upper portion of a semiconductor substrate, a photosensitive film pattern is formed on the upper portion thereof, and a semiconductor substrate having a protruding shape is formed by etching a predetermined thickness of the exposed oxide film and a lower portion of the semiconductor substrate. Forming an LDD region by removing the photoresist pattern and the oxide film, laminating a gate oxide film and a polysilicon layer as a whole, and ion implanting low concentration impurities into semiconductor waves on both sides of the protrusion; Forming a silicide layer on the silicon layer, forming a low temperature oxide layer on the silicide layer, and etching anisotropic blanket to form an oxide spacer on the sidewall of the polysilicon layer for the gate electrode; Silicide for gate electrode by etching so that polysilicon layer remains Forming a film pattern and a polysilicon layer pattern, and ion implanting a high concentration of impurities into the semiconductor substrate to form a source / drain region.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2a to 2d is a cross-sectional view showing a process step of manufacturing a MOSFET with an increased channel length in accordance with the present invention.

FIG. 2A shows an oxide film 8 having a thickness of 100-500 kV over the semiconductor substrate 1, a photoresist pattern 9 formed thereon, and an oxide film 8 and a semiconductor substrate 1 below it by an etching process. ) Is a cross-sectional view of a semiconductor substrate 1 having a projecting structure by etching a predetermined thickness. The oxide film 8 can be grown by a thermal process.

FIG. 2B shows that after removing the photoresist pattern 9, the oxide layer 8 is removed by HF and ion implanted into the semiconductor substrate 1 to control the threshold voltage V _T. A cross-sectional view in which a lightly doped drain (LDD) region 4 is formed by stacking a doped polysilicon layer 3 for a gate electrode on the semiconductor substrate 1 and then implanting low-concentration impurities into the semiconductor substrate 1 inclinedly. to be.

FIG. 2C is a cross-sectional view of the silicide film 7 formed on the gate electrode silicide film 3 by depositing a transition metal (not shown) on the entire structure and performing high temperature heat treatment.

2d illustrates an oxide spacer 5 formed on a sidewall of a polysilicon layer 3 for gate electrode by forming a low temperature oxide layer on the silicide layer 7 and anisotropic blanket etching to enclose the protrusion of the substrate. The film 7 and the polysilicon layer 3 underneath thereof are sequentially photographed to form a gate electrode silicide film 7 pattern and a polysilicon layer pattern 3 'that are sequentially stacked. Is a cross-sectional view where the source / drain regions 6 are formed by ion implantation into the semiconductor substrate 1.

According to the present invention described above, the effective channel length reduced by the high integration of the semiconductor device is extended, and silicide is formed on the surface of the gate electrode, thereby improving the electrical characteristics of the MOSFET.

Claims (3)

Forming an oxide film on the semiconductor substrate, forming a photoresist pattern on the upper portion of the semiconductor substrate, etching a predetermined thickness of the exposed oxide film and the lower semiconductor substrate to form a protruding semiconductor substrate, the photoresist pattern and the oxide film Forming a LDD region by ion implanting low-concentration impurities into the semiconductor substrates on both sides of the protrusions, and forming a silicide film on the polysilicon layer; Forming a low-temperature oxide film on the silicide layer and etching anisotropic blanket to form an oxide spacer on the sidewall of the polysilicon layer for the gate electrode, and etching by leaving the silicide surrounding the protrusion and the polysilicon layer below the gate. Forms the silicide film pattern and the polysilicon layer pattern for electrodes , By implanting high-concentration impurities into the semiconductor substrate MOSFET manufacturing method including forming source / drain regions. The method of claim 1, wherein the implant of the low concentration impurity is implanted at an angle with respect to the semiconductor substrate. The method of claim 1, wherein the impurity for adjusting the threshold voltage is implanted into the semiconductor substrate before the gate oxide layer is formed.