KR100337200B1 - Method for forming mosfer - Google Patents
Method for forming mosfer Download PDFInfo
- Publication number
- KR100337200B1 KR100337200B1 KR1019940028188A KR19940028188A KR100337200B1 KR 100337200 B1 KR100337200 B1 KR 100337200B1 KR 1019940028188 A KR1019940028188 A KR 1019940028188A KR 19940028188 A KR19940028188 A KR 19940028188A KR 100337200 B1 KR100337200 B1 KR 100337200B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- forming
- trench
- semiconductor substrate
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 모스펫 ( MOSFET : Metal Oxide Semiconductor Field Effect Transistor. 이하에서 모스펫이라 함 ) 형성방법에 관한 것으로 특히 반도체기판에서 활성영역의 일정부분을 식각하여 트렌치를 형성하고 트렌치를 매립하는 게이트전극이 형성된 구조의 모스펫을 형성함으로써 반도체소자의 고집적화를 가능하게 한다.The present invention relates to a method of forming a MOSFET (MOSFET), and in particular, a structure in which a gate electrode is formed by etching a portion of an active region in a semiconductor substrate to form a trench and fill a trench. By forming a MOSFET, high integration of the semiconductor device is possible.
종래기술은 반도체기판 활성영역의 일부에 게이트전극을 형성하고 이를 이용하여 엘.디.디. ( LDD : lightly doped drain ) 구조의 소오스/트레인 확산영역을 형성함으로써 모스펫을 형성하였다.The prior art forms a gate electrode on a part of an active region of a semiconductor substrate and uses the L.D.D. The MOSFET was formed by forming a source / train diffusion region having a lightly doped drain (LDD) structure.
그러나, 반도체소자 고집적화됨에따라 소오스 확산영역과 트레인 확산영역이 형성하는 채널의 길이가 짧아져 반도체소자의 특성을 열화시켜 반도체소자의 신뢰성을 저하시키는 문제점이 있다.However, as semiconductor devices become highly integrated, the lengths of the channels formed by the source diffusion region and the train diffusion region are shortened, thereby deteriorating the characteristics of the semiconductor element, thereby reducing the reliability of the semiconductor element.
따라서, 본 발명은 반도체기판 활성영역의 게이트전극이 형성될 부분에 트렌치를 형성하고 트렌치 상부에 게이트한화막, 게이트전극, 절연막 스페이서 및 소오스 트레인 확산영역을 순차적으로 형성함으로써 반도체소자의 고집적화로인한 쇼트채널( short chaanel )에 의하여 발생하는 문제점을 방지할 수 있는 모스펫 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a trench in a portion where the gate electrode of the semiconductor substrate active region is to be formed, and sequentially forms a gate limiting film, a gate electrode, an insulating film spacer, and a source train diffusion region on the trench, resulting in high integration of the semiconductor device. It is an object of the present invention to provide a method for forming a MOSFET capable of preventing a problem caused by a channel (short chaanel).
이상의 목적을 달성하기위한 모스펫 형성방법은,MOSFET forming method for achieving the above object,
게이트전극 영역으로 예정된 부분 내측의 반도체기판에 트렌치를 형성하는 공정과,Forming a trench in the semiconductor substrate inside the portion defined as the gate electrode region;
상기 트렌치를 포함한 전체표면상부에 게이트산화막을 형성하는 공정과,Forming a gate oxide film over the entire surface including the trench;
상기 게이트산화막 상에 게이트전극용 다결정실리콘막을 형성하는 공정과,Forming a polysilicon film for a gate electrode on the gate oxide film;
게이트전극 마스크를 이용한 노광 및 현상공정으로 감광막패턴을 형성하고 이를 마스크로 하여 상기 게이트전극용 다결정실리콘막과 게이트산화막을 식각함으로써 게이트전극을 형성하는 공정과,Forming a photoresist pattern by an exposure and development process using a gate electrode mask, and forming a gate electrode by etching the polysilicon film and the gate oxide film for the gate electrode using the photoresist pattern as a mask;
상기 게이트전극을 마스크로 하여 상기 반도체기판에 저농도의 분순물을 주입함으로써 저농도의 불순물 확산영역을 형성하는 공정과,Forming a low concentration impurity diffusion region by injecting a low concentration impurity into the semiconductor substrate using the gate electrode as a mask;
상기 게이트전극 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on the sidewalls of the gate electrode;
상기 게이트전극 절연막 스페이서를 마스크로하여 상기 반도체기판에 고농도의 불순물을 이온주입함으로써 고농도의 불순물 확산영역을 형성하는 공정을 포함하는 것을 제1특징으로 하며,And a step of forming a high concentration impurity diffusion region by ion implanting a high concentration of impurities into the semiconductor substrate using the gate electrode insulating spacer as a mask.
게이트 전극 영역의 반도체기판에 트렌치를 형성하는 공정과,Forming a trench in the semiconductor substrate in the gate electrode region;
상기 트렌치를 포함한 전체표면상부에 게이트산화막을 형성하는 공정과,Forming a gate oxide film over the entire surface including the trench;
상기 게이트산화막상에 게이트전극용 제1다결정실리콘막을 형성하되, 상기 트렌치 상측부의 제1다결정실리콘막이 타 부분보다 두껍게 형성되는 공정과,Forming a first polycrystalline silicon film for a gate electrode on the gate oxide film, wherein the first polycrystalline silicon film in the upper portion of the trench is formed thicker than another portion;
상기 반도체기판이 노출될때까지 상기 제1다결정실리콘막을 에치백하되, 상기 트렌치 상측부의 제1다결정실리콘막이 상기 트렌치 내측으로 오목한 구조로 구비되는 공정과,Etching back the first polysilicon layer until the semiconductor substrate is exposed, wherein the first polysilicon layer in the upper portion of the trench is concave inside the trench;
전체표면상부에 게이트전극용 제2다결정실리콘막을 형성하되, 상기 트렌치 상측부의 제2다결정실리콘막이 타 부분보다 두껍게 형성되는 공정과,Forming a second polysilicon film for the gate electrode on the entire surface, wherein the second polysilicon film in the upper portion of the trench is formed thicker than the other parts;
상기 반도체 기관이 노출될때까지 상기 제2다결정실리콘막을 에치백하되, 상기 트렌치 상측부의 제2다결정실리콘막이 반도체기판과 평탄한 구조로 구비되어 제1,2다결정실리콘막으로 게이트전극을 형성하는 공정과,Etching the second polycrystalline silicon film until the semiconductor engine is exposed, wherein the second polycrystalline silicon film in the upper portion of the trench is formed in a flat structure with the semiconductor substrate to form a gate electrode with the first and second polycrystalline silicon films;
전체표면상부에 저농도의 불순물을 이온주입하여 저농도의 불순물 확산영역을 형성하는 공정과,Forming a low concentration impurity diffusion region by implanting a low concentration of impurities onto the entire surface;
상기 게이트전극보다 양측의 반도체기판에 중첩되는 감광막패턴을 상기 게이트전극 상부에 형성하는 공정과,Forming a photoresist pattern on the gate electrode, the photoresist pattern overlapping the semiconductor substrate on both sides of the gate electrode;
상기 감광막패턴을 마스크로하여 상기 반도체기판에 고농도의 불순물을 이온 주입함으로써 고농도의 불순물 확산영역을 형성하는 공정과,Forming a high concentration impurity diffusion region by ion implanting a high concentration of impurities into the semiconductor substrate using the photoresist pattern as a mask;
상기 감광막패턴을 제거하는 공정을 포함하는 것을 제2특징으로 한다.It is a 2nd characteristic that it includes the process of removing the said photosensitive film pattern.
이하, 첨부된 도면을 참고로하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1A도 내지 제1C도는 본 발명의 제1실시예에 따른 모스펫 형성공정을 도시한 단면도이다.1A to 1C are cross-sectional views showing a MOSFET forming process according to a first embodiment of the present invention.
제1A도를 참조하면, 반도체기판(11) 활성영역에서 게이트전극이 형성되는 부분에 트렌치(13)를 형성한다. 이때, 트렌치(13)의 깊이는 0.1 내지 0.2㎛ 로 한다. 그 다음, 전표면상부에 게이트산화막(15)을 형성한다. 그리고, 게이트산화막(15) 상부에 게이트전극용 다결정실리콘막(17)을 형성한다.Referring to FIG. 1A, the trench 13 is formed in a portion where the gate electrode is formed in the active region of the semiconductor substrate 11. At this time, the depth of the trench 13 shall be 0.1-0.2 micrometer. Next, a gate oxide film 15 is formed over the entire surface. Then, a polysilicon film 17 for a gate electrode is formed on the gate oxide film 15.
그리고, 다결정실리콘막(17) 상부에 게이트전극을 형성하기위한 감광막패턴(19)을 형성한다. 이때, 감광막패턴(19)은 상기 트렌치의 양측 상부에 0.1 내지 0.2 ㎛ 폭으로 중첩시켜 형성한다.Then, a photosensitive film pattern 19 for forming a gate electrode is formed on the polysilicon film 17. At this time, the photoresist layer pattern 19 is formed by overlapping the upper side of the trench in a width of 0.1 to 0.2 μm.
제1B도를 참조하면,상기 감광막패턴(19)을 마스크로 하여 게이트전극용 다결정실리콘막(17)과 게이트산화막(15)을 순차적으로 식각하여 게이트전극(21)과 게이트산화막(15)패턴을 형성한다. 이때, 상기 게이트전극(21)은 트렌치(13) 양측 상부에 0.1 내지 0.2 ㎛ 중첩되도록 형성된다. Referring to FIG. 1B, the gate electrode 21 and the gate oxide film 15 patterns may be sequentially etched by sequentially etching the gate silicon polycrystalline film 17 and the gate oxide film 15 using the photoresist pattern 19 as a mask. Form. In this case, the gate electrode 21 is formed to overlap 0.1 to 0.2 μm on both sides of the trench 13.
그 다음, 감광막패턴(19)을 제거한다. 그리고 게이트전극(21)을 마스크로하여 저농도의 불순물을 이온주입함으로써 저농도의 소오스/트레인 확산영역(23)을 형성한다.Then, the photoresist pattern 19 is removed. A low concentration source / train diffusion region 23 is formed by ion implanting impurities of low concentration using the gate electrode 21 as a mask.
제1C도를 참조하면, 게이트전극(21) 측벽에 절연막 스페이서(25)를 형성한다. 그후, 게이트전극(21)과 절연막 스페이서(25)를 마스크로하여 반도체기판(11)에 고농도의 불순물을 이온주입함으로써 고농도의 불순물 확산영역(27)을 형성한다.Referring to FIG. 1C, an insulating film spacer 25 is formed on sidewalls of the gate electrode 21. Thereafter, a high concentration of impurity diffusion region 27 is formed by ion implanting a high concentration of impurities into the semiconductor substrate 11 using the gate electrode 21 and the insulating film spacer 25 as a mask.
여기서, 상기 고농도의 불순물을 확산영역(27)의 깊이는 0.2 내지 0.3 ㎛ 로 형성하여 상기 트렌치(13)에 형성된 상기 게이트전극(21)보다 0.1 내지 0.01 ㎛ 깊게 형성된다.In this case, the dopant having a high concentration is formed to have a depth of 0.2 to 0.3 μm, and thus 0.1 to 0.01 μm deeper than the gate electrode 21 formed in the trench 13.
제2A도 내지 제 2F도는 본 발명의 제2실시예에 따른 모스펫 형성공정을 도시한 단면도이다.2A to 2F are cross-sectional views showing a MOSFET forming process according to a second embodiment of the present invention.
그 다음, 전표면상부에 게이트산화막(35)을 형성한다.Next, a gate oxide film 35 is formed over the entire surface.
제2B도를 참조하면, 상기 트렌치(33)를 매립하는 게이트전극용 제1다결정실리콘막(37)을 전체표면상부에 형성한다.Referring to FIG. 2B, a first polycrystalline silicon film 37 for gate electrodes filling the trench 33 is formed over the entire surface.
이때, 상기 제1다결정실리콘막(37)은 상기 트렌치(33)로 인하여 상기트렌치(33) 상측에서 오목한 구조로 형성된다.In this case, the first polysilicon layer 37 is formed to have a concave structure on the trench 33 due to the trench 33.
제2C도를 참조하면, 상기 게이트전극용 제1다결정실리콘막(37)을 에치백 (etch back ) 한다. 이때, 상기 에치백 공정은 상기 트렌치(33)을 제외한 상기 반도체기판(31) 상부에 형성된 게이트전극용 제1다결정실리콘막(37)을 모두 식각할 수 있도록 실시한 것이다. 이로인하여, 상기 게이트전극용 제1다결정실리콘막(37)으로 상기 트렌치(33)가 매립되되, 상기 트렌치(33) 상측의 오목한 구조로 인하여 완전히 매립되지 않은 구조로 형성된다.Referring to FIG. 2C, the first polysilicon layer 37 for the gate electrode is etched back. In this case, the etch back process may be performed to etch all of the first polycrystalline silicon film 37 for gate electrodes formed on the semiconductor substrate 31 except for the trench 33. As a result, the trench 33 is filled in the first polysilicon film 37 for the gate electrode, but the trench 33 is not completely embedded due to the concave structure on the upper side of the trench 33.
그리고 전표면상부에 게이트전극용 제2다결정실리콘막(39)을 일정두께 형성한다. 이때, 상기 게이트전극용 제2다결정실리콘막(39)은 상기 트렌치(33) 내에서 상기 제1다결정실리콘막(37)에 의하여 형성된 오목한 부분 상측에서 오목한 형태로 형성된다.Then, a second polycrystalline silicon film 39 for gate electrodes is formed on the entire surface. In this case, the second polysilicon film 39 for the gate electrode is formed in a concave shape on the concave portion formed by the first polycrystalline silicon film 37 in the trench 33.
제2D도를 참조하면, 상기 게이트전극용 제2다결정실리콘막(39)을 에치백하여 반도체기판(31) 상부를 평탄화시킴으로써 상기 트렌치(33)를 매립하는 게이트전극(41)을 형성한다. 여기서, 상기 게이트전극(41)은 상기 트렌치(33)와의 계면에 게이트산화막(35)이 구비된다.Referring to FIG. 2D, the gate electrode 41 filling the trench 33 is formed by etching back the second polysilicon layer 39 for the gate electrode to planarize the upper portion of the semiconductor substrate 31. Here, the gate electrode 41 is provided with a gate oxide film 35 at an interface with the trench 33.
이때, 상기 에치백 공정은 상기 트렌치(33)를 제외한 상기 반도체기판(31) 상부의 게이트전극용 제2다결정실리콘막(39)을 모두 식각할 수 있도록 실시하여 상기 트렌치(33)를 제1,2다결정실리콘막(37,39)으로 완전히 매립한 것이다.At this time, the etch back process is performed to etch all of the second polycrystalline silicon film 39 for the gate electrode on the semiconductor substrate 31 except for the trench 33. It is completely embedded in the two polysilicon films 37 and 39.
그 다음, 상기 반도체기판(31)에 저농도의 불순물을 이온주입하여 저농도의 불순물 확산영역(43)을 형성한다.Next, a low concentration of impurity diffusion region 43 is formed by ion implanting impurities of low concentration into the semiconductor substrate 31.
제2E도를 참조하면, 상기 트렌치(33) 상부에 감광막패턴(45)을 형성한다. 이때, 상기 감광막패턴(45)은 상기 트렌치(33)보다 크게 형성되어 상기 트렌치(33) 주변의 반도체기판(31)에 중첩되게 형성된 것이다.Referring to FIG. 2E, a photoresist pattern 45 is formed on the trench 33. In this case, the photoresist pattern 45 is formed to be larger than the trench 33 and overlaps the semiconductor substrate 31 around the trench 33.
그리고, 상기 감광막패턴(45)을 마스크로하여 고농도의 불순물을 이온주입함으로써 상기 반도체기판(31)에 고농도의 불순물 확산영역(47)을 형성한다.A high concentration of impurity diffusion region 47 is formed in the semiconductor substrate 31 by ion implantation of a high concentration of impurities using the photosensitive film pattern 45 as a mask.
제2F도를 참조하면, 제2E도 공정후에 상기 감광막패턴(45)을 제거하여 상부면이 평탄한 모스펫을 형성한다.Referring to FIG. 2F, after the process of FIG. 2E, the photoresist pattern 45 is removed to form a MOSFET having a flat top surface.
이상에서 설명한 바와같이 본 발명에 따른 모스펫 형성방법은, 소오스 확산 영역과 트레인 확산영역 사이에 형성된 게이트산화막과 게이트전극이 장벽역활을하여 고집적화로 인하여 발생할 수 있는 반도체소자의 특성열화를 방지함으로써 반도체소자의 신뢰성을 향상시킬 수 있는 잇점이 있다.As described above, in the method for forming a MOSFET according to the present invention, the gate oxide film and the gate electrode formed between the source diffusion region and the train diffusion region act as a barrier to prevent deterioration of characteristics of the semiconductor device that may occur due to high integration. There is an advantage to improve the reliability of.
제 1A 도 내지 제 1C 도는 본 발명의 제1실시예에 따른 모스펫 형성공정을 도시한 단면도.1A to 1C are cross-sectional views showing a MOSFET forming process according to a first embodiment of the present invention.
제 2A 도 내지 제 2F 도는 본 발명의 제2실시예에 따른 모스펫 형성공정을 도시한 단면도.2A to 2F are cross-sectional views showing a MOSFET forming process according to a second embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 트렌치11,31: semiconductor substrate 13,33: trench
15,35 : 게이트산화막15,35: gate oxide film
17 : 게이트전극용 다결정실리콘막17 polycrystalline silicon film for the gate electrode
19,45 : 감광막패턴 21,41 : 게이트 전극19,45 photoresist pattern 21,41 gate electrode
23,43 : 저농도의 불순물 확산영역23,43: low concentration impurity diffusion region
25 : 절연막 스페이서25: insulating film spacer
27,47 : 고농도의 불순물 확산영역27,47: high concentration of impurity diffusion
37 : 게이트전극용 제1다결정실리콘막37: first polysilicon film for the gate electrode
39 : 게이트전극용 제2다결정실리콘막39 second polysilicon film for the gate electrode
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940028188A KR100337200B1 (en) | 1994-10-31 | 1994-10-31 | Method for forming mosfer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940028188A KR100337200B1 (en) | 1994-10-31 | 1994-10-31 | Method for forming mosfer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960015813A KR960015813A (en) | 1996-05-22 |
KR100337200B1 true KR100337200B1 (en) | 2002-11-23 |
Family
ID=37479979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940028188A KR100337200B1 (en) | 1994-10-31 | 1994-10-31 | Method for forming mosfer |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100337200B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100781450B1 (en) | 2006-10-27 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for forming the polysilicon gate electrode having trench structure |
-
1994
- 1994-10-31 KR KR1019940028188A patent/KR100337200B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100781450B1 (en) | 2006-10-27 | 2007-12-03 | 동부일렉트로닉스 주식회사 | Method for forming the polysilicon gate electrode having trench structure |
Also Published As
Publication number | Publication date |
---|---|
KR960015813A (en) | 1996-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100610465B1 (en) | Method for fabricating semiconductor device | |
KR100272527B1 (en) | Semiconductor device and method for fabricating the same | |
US5817563A (en) | Method for fabricating an LDD transistor | |
US20040217417A1 (en) | High voltage device and method for fabricating the same | |
KR0150105B1 (en) | Method of fabricating transistor of semiconductor device | |
JP3360064B2 (en) | Method for manufacturing semiconductor device | |
KR20040002204A (en) | Semiconductor device and method for manufacturing the same | |
KR100337200B1 (en) | Method for forming mosfer | |
KR100873356B1 (en) | Method for forming the high voltage transistor | |
JP3049496B2 (en) | Method of manufacturing MOSFET | |
KR100227644B1 (en) | Manufacturing method of a transistor | |
KR20000031366A (en) | Semiconductor device and production method thereof | |
KR100298874B1 (en) | Method for forming transistor | |
KR100320436B1 (en) | Method for manufacturing mosfet | |
KR20000060696A (en) | Method for manufacturing semiconductor device the same | |
KR100756815B1 (en) | Method for manufacturing a transistor | |
KR101068137B1 (en) | Method for manufacturing high voltage transistor | |
KR20040002211A (en) | Semiconductor device and method for fabricating the same | |
KR0125296B1 (en) | Fabrication method of mosfet | |
KR100905165B1 (en) | A method for forming a transistor of a semiconductor device | |
KR100257756B1 (en) | Method for manufacturing mosfet | |
KR100197987B1 (en) | Method of manufacturing drain transistor | |
KR0125297B1 (en) | Fabrication method of mosfet | |
KR100609541B1 (en) | Forming method for transistor of semiconductor device | |
KR0135670B1 (en) | Method of manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110429 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |