KR100257756B1 - Method for manufacturing mosfet - Google Patents

Method for manufacturing mosfet Download PDF

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KR100257756B1
KR100257756B1 KR1019970075044A KR19970075044A KR100257756B1 KR 100257756 B1 KR100257756 B1 KR 100257756B1 KR 1019970075044 A KR1019970075044 A KR 1019970075044A KR 19970075044 A KR19970075044 A KR 19970075044A KR 100257756 B1 KR100257756 B1 KR 100257756B1
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region
forming
gate electrode
semiconductor substrate
film
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KR19990055132A (en
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황준
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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  • Power Engineering (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

PURPOSE: A manufacturing method of MOS(metal-oxide- semiconductor) transistor is provided to prevent lowering of element characteristics due to the source-drain serial resistance and floating body effect by using a newly deposited polysilicon and bulk plate as a joining region. CONSTITUTION: A gate region is exposed on a semiconductor plate(21) by selectively removing nitride film(23). Ion is injected at the bottom of a channel region located at below the gate region to form a filled insulation film. The nitride film(23) is removed after a gate electrode is formed. A source region and a drain region are formed at each side of the gate electrode. The filled insulation film may be formed with an oxidation film.

Description

모스트랜지스터 제조 방법Most transistor manufacturing method

본 발명은 반도체 장치 및 그 제조 방법에 관한 것으로 특히, 소오스/드레인간의 직렬 저항 및 단채널 효과를 감소할 수 있는 모스트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a MOS transistor capable of reducing the series resistance and short channel effects between a source and a drain.

0.05 ㎛ 이하의 크기를 갖는 고집적 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)에서는 단채널 효과를 억제하고 기생적인 소스/드레인 접합 용량 및 소스/드레인에 의한 직렬 저항을 줄이는 것이 중요하다.In high-density MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) with a size of less than 0.05 µm, it is important to suppress short channel effects and reduce parasitic source / drain junction capacitance and series / drain resistance by source / drain.

도1a 내지 도1c는 종래 기술에 따른 반도체 장치 제조 공정 단면도이다. 도1a 내지 도1b를 참조하여 SOI (Silicon-On-Insulator) 기판에 모스트랜지스터를 형성하기 위한 종래의 방법을 설명한다.1A to 1C are cross-sectional views of a semiconductor device manufacturing process according to the prior art. 1A to 1B, a conventional method for forming a MOS transistor on a silicon-on-insulator (SOI) substrate will be described.

먼저, 도1a에 도시한 바와 같이 반도체 기판(11) 상에 매몰 산화막(12) 및 실리콘막(13)을 차례로 형성한 후 소자 분리를 위한 필드산화막(14)을 형성한다.First, as shown in FIG. 1A, a buried oxide film 12 and a silicon film 13 are sequentially formed on the semiconductor substrate 11, and then a field oxide film 14 for device isolation is formed.

다음으로, 도1b에 도시한 바와 같이 게이트 절연막(15)을 형성하고 게이트 전극 형성을 위한 폴리실리콘을 증착하고 패터닝하여 게이트 전극(16)을 형성한다. 이어서, 이온주입 공정을 실시하여 n-불순물 도핑 영역(17)을 형성한다.Next, as shown in FIG. 1B, the gate insulating film 15 is formed, and polysilicon is deposited and patterned to form the gate electrode to form the gate electrode 16. Next, an ion implantation process is performed to form the n − impurity doped region 17.

다음으로, 도1c에 도시한 바와 같이 스페이서(18)를 형성한 후 이온주입 공정을 실시하여 n+불순물 도핑 영역(19)을 형성하여 저도핑 드레인(lightly doped drain) 구조를 갖는 소오스/드레인 접합을 형성한다.Next, as shown in FIG. 1C, a spacer 18 is formed and an ion implantation process is performed to form n + impurity doped region 19 to form a source / drain junction having a lightly doped drain structure. To form.

상기와 같이 SOI 기판에 형성되는 모스트랜지스터는 벌크 실리콘 기판(Bulk Silicon Wafer)에 형성되는 모스트랜지스터에 비해 래치-업(LATCH-UP)에 강하고, 낮은 문턱 전압(Low Threshold Voltage) 조절이 용이하며, 저전압 소자에 유용하게 적용할 수 있으며, 또한 소자의 고집적이 용이하다는 장점이 있다.As described above, the MOS transistor formed on the SOI substrate is stronger in LATCH-UP than the MOS transistor formed on the bulk silicon wafer, and easy to control the low threshold voltage. It can be usefully applied to low-voltage devices, and also has the advantage of easy integration of devices.

그러나, 얇은 SOI 기판상에 소오스 및 드레인 영역을 형성하게 되므로, 소자의 동작에 있어서, 소오스/드레인간의 직렬 저항이 크다. 또한, 소오스/드레인 접합이 필드산화막(14) 및 게이트 전극(16)에 의해 완전히 차단되어 있어 소오스/드레인에 전하 증가(charge build-up)로 인한 소오스와 기판 사이의 바이어스 전압에 따라 문턱전압이 변화하는 플로팅 바디 효과( floating body effect) 문제가 발생한다.However, since source and drain regions are formed on a thin SOI substrate, the series resistance between the source and the drain is large in the operation of the device. In addition, since the source / drain junction is completely blocked by the field oxide film 14 and the gate electrode 16, the threshold voltage is increased depending on the bias voltage between the source and the substrate due to the charge build-up of the source / drain. A floating body effect problem occurs.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 소오스-드레인간의 직렬 저항 감소 및 플로팅 바디 효과를 제거할 수 있는 반도체 장치 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a semiconductor device and a method of manufacturing the same that can reduce the series resistance between the source and drain and the floating body effect.

도1a 내지 도1c는 종래 기술에 따른 SOI 모스트랜지스터 제조 공정 단면도.1A-1C are cross-sectional views of a prior art SOI morph transistor manufacturing process.

도2a 내지 도2e는 본 발명의 일실시예에 따른 모스트랜지스터 제조 공정 단면도.Figure 2a to 2e is a cross-sectional view of the morph transistor manufacturing process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

21: 반도체 기판 22: 필드산화막21: semiconductor substrate 22: field oxide film

23: 질화막 24: 감광막 패턴23: nitride film 24: photosensitive film pattern

25: 매몰산화층 26: 게이트 산화막25: buried oxide layer 26: gate oxide film

27: 폴리실리콘막 28: n-불순물 도핑 영역27: polysilicon film 28: n - impurity doped region

29:: 스페이서 30: n+불순물 도핑 영역29 :: spacer 30: n + impurity doped region

상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 형성된 질화막을 선택적으로 제거하여 게이트 영역의 상기 반도체 기판 표면을 노출하는 단계; 상기 게이트 영역 하부에 위치하는 채널 영역 하부에 이온을 주입하여 매립 절연층을 형성하는 단계; 게이트 전극을 형성하고, 상기 질화막을 제거하는 단계; 및 상기 게이트 전극 일측 및 타측의 상기 반도체 기판 내에 소오스 및 드레인 영역을 형성하는 단계를 포함하여 이루어지는 모스트랜지스터 제조 방법을 제공한다.The present invention for achieving the above object, the step of selectively removing the nitride film formed on the semiconductor substrate to expose the surface of the semiconductor substrate of the gate region; Forming a buried insulation layer by implanting ions into a lower portion of the channel region under the gate region; Forming a gate electrode and removing the nitride film; And forming a source and a drain region in the semiconductor substrate on the one side and the other side of the gate electrode.

도2a 내지 도2e는 본 발명의 일실시예에 따른 모스트랜지스터 제조 공정 단면도이다. 이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 설명한다.2A to 2E are cross-sectional views of a MOS transistor manufacturing process according to an embodiment of the present invention. Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

먼저, 도2a에 도시한 바와 같이 웰(도시하지 않음)이 형성된 반도체 기판(21)에 소자분리를 위하여 필드산화막(22)을 형성한다.First, as shown in FIG. 2A, a field oxide film 22 is formed on a semiconductor substrate 21 having wells (not shown) for device isolation.

다음으로, 도2b에 도시한 바와 같이 500 Å 내지 1500 Å 두께의 질화막(23)을 형성하고, 게이트 영역을 노출하는 감광막 패턴(24)을 형성한다. 이어서, 상기 감광막 패턴(24)을 마스크로하여 상기 질화막(23)을 선택적으로 식각하여 게이트 영역의 반도체 기판 표면을 노출한다. 이어서, 상기 감광막 패턴(24)을 이온주입 마스크로 하여 채널영역 하부에 O+이온을 주입하여 한다.Next, as shown in FIG. 2B, a nitride film 23 having a thickness of 500 kV to 1500 kV is formed, and a photosensitive film pattern 24 exposing the gate region is formed. Subsequently, the nitride film 23 is selectively etched using the photoresist pattern 24 as a mask to expose the semiconductor substrate surface of the gate region. Subsequently, O + ions are implanted under the channel region using the photoresist pattern 24 as an ion implantation mask.

다음으로, 도2c에 도시한 바와 같이 상기 감광막 패턴(24)을 제거한 후 재결정을 위한 열처리(annealing) 공정을 실시하여 채널영역 하부에 매몰산화층(25)을 형성함으로써, 채널의 깊이(t)가 반도체 기판(21) 표면과 매몰산화층(25) 사이의 간격으로 결정되도록 한다. 이로써, 채널 영역이 SOI 층에 형성되는 것과 같은 효과를 가질 수 있다. 이어서, 산화공정을 실시하여 게이트 산화막(26)을 형성한 후, 폴리실리콘막(27)을 형성하고 게이트 전극을 형성하기 위하여 폴리실리콘막(27)에 불순물을 도핑한다.Next, as shown in FIG. 2C, after removing the photoresist pattern 24, an annealing process for recrystallization is performed to form a buried oxide layer 25 under the channel region, whereby the depth t of the channel is increased. The gap between the surface of the semiconductor substrate 21 and the buried oxide layer 25 is determined. This can have the same effect as the channel region is formed in the SOI layer. Subsequently, after the oxidation process is performed to form the gate oxide film 26, the polysilicon film 27 is doped with impurities to form the polysilicon film 27 and to form the gate electrode.

다음으로, 도2d에 도시한 바와 같이 상기 폴리실리콘막(27)을 패터닝하여 게이트 전극(27')을 형성하고, 게이트 영역을 제외한 영역에 형성되어 있는 질화막을 제거한다. 이때, 상기 게이트 전극(27')을 형성하기 위하여 폴리실리콘막(27)을 패터닝하는 과정에서 마스크 정렬 오차에 의해 게이트 전극(27')의 하단양측에 질화막이 남게되는데, 남는 질화막 폭(A, B)은 각각 0.1 ㎛가 넘지 않도록 한다. 이어서, 이온주입 공정을 실시하여 n-불순물 도핑 영역(28)을 형성하는데, 게이트 전극(27')의 하단 양측에 남은 질화막의 폭을 고려하여 경사 이온 입을 실시한다. 경사 이온주입은 게이트 전극(27')의 일측 및 타측에서 두 번 실시되는데, 각각의 이온주입시 주입되는 이온이 반도체 기판(21)으로부터 30 °내지 60°의 각을 이루도록한다.Next, as shown in FIG. 2D, the polysilicon film 27 is patterned to form the gate electrode 27 ', and the nitride film formed in the region except the gate region is removed. At this time, in the process of patterning the polysilicon film 27 to form the gate electrode 27 ', nitride films remain on both sides of the lower end of the gate electrode 27' due to a mask alignment error. B) should not exceed 0.1 µm each. Subsequently, an ion implantation process is performed to form the n − impurity doped region 28, and inclined ion implantation is performed in consideration of the width of the nitride film remaining on both sides of the lower end of the gate electrode 27 ′. Inclined ion implantation is performed twice on one side and the other side of the gate electrode 27 ', so that the ions implanted during each ion implantation form an angle of 30 ° to 60 ° from the semiconductor substrate 21.

다음으로 도2e에 도시한 바와 같이 스페이서(29)를 형성하고, 이온주입 공정을 실시하여 n+불순물 도핑 영역(30)을 형성하여 저도핑 드레인 구조의 소오스/드레인 접합을 형성한다.Next, as shown in FIG. 2E, a spacer 29 is formed, and an ion implantation process is performed to form an n + impurity doped region 30 to form a source / drain junction having a low doped drain structure.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 벌크(bulk) 기판에 형성되는 트랜지스터의 장점 및 SOI형 트랜지스터의 장점을 동시에 갖는 반도체 장치 및 그 제조 방법으로서 새로이 증착된 폴리실리콘과 벌크 기판을 접합 영역으로 사용하기 때문에 종래의 SOI 모스트랜지스터에서 나타나는 소오스-드레인의 직렬 저항 및 플로팅 바디 효과에 의한 소자 특성 저하를 방지할 수 있다.The present invention made as described above is a semiconductor device having both the advantages of a transistor formed on a bulk substrate and the advantages of an SOI transistor, and a method of manufacturing the same. Deterioration of device characteristics due to the series resistance and floating body effects of the source-drain appearing in the SOI morph transistors of the transistor can be prevented.

Claims (5)

반도체 기판 상에 형성된 질화막을 선택적으로 제거하여 게이트 영역의 상기 반도체 기판 표면을 노출하는 단계;Selectively removing the nitride film formed on the semiconductor substrate to expose the surface of the semiconductor substrate in the gate region; 상기 게이트 영역 하부에 위치하는 채널 영역 하부에 이온을 주입하여 매립 절연층을 형성하는 단계;Forming a buried insulation layer by implanting ions into a lower portion of the channel region under the gate region; 게이트 전극을 형성하고, 상기 질화막을 제거하는 단계; 및Forming a gate electrode and removing the nitride film; And 상기 게이트 전극 일측 및 타측의 상기 반도체 기판 내에 소오스 및 드레인 영역을 형성하는 단계를 포함하여 이루어지는 모스트랜지스터 제조 방법.And forming a source and a drain region in the semiconductor substrate on one side and the other side of the gate electrode. 제 1 항에 있어서,The method of claim 1, 상기 매립 절연층을 산화막으로 형성하는 모스트랜지스터 제조 방법.A method of manufacturing a MOS transistor, wherein the buried insulating layer is formed of an oxide film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 소오스 및 드레인 영역을 형성하는 단계는,Forming the source and drain regions, 상기 게이트 전극을 이온주입 방지막으로하여 제1 불순물 도핑 영역을 형성하는 단계;Forming a first impurity doped region by using the gate electrode as an ion implantation prevention film; 상기 게이트 전극 측벽에 스페이서를 형성하는 단계;Forming a spacer on sidewalls of the gate electrode; 상기 게이트 전극 및 스페이서를 이온주입 방지막으로하여 상기 제1 불순물 도핑 영역의 일부분과 인접하되, 상기 제1 불순물 도핑 영역보다 농도가 높은 제2 불순물 도핑 영역을 형성하는 단계를 포함하는 모스트랜지스터 제조 방법.And forming a second impurity doped region adjacent to a portion of the first impurity doped region and having a higher concentration than the first impurity doped region by using the gate electrode and the spacer as an ion implantation prevention film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 매립 절연층을 상기 반도체 기판 표면으로부터 그 내부로 채널 폭만큼 이격하여 형성하는 모스트랜지스터 제조 방법.And forming the buried insulating layer spaced apart from the surface of the semiconductor substrate by a channel width therein. 제 4 항에 있어서,The method of claim 4, wherein 상기 질화막을 500 Å 내지 1500 Å 두께로 형성하고,The nitride film is formed to a thickness of 500 kV to 1500 kV, 상기 제1 불순물 도핑 영역을 형성하는 단계에서 주입되는 이온이 상기 반도체 기판으로부터 30°내지 60°각을 이루도록 이온 주입하는 것을 특징으로 하는 모스트랜지스터 제조 방법.And implanting ions implanted in the step of forming the first impurity doped region to form an angle of 30 ° to 60 ° from the semiconductor substrate.
KR1019970075044A 1997-12-27 1997-12-27 Method for manufacturing mosfet KR100257756B1 (en)

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