KR100252754B1 - Thin film transistor and the manufacturing method thereof - Google Patents
Thin film transistor and the manufacturing method thereof Download PDFInfo
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- KR100252754B1 KR100252754B1 KR1019960067612A KR19960067612A KR100252754B1 KR 100252754 B1 KR100252754 B1 KR 100252754B1 KR 1019960067612 A KR1019960067612 A KR 1019960067612A KR 19960067612 A KR19960067612 A KR 19960067612A KR 100252754 B1 KR100252754 B1 KR 100252754B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000001953 recrystallisation Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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Abstract
Description
본 발명은 박막트랜지스터(Thin Film Transistor) 및 그 제조방법에 관한 것으로, 특히 높은 온/오프 전류비(ON/OFF current ratio) 특성을 갖는 폴리실리콘 박막트랜지스터구조 및 이의 제조방법에 관한 것이다.The present invention relates to a thin film transistor (Thin Film Transistor) and a method for manufacturing the same, and more particularly to a polysilicon thin film transistor structure having a high ON / OFF current ratio characteristics and a manufacturing method thereof.
박막트랜지스터는 액정표시장치(liquid crystal display) 및 고집적 SRAM의 부하저항으로 사용되는 반도체소자로서, 이와 같은 박막트랜지스터를 제조하기 위한 종래의 방법을 도 1A 내지 도 1D를 참조하여 설명하면 다음과 같다.The thin film transistor is a semiconductor device used as a load resistance of a liquid crystal display and a highly integrated SRAM. A conventional method for manufacturing such a thin film transistor will be described with reference to FIGS. 1A to 1D.
먼저, 도 1A에 도시된 바와 같이 기판(1)상에 절연층으로서 산화막(2)을 형성하고, 그위에 비정질실리콘(3)을 증착한 후, 채널형성을 위해 비정질실리콘층(3)에 n형 불순물을 이온주입(4)한다.First, as shown in FIG. 1A, an oxide film 2 is formed on the substrate 1 as an insulating layer, and amorphous silicon 3 is deposited thereon, and then n is deposited on the amorphous silicon layer 3 for channel formation. Ion implantation (4) of a type impurity is carried out.
이어서 도 1B에 도시된 바와 같이 상기 비정질실리콘층(3)상에 게이트산화막(5)을 개재하여 게이트전극(6)을 형성한다.Subsequently, as shown in FIG. 1B, the gate electrode 6 is formed on the amorphous silicon layer 3 via the gate oxide film 5.
다음에 도 1C에 도시된 바와 같이 기판상에 포토레지스트를 도포하고 이를 사진식각공정을 통해 선택적으로 노광 및 현상하여 소정의 마스크패턴(7)을 형성한 후, p형 불순물을 고농도로 이온주입(8)한다.Next, as shown in FIG. 1C, a photoresist is applied onto the substrate, and the photoresist is selectively exposed and developed through a photolithography process to form a predetermined mask pattern 7. Then, p-type impurities are implanted at high concentration ( 8)
이어서 도 1D에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 어닐링을 행하여 게이트전극(6) 양측의 비정질실리콘층(3) 소정부분에 p+ 소오스(10) 및 드레인(11)을 형성한다. 이와 같이 함으로써 LDD구조 및 드레인 오프셋구조(12)를 갖는 박막트랜지스터를 형성한다.Subsequently, after removing the photoresist pattern as shown in FIG. 1D, annealing is performed to form a p + source 10 and a drain 11 at predetermined portions of the amorphous silicon layer 3 on both sides of the gate electrode 6. In this manner, a thin film transistor having an LDD structure and a drain offset structure 12 is formed.
상술한 바와 같은 LDD구조 및 드레인오프셋구조를 갖는 종래의 박막트랜지스터는 오프(off)상태에서 누설전류가 크다는 문제가 있다. 이는 드레인(11)쪽에서 높은 전계(electric field)에 의해 활성층인 폴리실리콘의 결정입계(grain boundary)를 따라 필드 방출(field emission)이 일어나기 때문이다.The conventional thin film transistor having the LDD structure and the drain offset structure as described above has a problem that the leakage current is large in the off state. This is because field emission occurs along the grain boundary of the polysilicon as an active layer by a high electric field on the drain 11 side.
종래의 LDD구조나 오프셋 드레인구조 자체도 드레인 필드를 줄여 누설전류를 줄일 수 있으나, 온(on)상태에서의 전류까지 줄이는 (추가적인 직렬저항의 증가를 초래함으로써) 문제점이 있다.Conventional LDD structures or offset drain structures themselves can reduce the leakage field by reducing the drain field, but have a problem of reducing the current in the on state (by causing additional series resistance increase).
따라서 고집적 SRAM등에서 요구되는 높은 온/오프 전류비를 갖는 박막트랜지스터를 형성할 수 없다는 문제가 있다.Therefore, there is a problem in that a thin film transistor having a high on / off current ratio required in a highly integrated SRAM or the like cannot be formed.
본 발명은 높은 온/오프 전류비를 갖는 박막트랜지스터 및 이의 제조방법을 제공하는 것을 그 목적으로 한다.An object of the present invention is to provide a thin film transistor having a high on / off current ratio and a method of manufacturing the same.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터는 반도체기판상에 형성되며 소정영역에 리세스구조를 갖춘 절연층과, 상기 절연층의 리세스영역 양측면에 형성된 스페이서 형태의 부유게이트, 상기 절연층 및 부유게이트 상부에 층간절연막을 개재하여 형성되며, 제1도전형의 채널영역과 이 채널영역 양측에 형성된 제2도전형의 저농도 불순물영역 및 이 제2도전형의 저농도 불순물영역 양측에 형성된 제2도전형의 고농도 소오스 및 드레인으로 이루어진 활성층, 및 상기 제1도전형의 채널영역 상부에 게이트산화막을 개재하여 형성된 게이트전극을 포함하여 구성된다.The thin film transistor of the present invention for achieving the above object is an insulating layer formed on a semiconductor substrate having a recess structure in a predetermined region, a floating gate in the form of a spacer formed on both sides of the recess region of the insulating layer, the insulating layer and The interlayer insulating film is formed over the floating gate, and the channel region of the first conductivity type, the low concentration impurity region of the second conductivity type formed on both sides of the channel region, and the second conductivity formed on both sides of the low concentration impurity region of the second conductivity type are formed. An active layer comprising a high concentration source and a drain of the type, and a gate electrode formed on the channel region of the first conductive type via a gate oxide film.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터 제조방법은 반도체기판상에 절연층을 형성하는 단계와, 상기 절연층의 소정부분을 선택적으로 소정두께만큼 식각하는 단계, 상기 절연층의 식각된 부위 측면에 스페이서형태의 부유게이트를 형성하는 단계, 상기 부유게이트가 형성된 기판 전면에 층간절연막을 개재하여 폴리실리콘층을 형성하는 단계, 상기 폴리실리콘층 상부의 소정영역에 게이트산화막과 제1도전형 불순물로 도핑된 게이트전극을 차례로 형성하는 단계, 상기 게이트전극 양단의 상기 폴리실리콘층 부위에 제2도전형의 저농도 불순물영역을 형성하는 단계, 상기 게이트전극 양측면에 절연막스페이서를 형성하는 단계, 및 상기 절연막스페이서 양단의 상기 폴리실리콘층 부위에 제2도전형의 고농도 소오스 및 드레인영역을 형성하는 단계를 포함하여 구성된다.The thin film transistor manufacturing method of the present invention for achieving the above object comprises the steps of forming an insulating layer on a semiconductor substrate, selectively etching a predetermined portion of the insulating layer by a predetermined thickness, side of the etched portion of the insulating layer Forming a floating gate in the form of a spacer on the substrate; forming a polysilicon layer on the entire surface of the substrate on which the floating gate is formed with an interlayer insulating layer; and forming a gate oxide layer and a first conductive impurity on a predetermined region Forming a doped gate electrode in sequence, forming a low concentration impurity region of a second conductivity type in the polysilicon layer region across the gate electrode, forming an insulating film spacer on both sides of the gate electrode, and the insulating film spacer High concentration source and drain regions of the second conductivity type are formed in the polysilicon layer portions at both ends. It is configured to include the step of.
도 1A 내지 도 1D는 종래기술에 의한 박막트랜지스터 제조방법을 도시한 공정순서도,1A to 1D are process flowcharts showing a method of manufacturing a thin film transistor according to the prior art;
도 2는 본 발명에 의한 박막트랜지스터의 단면구조도,2 is a cross-sectional structure diagram of a thin film transistor according to the present invention;
도 3A 내지 도 3E는 본 발명에 의한 박막트랜지스터 제조방법을 도시한 공정순서도.3A to 3E are process flowcharts showing a method of manufacturing a thin film transistor according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20:반도체기판 21:절연층20: semiconductor substrate 21: insulating layer
23:부유게이트 24:층간절연막23: floating gate 24: interlayer insulating film
26:게이트산화막 27:게이트전극26: gate oxide film 27: gate electrode
29:P-LDD영역 30:절연막스페이서29: P - LDD area 30: insulating film spacer
32:P+ 소오스 33:드레인32: P + Source 33: Drain
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2에 본 발명에 의한 박막트랜지스터 구조를 단면도로 나타내었다.2 is a cross-sectional view of a thin film transistor structure according to the present invention.
도 2는 PMOS 박막트랜지스터의 경우를 도시한 것으로, 반도체기판(20)상에 리세스(recess)구조를 갖는 절연층(21)이 형성되고, 이 절연층의 리세스부분의 측면에 스페이서 형태의 부유게이트(23)가 형성되며, 상기 절연층 및 부유게이트 상부에 층간절연막(24)을 개재하여 활성층인 폴리실리콘층이 형성되는바, 상기 리세스부분 상부의 폴리실리콘층 부위는 N-채널영역(25)으로 이루어지고, 이 N-영역 양측은 P-LDD영역(29), 그리고 P_LDD영역 양측은 P+ 소오스(32) 및 드레인(33)으로 이루어져 있다. 상기 N_채널영역 상부에는 게이트산화막(26)을 개재하여 게이트전극(27)이 형성되고, 게이트전극(27)의 양측면에는 절연막 스페이서(30)가 형성된 구조로 본 발명의 박막트랜지스터는 구성된다.FIG. 2 shows a case of a PMOS thin film transistor, in which an insulating layer 21 having a recess structure is formed on a semiconductor substrate 20, and a spacer is formed on the side of the recess portion of the insulating layer. A floating gate 23 is formed, and a polysilicon layer as an active layer is formed on the insulating layer and the interlayer insulating layer 24 over the floating gate, and the polysilicon layer portion on the recess portion is an N - channel region. is composed of 25, and the N - region is both side P - it consists of a LDD region 29, and P _ LDD regions on both sides is P + source 32 and drain 33. The thin film transistor of the present invention has a structure in which a gate electrode 27 is formed on the N_ channel region through a gate oxide layer 26, and insulating film spacers 30 are formed on both sides of the gate electrode 27.
본 발명은 상기 부유게이트(23)를 이용하여 오프상태에서의 누설전류와 킹크 효과(kink effect)를 효과적으로 억제하면서 매우 양호한 온상태에서의 전류를 얻을 수 있도록 한다.The present invention makes it possible to obtain a very good on-state current while effectively suppressing the leakage current and the kink effect in the off state by using the floating gate 23.
오프상태(Vd=Vdd, Vg=0)에서는 부유게이트(23)의 전위(potential)에 의해 드레인(33)과 게이트(27) 사이의 전계가 감소하게 되어 누설전류가 감소하며, 온상태(Vg>0, Vd=Vdd)에서는 부유게이트(23)가 축적층(accumulation layer)의 역할을 하여 소오스(32)와 드레인(33)간의 직렬 저항을 감소시켜 온전류가 증가하게 된다.In the off state (Vd = Vdd, Vg = 0), the electric field between the drain 33 and the gate 27 decreases due to the potential of the floating gate 23 so that the leakage current decreases, and the on state Vg > 0, Vd = Vdd), the floating gate 23 acts as an accumulation layer to decrease the series resistance between the source 32 and the drain 33, thereby increasing the on-current.
도 3A 내지 도 3E를 참조하여 본 발명에 의한 박막트랜지스터 제조방법을 다음에 설명한다.3A to 3E, a method of manufacturing a thin film transistor according to the present invention will be described next.
먼저, 도 3A에 도시된 바와 같이 기판(20)상에 절연층으로서 산화막(21)을 형성하고, 그위에 포토레지스트를 도포한 후 사진식각공정을 통해 선택적으로 노광 및 현상하여 소정의 마스크패턴(22)을 형성한다.First, as shown in FIG. 3A, an oxide layer 21 is formed on the substrate 20 as an insulating layer, a photoresist is applied thereon, and then selectively exposed and developed through a photolithography process to obtain a predetermined mask pattern ( 22).
이어서 도 3B에 도시된 바와 같이 상기 마스크패턴(22)을 마스크로 이용하여 노출된 산화막(21)부위를 선택적으로 소정깊이 만큼 식각한다. 이때, 식각되는 깊이(A)는 0.2-0.5│Lm정도가 되도록 하며, 식각되지 않고 남아 있게 되는 두께(B)는 0.1-0.2│Lm정도가 되도록 하는 것이 바람직하다. 이어서 도전물질로서 폴리실리콘을 상기 산화막(21) 전면에 증착하고 p+ 도핑을 행한 후, 이를 블랭킷 에치(blanket etch)하여 산화막(21)의 식각된 부위 측면에 스페이서형태의 부유게이트(23)를 형성한다. 다음에 상기 부유게이트(23)가 형성된 기판 전면에 층간절연층으로서 산화막(24)을 250-500Å 두께로 형성하고, 이위에 비정질실리콘층을 1000-2000Å 두께로 형성한 후, 이를 재결정화(recrystallization)하여 폴리실리콘층(25)을 형성한다.Subsequently, as illustrated in FIG. 3B, the exposed oxide layer 21 is selectively etched by a predetermined depth using the mask pattern 22 as a mask. At this time, the depth (A) to be etched to be about 0.2-0.5 | Lm, and the thickness (B) that remains unetched is preferably about 0.1-0.2 | Lm. Subsequently, polysilicon is deposited as a conductive material on the entire surface of the oxide film 21 and then doped with p +, followed by blanket etch to form a spacer-type floating gate 23 on the side of the etched portion of the oxide film 21. do. Next, an oxide film 24 is formed to have a thickness of 250 to 500 mW as an interlayer insulating layer on the entire surface of the substrate on which the floating gate 23 is formed, and an amorphous silicon layer is formed to have a thickness of 1000 to 2000 mW thereon, followed by recrystallization. ) To form a polysilicon layer 25.
이어서 도 3C에 도시된 바와 같이 상기 폴리실리콘층(25)상에 산화막(26)과 폴리실리콘층(27)을 차례로 형성하고, 폴리실리콘층(27)에 n+ 도핑을 행한 후, 폴리실리콘층(27) 및 산화막(26)을 소정패턴으로 패터닝하여 게이트산화막(26) 및 게이트전극(27)을 형성한다. 이어서 p형 불순물을 저농도로(p-) 이온주입(28)하여 도 3D에 도시된 바와 같이 게이트전극(27) 양단의 폴리실리콘층(25) 부위에 P-LDD영역(29)을 형성한다.Subsequently, as shown in FIG. 3C, an oxide film 26 and a polysilicon layer 27 are sequentially formed on the polysilicon layer 25, and n + doping is performed on the polysilicon layer 27, followed by a polysilicon layer ( 27 and the oxide film 26 are patterned in a predetermined pattern to form the gate oxide film 26 and the gate electrode 27. Subsequently, the p-type impurity is implanted at a low concentration (p−) ion 28 to form the P − LDD region 29 at the polysilicon layer 25 across the gate electrode 27 as shown in FIG. 3D.
이어서 절연층으로서, 예컨대 산화막을 기판 전면에 형성하고 이를 블랭킷 에치하여 게이트전극(27) 및 게이트산화막(26) 측면에 산화막스페이서(30)를 형성한 다음, p형 불순물을 고농도로(p+) 이온주입(31)하고 어닐링을 행하여 도 3E에 도시된 바와 같이 상기 폴리실리콘층(25) 소정부분에 P+ 소오스(32) 및 드레인(33)을 형성한다.Subsequently, as an insulating layer, for example, an oxide film is formed on the entire surface of the substrate and blanket etched to form an oxide film spacer 30 on the side of the gate electrode 27 and the gate oxide film 26, and then p-type impurities are formed at high concentration (p +) ions. The implant 31 is then annealed to form a P + source 32 and a drain 33 in a predetermined portion of the polysilicon layer 25 as shown in FIG. 3E.
상기 실시예에서는 PMOS 박막트랜지스터를 형성하는 경우를 설명하였으며, NMOS 박막트랜지스터의 경우는 주입되는 불순물 이온의 극성만 반대로 해주면 된다.In the above embodiment, the case of forming the PMOS thin film transistor has been described. In the case of the NMOS thin film transistor, only the polarity of the impurity ions to be implanted is reversed.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 드레인측 누설전류의 감소효과를 얻을 수 있고, 온/오프 전류비를 증가시킬 수 있어 차세대 고집적 소자에 적용에 가능하게 된다.According to the present invention, the effect of reducing the drain side leakage current can be obtained, and the on / off current ratio can be increased, making it possible to apply to the next generation high integration device.
Claims (8)
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