KR100190374B1 - Thin film transistor having high on/off current ratio and fabrication method of the same - Google Patents
Thin film transistor having high on/off current ratio and fabrication method of the same Download PDFInfo
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- KR100190374B1 KR100190374B1 KR1019950050994A KR19950050994A KR100190374B1 KR 100190374 B1 KR100190374 B1 KR 100190374B1 KR 1019950050994 A KR1019950050994 A KR 1019950050994A KR 19950050994 A KR19950050994 A KR 19950050994A KR 100190374 B1 KR100190374 B1 KR 100190374B1
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- film
- conductive film
- forming conductive
- thin film
- gate
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- 239000010409 thin film Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 208000003443 Unconsciousness Diseases 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
본 발명은 일부영역에 고농도의 불순물이 주입된 플로팅 영역을 갖는 채널 폴리실리콘막(3); 상기 채널 폴리실리콘막(3) 상에 형성된 게이트 산화막(4); 및 상기 게이트 산화막(4) 상에 형성되되 상기 채널 폴리실리콘막(3)에 형성된 플로팅 영역 상부에는 위치하지 않고 필드영역에서 전기적으로 접속되는 게이트 폴리실리콘막(5)을 포함하여 이루어지는 것을 특징으로 하는 높은 온/오프 전류비를 갖는 박막 트랜지스터에 관한 것으로, 누설전류를 줄여 트랜지스터의 오프시 전류를 감소시킴으로써 에너지 소비를 줄일 수 있고, 특히 온/오프 전류비가 106이상이 되어야 하는 LCD TFT의 경우에 있어서 충분한 오프전류의 감소를 얻을 수 있는 박막 트랜지스터에 관한 것이다.The present invention provides a channel polysilicon film (3) having a floating region in which a high concentration of impurities are injected into a partial region; A gate oxide film 4 formed on the channel polysilicon film 3; And a gate polysilicon film 5 formed on the gate oxide film 4 and not electrically located above the floating region formed in the channel polysilicon film 3 and electrically connected in the field region. in the case of a LCD TFT to be that, by reducing the leakage current decrease the oFF-state when the current of the transistor can be reduced energy consumption, in particular on / off current ratio of 10 6 or above on the thin-film transistor having a high on / off current ratio The present invention relates to a thin film transistor which can achieve a sufficient reduction of off current.
Description
제1도 내지 제3도는 본 발면에 따른 박막 트랜지스터 제조 공정 단면도.1 to 3 are cross-sectional views of a thin film transistor manufacturing process according to the present invention.
제4도는 제3도의 평면도.4 is a plan view of FIG.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 절연막 2 : 산화막1 insulating film 2 oxide film
3 : 채널 폴리실콘막 4 : 게이트 산화막3: channel polysilicon film 4: gate oxide film
5 : 게이트 폴리실리콘막5: gate polysilicon film
본 발명은 LOC, SRAM 및 이미지 센서에 주로 사용되는 박막 트랜지스터 및 그 제조방법에 관한 것으로 특히 누설전류를 최소화할 수 있는 박막 트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors mainly used in LOCs, SRAMs, and image sensors, and a method of manufacturing the same.
일반적으로, MOS 구조를 이용한 TFT(thin film transistor)는 드렌인 접합(drain junction)에 높은 전압이 걸려 누설전류(leakage current)가 많이 흐르게 된다. 특히, 폴리실리콘막을 사용하여 형성되는 박막 트랜지스터는 상기 폴리실리콘막이 단결정 실리콘에 비해 결함을 많이 가지고 있기 때문에 비교적 누설전류가 많이 발생하게 된다.In general, a thin film transistor (TFT) using a MOS structure has a high voltage applied to a drain-in junction, so that a large amount of leakage current flows. In particular, in the thin film transistor formed using the polysilicon film, since the polysilicon film has more defects than single crystal silicon, a relatively large leakage current is generated.
또한 누설전류는 드레인 접합에 걸리는 전압에 의해 지수함수적으로 증가하기 때문에 트랜지스터의 드레인 접합에 전압이 많이 걸리면 오프 전류(off current)가 많이 흐른다.In addition, since the leakage current increases exponentially with the voltage applied to the drain junction, a large amount of off current flows when a large voltage is applied to the drain junction of the transistor.
따라서, 드레인 접합에 걸리는 전압을 최소화하기 위한 방법이 개발되고 있지만, 원하는 수준의 누설전류 감소를 얻지 못하여 박막 트랜지스터의 전기적 특성을 만족시키지 못하는 문제점이 있었다.Therefore, although a method for minimizing the voltage applied to the drain junction has been developed, there is a problem in that the electrical characteristics of the thin film transistor are not satisfied because a desired leakage current reduction is not achieved.
상기 문제점을 해결하기 위하여 안출된 본 발명은 박막 트랜지스터의 채널에서의 농도변화를 주어 드레인 접합에 인가되는 전압을 낮추어 누설전류의 감소를 얻기 위한 박막 트랜지스터 및 그 제조방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a thin film transistor and a method of manufacturing the same to obtain a reduction in leakage current by lowering the voltage applied to the drain junction by changing the concentration in the channel of the thin film transistor. .
상기 목적을 달성하기 위하여 본 발명은, 절연막 상에 채널 형성용 전도막, 게이트 절연막 및 게이트 형성용 전도막을 차례로 증착하는 단계; 상기 게이트 형성용 전도막의 중앙 일부부위를 소정의 크기로 패턴하여 제거하되 필드영역에서 분리된 게이트 형성용 전도막이 전기적으로 접속되도록 식각하는 단계; 및 상기 게이트 형성용 전도막이 제거된 지역의 하부에 위치하는 채널 형성용 전도막에 불순물 이온을 주입하여 서로 분리된 3개의 고농도 이온 주입영역을 형성하여 소오스/드레인 영역과 플로팅(floating) 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of depositing a channel forming conductive film, a gate insulating film and a gate forming conductive film on the insulating film in order; Patterning and removing a central portion of the gate forming conductive film to a predetermined size, and etching the gate forming conductive film separated from the field region so as to be electrically connected; And implanting impurity ions into the channel forming conductive film positioned below the region where the gate forming conductive film is removed to form three high concentration ion implantation regions separated from each other to form source / drain regions and floating regions. Characterized in that it comprises a step.
또한, 본 발명은 일부 영역에 고농도의 불순물이 주입된 플로팅 영역을 갖는 채널 형성용 전도막; 상기 채널 형성용 전도막 상에 형성된 게이트 절연막; 및 상기 게이트 절연막 상에 형성되되 상기 채널 형성용 전도막에 형성된 플로팅 영역 상부에는 위치하지 않고 필드영역에서 전기적으로 접속되는 게이트 형성용 전도막을 포함하여 이루어지는 것을 특징으로 한다.In addition, the present invention is a conductive film for forming a channel having a floating region in which a high concentration of impurities are injected into a portion; A gate insulating film formed on the channel forming conductive film; And a gate forming conductive film formed on the gate insulating film and not electrically located above the floating region formed in the channel forming conductive film, but electrically connected in the field region.
이하, 첨부된 도면 제 1 도 내지 제 4 도는 본 발명에 따른 박막 트랜지스터 및 그 제조방법을 상세히 설명하면 다음과 같다.1 to 4 illustrate the thin film transistor and the method of manufacturing the same according to the present invention in detail.
먼저, 제 1 도에 도시된 바와 같이 SOI(silicon on insulator) 구조의 박막 트랜지스터를 형성하기 위하여 절연막(1) 상에 산화막(2), 채널 폴리실리콘막(3), 게이트 산화막(4) 및 n+ 불순물 이온 주입된 게이트 폴리실리콘막(5)을 차례로 증착한다. 이때, 상기 채널 폴리실리콘막(3)에는 불순물 이온이 주입되거나 주입되지 않을 수도 있다.First, as shown in FIG. 1, an oxide film 2, a channel polysilicon film 3, a gate oxide film 4, and n + are formed on an insulating film 1 to form a thin film transistor having a silicon on insulator (SOI) structure. The impurity ion implanted gate polysilicon film 5 is sequentially deposited. In this case, impurity ions may or may not be implanted into the channel polysilicon film 3.
이어서, 제 2 도와 같이 포토공정과 식각공정을 수행하여 상기 게이트 폴리실리콘막(5) 및 게이트 산화막(4)을 소정의 크기로 패턴하게 되는 데, 상기 게이트 폴리실리콘막(5)은 전기적으로 접속되도록 제 4 도와 같이 필드영역에서 서로 연결되도록 형성한다.Subsequently, the gate polysilicon film 5 and the gate oxide film 4 are patterned to a predetermined size by performing a photo process and an etching process as shown in FIG. 2, wherein the gate polysilicon film 5 is electrically connected. It is formed to be connected to each other in the field area as shown in the fourth degree.
그리고 제 3 도와 같이 소오스/드레인을 형성하기 위하여 고농도의 불순물 이온을 채널에 주입함과 동시에 상기 게이트 폴리실리콘막(5) 사이의 중앙 부위에 위치한 채널에도 고농도의 불순물이 주입된다.As shown in FIG. 3, a high concentration of impurity ions are implanted into the channel to form a source / drain, and a high concentration of impurities is also implanted into the channel located between the gate polysilicon film 5.
상기 게이트 폴리실리콘막(5) 사이의 중앙 부위에 위치하여 고농도의 불순물이 주입된 채널영역(도면부호10)은 마치 두개의 트랜지스터의 채널을 연결하는 역할을 한다. 따라서 상기 도면부호 10의 채널은 전압을 가하지 않고 플로팅(floating) 상태로 존재하게 된다.The channel region (10), which is located at the center between the gate polysilicon layers 5 and into which a high concentration of impurities are injected, serves to connect the channels of two transistors. Accordingly, the channel 10 is in a floating state without applying a voltage.
상기 본 발명의 트랜지스터가 동작상태에 있으면 두 채널 길이를 합한 만큼이 하나의 트랜지스터로 동작한다. 그러나, 오프시 드레인 전압이 제 3 도의 밧금친 부분에 나누어 걸리기 때문에 접합에 걸리기 전압은 반으로 줄어 누설전류는 크게 감소하게 된다.When the transistor of the present invention is in an operating state, the sum of two channel lengths operates as one transistor. However, since the drain voltage at the time of off is divided between the portions shown in FIG. 3, the voltage applied to the junction is reduced in half, and the leakage current is greatly reduced.
상기 본 발명의 트랜지스터는 NMOS인 경우에 국한하여 설명하였지만 PMOS인 경우도 마찬가지로 적용된다.Although the transistor of the present invention has been described in the case of NMOS, the same applies to the case of PMOS.
상기와 같이 이루어지는 본 발명은 누설전류를 줄여 트랜지스터의 오프시 전류를 감소시킴으로써 에너지 소비를 줄일 수 있고, 특히 온/오프 전류비가 106이상이 되어야 하는 LCD TFT의 경우에 있어서 충분한 오프전류의 감소를 얻을 수 있는 효과가 있다.The present invention as described above can reduce the energy consumption by reducing the leakage current to reduce the current when the transistor is off, and in particular in the case of the LCD TFT that the on / off current ratio should be 10 6 or more to reduce the sufficient off current There is an effect that can be obtained.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050994A KR100190374B1 (en) | 1995-12-16 | 1995-12-16 | Thin film transistor having high on/off current ratio and fabrication method of the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050994A KR100190374B1 (en) | 1995-12-16 | 1995-12-16 | Thin film transistor having high on/off current ratio and fabrication method of the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970054498A KR970054498A (en) | 1997-07-31 |
| KR100190374B1 true KR100190374B1 (en) | 1999-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050994A KR100190374B1 (en) | 1995-12-16 | 1995-12-16 | Thin film transistor having high on/off current ratio and fabrication method of the same |
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1995
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| KR970054498A (en) | 1997-07-31 |
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