KR0146276B1 - Method for manufacturing mosfet - Google Patents
Method for manufacturing mosfetInfo
- Publication number
- KR0146276B1 KR0146276B1 KR1019930031828A KR930031828A KR0146276B1 KR 0146276 B1 KR0146276 B1 KR 0146276B1 KR 1019930031828 A KR1019930031828 A KR 1019930031828A KR 930031828 A KR930031828 A KR 930031828A KR 0146276 B1 KR0146276 B1 KR 0146276B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- forming
- gate electrode
- polysilicon layer
- pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910052723 transition metal Inorganic materials 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 150000003624 transition metals Chemical class 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- -1 silicide transition metal Chemical class 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
본 발명은 반도체 소자의 모스펫(MOSFET) 제조방법에 관한 것으로, 집적도가 높아짐에 따라 감소하는 채널길이가 작아져 발생되는 문제를 해결하기 위하여 반도체 기판에 돌출부를 제조한 다음, 돌출부가 감싸지도록 게이트 산화막과 게이트전극을 형성하고, 게이트전극 양측 가장자리 저부의 반도체 기판에 LDD영역 및 소오스/드레인 영역을 각각 형성하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET in a semiconductor device. In order to solve the problem caused by a decrease in the channel length, which decreases as the degree of integration increases, a gate oxide film is formed on the semiconductor substrate and then the protrusion is wrapped. And a gate electrode, and an LDD region and a source / drain region are formed on the semiconductor substrate at the bottom edges of both sides of the gate electrode.
Description
제1도는 종래의 기술로 모스펫(MOSFET)을 제조한 단면도.1 is a cross-sectional view of manufacturing a MOSFET by a conventional technique.
제2(a)도 내지 제2(d)도는 본 발명에 의해 채널길이가 증대된 모스펫을 제조하는 단계를 도시한 단면도.2 (a) to 2 (d) is a cross-sectional view showing a step of manufacturing a MOSFET with an increased channel length in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 게이트산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘층 4 : LDD영역3: polysilicon layer 4: LDD area
5 : 산화막 스페이서 6 : 소오스/드레인영역5 oxide film spacer 6 source / drain region
7 : 실리사이드막 8 : 산화막7: silicide film 8: oxide film
9 : 감광막패턴9: photosensitive film pattern
본 발명은 반도체 소자의 모스펫(MOSFET) 제조방법에 관한 것으로, 특히 채널길이가 증대되고, 자기 정렬된 폴리사이드 구조를 갖는 모스펫 제조방법에 관한 반도체 소자가 고집적화됨에 따라 자기정렬된 폴리사이드(Polycide)구조를 갖는 게이트전극이 개발되었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET of a semiconductor device, and more particularly, to a method in which a channel length is increased and a semiconductor device related to a method of manufacturing a MOSFET having a self-aligned polyside structure is highly integrated. A gate electrode having a structure has been developed.
종래의 기술에 의해 제조된 폴리사이드 구조를 갖는 모스펫을 제1도를 참조하여 설명하기로 한다.A MOSFET having a polyside structure manufactured by a conventional technique will be described with reference to FIG.
반도체 기판(1)에 게이트산화막(2) 및 폴리실리콘층(3)을 순차적으로 적층한 다음, 리소그라피 공정을 통하여 게이트전극용 폴리실리콘 패턴을 형성하고, 저농도 불순물을 기판으로 이온주입하여 LDD영역(4)을 형성하고, 게이트전극 측벽에 산화막 스페이서(5)를 형성한 다음, 고농도 불순물을 기판으로 이온주입하여 소오스/드레인영역(6)을 형성하고, 선택증착법으로 상기 폴리실리콘층(3)과 소오스/드레인영역(6)에 실리사이드막(7)을 형성한 것이다.After sequentially stacking the gate oxide film 2 and the polysilicon layer 3 on the semiconductor substrate 1, a polysilicon pattern for the gate electrode is formed through a lithography process, and ion implantation of low concentration impurities into the substrate is used to form an LDD region ( 4), an oxide spacer 5 is formed on the sidewalls of the gate electrode, and ion source implanted into the substrate to form a source / drain region 6, and then the polysilicon layer 3 is formed by selective deposition. The silicide film 7 is formed in the source / drain region 6.
상기와 같은 공정으로 형성된 모스펫은 고집적회로가 됨에 따라 채널길이가 짧아져서 문턱전압(VT)과 파괴전압(VBD)의 감소와 기판 전류 증가 등으로 모스펫의 전기적 특성이 악화되는 문제점이 발생된다.As the MOSFET formed by the above process becomes a highly integrated circuit, the channel length is shortened, and thus the electrical characteristics of the MOSFET are deteriorated due to the decrease of the threshold voltage (V T ), the breakdown voltage (V BD ), and the increase of the substrate current. .
본 발명은 상기한 문제점을 해결하기 위하여 모스펫의 채널길이를 증대시키는데 그 목적이 있다.The present invention is to increase the channel length of the MOSFET in order to solve the above problems.
본 발명에 의한 모스펫에 의하면 반도체 기판의 소정부분이 돌출된 구조로 형성되고, 상기 돌출된 구조의 반도체 기판을 둘러 쌓이도록 게이트 산화막과 게이트 전극용 폴리실리콘 패턴이 구비되고, 상기 게이트 전극용 폴리실리콘 패턴 양측 가장자리 하부의 반도체 기판에 LDD영역과 소오스/드레인영역이 구비되고 상기 게이트 전극용 폴리실리콘 패턴 상부에 실리사이드가 구비되는 것을 특징으로 한다.According to the MOSFET according to the present invention, a predetermined portion of the semiconductor substrate is formed to have a protruding structure, and a gate oxide film and a polysilicon pattern for the gate electrode are provided to surround the semiconductor substrate having the protruding structure, and the polysilicon for the gate electrode is provided. An LDD region and a source / drain region are provided on the semiconductor substrate below the edges of both patterns, and silicide is provided on the polysilicon pattern for the gate electrode.
본 발명에 의한 모스펫 제조방법에 의하면, 반도체 기판 상부에 산화막을 형성하고, 그 상부에 감광막패턴을 형성하고, 노출된 산화막과 그 하부의 반도체 기판의 일정두께를 식각하여 돌출된 형태의 반도체 기판을 형성하는 단계와,According to the method for manufacturing a MOSFET according to the present invention, an oxide film is formed on an upper portion of a semiconductor substrate, a photoresist pattern is formed on the upper portion of the semiconductor substrate, and a semiconductor substrate having a protruding shape is formed by etching a predetermined thickness between the exposed oxide film and the lower semiconductor substrate. Forming step,
상기 감광막패턴과 산화막을 제거하고, 전체적으로 게이트산화막과 폴리실리콘층을 적층하는 단계와,Removing the photoresist pattern and the oxide film, and laminating a gate oxide film and a polysilicon layer as a whole;
게이트전극 마스크를 이용한 식각공정으로 상기 폴리실리콘층의 일정부분을 제거하여 돌출부의 반도체 기판을 둘러싼 게이트 전극용 폴리실리콘층 패턴을 형성하는 단계와,Removing a portion of the polysilicon layer by an etching process using a gate electrode mask to form a polysilicon layer pattern for the gate electrode surrounding the semiconductor substrate of the protrusion;
저농도 불순물을 반도체 기판으로 이온주입하여 LDD영역을 형성하는 단계와,Ion implanting low concentration impurities into the semiconductor substrate to form an LDD region;
상기 폴리실리콘층 패턴 측벽에 산화막 스페이서를 형성한 다음, 고농도 불순물을 반도체 기판으로 이온주입하여 소오스/드레인영역을 형성하는 단계와,Forming an oxide spacer on the sidewalls of the polysilicon layer pattern and ion implanting high concentration impurities into the semiconductor substrate to form source / drain regions;
전체구조 상부에 전이금속을 형성하고, 열처리 공정을 실시하여 상기 게이트 전극용 폴리실리콘층 패턴과 소오스/드레인영역 상부에 실리사이드막을 형성하는 단계와,Forming a transition metal on the entire structure and performing a heat treatment process to form a silicide layer on the polysilicon layer pattern for the gate electrode and the source / drain regions;
실리사이드가 형성되지 않은 전이금속을 습식식각으로 제거하는 단계를 포함하는 것을 특징으로 한다.And removing the transition metal in which silicide is not formed by wet etching.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2(a)도 내지 제2(d)도는 본 발명에 의해 채널 길이가 증대된 모스펫을 제조하는 공정단계를 도시한 단면도이다.2 (a) to 2 (d) is a cross-sectional view showing a process step of manufacturing a MOSFET with an increased channel length in accordance with the present invention.
제2(a)도는 반도체 기판(1) 상부에 100-500Å 두께의 산화막(8)을 형성하고, 그 상부에 감광막패턴(9)을 형성하고, 식각공정으로 산화막(8)과 그 하부의 반도체 기판(1)을 일정두께 식각하여 돌출된 구조의 반도체 기판(1)을 형성한 단면도이다. 상기 산화막(8)은 열 공정으로 성장시킬 수 있다.FIG. 2 (a) shows an oxide film 8 having a thickness of 100-500 에 over the semiconductor substrate 1, a photoresist pattern 9 formed thereon, and an oxide film 8 and a semiconductor below A cross-sectional view of the semiconductor substrate 1 having a structure protruding by etching the substrate 1 by a predetermined thickness. The oxide film 8 may be grown by a thermal process.
제2(b)도는 상기 감광막패턴(9)을 제거한 후, HF에 의해 상기 산화막(8)을 제거하고, 반도체 기판(1)으로 문턱전압(VT) 조절용 불순물을 이온주입한 후 게이트산화막(2)과 도핑된 게이트 전극용 폴리실리콘층(3)을 반도체 기판(1) 상부에 형성한 단면도이다.In FIG. 2 (b), after the photoresist pattern 9 is removed, the oxide film 8 is removed by HF, and the ion oxide is implanted into the semiconductor substrate 1 to control the threshold voltage V T. 2) and the doped polysilicon layer 3 for the gate electrode are formed on the upper surface of the semiconductor substrate 1.
제2(c)도는 게이트 마스크를 이용한 식각공정으로 상기 돌출부위의 반도체 기판(1)을 감싸는 구조의 게이트 전극용 폴리실리콘층 패턴(3')을 형성하고, 저농도 불순물을 반도체 기판(1)에 경사지게 이온주입하여 LDD(Lightly Doped Drain)영역(4)을 형성한 단면도이다.FIG. 2 (c) shows a polysilicon layer pattern 3 ′ for a gate electrode having a structure surrounding the semiconductor substrate 1 on the protruding portion by an etching process using a gate mask, and a low concentration impurity is deposited on the semiconductor substrate 1. It is sectional drawing in which the LDD (Lightly Doped Drain) area | region 4 was formed by ion implantation inclinedly.
제2(d)도는 상기 게이트 전극용 폴리실리콘층 패턴(3') 측벽에 산화막 스페이서(5)를 형성하고, 고농도 불순물을 반도체 기판(1)으로 이온주입시켜 LDD영역(4)과 중첩되는 부분에 소오스/드레인영역(6)을 형성한 다음, 전체구조 상부에 전이 금속(도시되지 않음)을 증착하고 열처리 공정을 실시하여 상기 게이트 전극용 폴리실리콘층 패턴(3)과 소오스/드레인영역(6) 상부에 실리사이드막(7)을 형성하고, 실리사이드가 되지 않은 전이금속을 황산과 과산화 수소의 혼합액에서 습식식각하여 제거한 단면도이다.FIG. 2 (d) shows an oxide spacer 5 formed on the sidewall of the polysilicon layer pattern 3 ′ for the gate electrode, and implants high concentration impurities into the semiconductor substrate 1 to overlap the LDD region 4. After forming the source / drain regions 6 on the substrate, a transition metal (not shown) is deposited on the entire structure, and a heat treatment process is performed to perform the polysilicon layer pattern 3 and the source / drain regions 6 on the gate electrode. ) A cross-sectional view of the silicide film 7 formed on the upper side and wetted etching of the transition metal that is not silicide in the mixed solution of sulfuric acid and hydrogen peroxide.
상기한 본 발명에 의하면 반도체 소자의 고집적화에 의해 줄어드는 유효채널 길이를 연장시켜 모스펫의 전기적 특성을 개선시키는 효과가 있다.According to the present invention described above, the effective channel length reduced by high integration of the semiconductor device is extended, thereby improving the electrical characteristics of the MOSFET.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031828A KR0146276B1 (en) | 1993-12-31 | 1993-12-31 | Method for manufacturing mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031828A KR0146276B1 (en) | 1993-12-31 | 1993-12-31 | Method for manufacturing mosfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021788A KR950021788A (en) | 1995-07-26 |
| KR0146276B1 true KR0146276B1 (en) | 1998-11-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930031828A KR0146276B1 (en) | 1993-12-31 | 1993-12-31 | Method for manufacturing mosfet |
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| KR100835522B1 (en) * | 2006-12-27 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing thereof |
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1993
- 1993-12-31 KR KR1019930031828A patent/KR0146276B1/en not_active IP Right Cessation
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| KR950021788A (en) | 1995-07-26 |
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