KR100364794B1 - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR100364794B1 KR100364794B1 KR1019990065535A KR19990065535A KR100364794B1 KR 100364794 B1 KR100364794 B1 KR 100364794B1 KR 1019990065535 A KR1019990065535 A KR 1019990065535A KR 19990065535 A KR19990065535 A KR 19990065535A KR 100364794 B1 KR100364794 B1 KR 100364794B1
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- insulating film
- forming
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- gate
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 241000293849 Cordylanthus Species 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
리세스 게이트산화막을 형성함에 있어서, 식각데미지를 줄이고 공정을 단순화시키기에 알맞은 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 제 1 도전형의 반도체기판의 소정영역상에 절연막패턴을 형성하는 공정, 열산화공정으로 상기 노출된 제 1 도전형 반도체기판상에 절연막을 형성할 뿐만아니라, 버즈 빅(bird's beak)현상에 의해서 상기 절연막패턴 하면에도 상기 절연막이 연장 형성되도록 하여 상기 절연막패턴 하부에서 리세스되는 절연막을 형성하는 공정, 상기 절연막패턴을 제거하는 공정, 상기 절연막의 리세스된 부분만 남도록 상기 절연막을 식각해서 게이트절연막을 형성하는 공정, 상기 게이트절연막 양측의 상기 반도체기판에 제 1 불순물영역을 형성하는 공정, 상기 리세스된 게이트절연막상에 리세스된 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.In order to provide a method for manufacturing a semiconductor device suitable for reducing etching damage and simplifying a process in forming a recess gate oxide film, a method of manufacturing a semiconductor device for achieving the above object is a semiconductor of a first conductivity type. Forming an insulating film pattern on a predetermined region of the substrate, and forming an insulating film on the exposed first conductive semiconductor substrate by a thermal oxidation process, and also on the lower surface of the insulating film pattern by a bird's beak phenomenon. Forming an insulating film recessed under the insulating film pattern to extend the insulating film, removing the insulating film pattern, etching the insulating film so that only the recessed portion of the insulating film remains, and forming a gate insulating film; Forming a first impurity region in the semiconductor substrate on both sides of the gate insulating film; Seudoen characterized in that the gate dielectric comprises a step of forming a gate electrode film process Erie.
Description
본 발명은 반도체소자에 대한 것으로, 특히 공정을 단순화시키면서 게이트산화막에 데미지가 발생하는 것을 방지하기 위한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for preventing damage to a gate oxide film while simplifying a process.
첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a conventional semiconductor device is as follows.
도 1a 내지 도 1f는 종래 반도체소자의 제조방법을 나타낸 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
종래 반도체소자의 제조방법은 먼저 도 1a에 도시한 바와 같이 필드영역과 액티브영역이 정의된 P형 반도체기판(1)의 필드영역에 필드산화막(2)을 형성한다.In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, a field oxide film 2 is formed in a field region of a P-type semiconductor substrate 1 in which a field region and an active region are defined.
그리고 전면에 열산화공정으로 산화막(3)을 증착하고, 산화막(3)상에 질화막(4)을 증착한다. 이후에 질화막(4)상에 감광막(5)을 도포하고, 노광 및 현상공정으로 일정영역이 오픈되도록 감광막(5)을 패터닝한다. 이때 일정영역은 차후에 게이트전극이 형성될 부분을 의미한다.The oxide film 3 is deposited on the entire surface by a thermal oxidation process, and the nitride film 4 is deposited on the oxide film 3. Thereafter, the photoresist film 5 is coated on the nitride film 4, and the photoresist film 5 is patterned so that a predetermined region is opened by exposure and development processes. In this case, the predetermined region means a portion where the gate electrode is to be formed later.
이후에 패터닝된 감광막(5)을 마스크로 질화막(4)을 식각하여 산화막(3)이 드러나게 한다.Thereafter, the nitride film 4 is etched using the patterned photosensitive film 5 as a mask so that the oxide film 3 is exposed.
다음에 도 1b에 도시한 바와 같이 감광막(5)을 제거하고, 차후에 반도체기판(1)에 리세스 영역을 만들기 위해서 질화막(4)을 마스크로 열처리공정을 진행하여서 질화막(4) 사이의 반도체기판(1) 하부에 리세스산화막(6)을 형성한다.Next, as shown in FIG. 1B, the photoresist film 5 is removed and a heat treatment process is performed using the nitride film 4 as a mask in order to form a recessed region in the semiconductor substrate 1. (1) A recess oxide film 6 is formed below.
이후에 도 1c에 도시한 바와 같이 전면에 감광막(7)을 도포한 후에 액티브영역을 제외한 필드산화막(2)의 일영역에만 남도록 노광 및 현상공정으로 감광막(7)을 선택적으로 패터닝한다.Subsequently, after the photoresist film 7 is applied to the entire surface as shown in FIG. 1C, the photoresist film 7 is selectively patterned by an exposure and development process so as to remain in only one region of the field oxide film 2 except for the active region.
그리고 패터닝된 감광막(7)을 마스크로 액티브영역에 저농도 N형(N-) 불순물이온을 주입해서 리세스산화막(6)의 양측 반도체기판(1)에 저농도 불순물영역(8)을 형성한다.A low concentration impurity region 8 is formed in both semiconductor substrates 1 of the recess oxide film 6 by implanting low concentration N-type (N−) impurity ions into the active region using the patterned photosensitive film 7 as a mask.
다음에 도 1d에 도시한 바와 같이 질화막(4)을 마스크로 드러난 리세스 산화막(6)을 제거하여서 반도체기판(1)이 드러나도록 한다. 이에 따라서 반도체기판(1)에는 리세스영역이 형성된다.Next, as shown in FIG. 1D, the recess oxide film 6 having the nitride film 4 exposed as a mask is removed to expose the semiconductor substrate 1. As a result, a recess region is formed in the semiconductor substrate 1.
그리고 질화막(4)을 마스크로 리세스된 반도체기판(1)의 표면에 문턱전압 조절이온을 주입해서 문턱전압 조절이온 주입영역(9)을 형성한다.The threshold voltage regulation ion implantation region 9 is formed by implanting the threshold voltage regulation ion into the surface of the semiconductor substrate 1 recessed using the nitride film 4 as a mask.
이후에 도 1e에 도시한 바와 같이 감광막(7)을 제거하고, 리세스된 반도체기판(1)에 열산화공정으로 게이트산화막(10)을 형성한다. 이때 산화막(3)에 의해서 리세스된 반도체기판(1)에 형성된 게이트산화막(10)의 양측에 버즈빅(Bird's beak) 현상이 일어날 수 있다.Thereafter, as shown in FIG. 1E, the photoresist film 7 is removed and the gate oxide film 10 is formed on the recessed semiconductor substrate 1 by a thermal oxidation process. In this case, a bird's beak phenomenon may occur at both sides of the gate oxide film 10 formed in the semiconductor substrate 1 recessed by the oxide film 3.
다음에 전면에 폴리실리콘층을 증착한 후에, 게이트형성 마스크를 이용한 포토공정으로 폴리실리콘층을 식각해서 리세스된 반도체기판(1)상의 게이트산화막(10) 및 그 양측의 질화막(4) 상부에 굴곡을 갖는 게이트전극(11)을 형성한다.Next, after the polysilicon layer is deposited on the entire surface, the polysilicon layer is etched by a photo process using a gate forming mask, and then the gate oxide film 10 on the recessed semiconductor substrate 1 and the nitride film 4 on both sides thereof. The curved gate electrode 11 is formed.
그리고 도 1f에 도시한 바와 같이 전면에 감광막(12)을 도포한 후에 노광 및 현상공정으로 액티브영역을 제외한 필드산화막(2) 상측의 질화막(4)상에만 감광막(11)이 남도록 선택적으로 감광막(12)을 패터닝한다.As shown in FIG. 1F, after the photoresist film 12 is applied to the entire surface, the photoresist film 11 is selectively left so that the photoresist film 11 remains only on the nitride film 4 on the upper side of the field oxide film 2 except the active region in the exposure and development processes. Pattern 12).
이후에 패터닝된 감광막(12)을 마스크로 게이트전극(11) 양측의 반도체기판(1)내에 고농도 N형(N+) 불순물이온을 주입해서 고농도 소오스/드레인영역(13)을 형성하고, 감광막(12)을 제거한다.Subsequently, a high concentration N-type (N +) impurity ion is implanted into the semiconductor substrate 1 on both sides of the gate electrode 11 using the patterned photoresist film 12 as a mask to form a high concentration source / drain region 13, and then a photoresist film 12. ).
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 리세스 산화막을 형성하고 식각한 후에 식각된 부분에 게이트산화막을 형성하는 것이므로, 리세스산화막을 식각할 때 산화막이 손상되어서 차후에 형성될 소자의 특성이 저하되는 문제가 발생한다.First, since the gate oxide film is formed on the etched portion after the recess oxide film is formed and etched, the oxide film is damaged when the recess oxide film is etched, thereby deteriorating the characteristics of the device to be formed later.
둘째, 게이트산화막을 형성하기 위해서 리세스산화막을 형성한 후 제거하는 공정이 필요하므로 그 방법이 복잡하다.Second, in order to form the gate oxide film, a process of forming and removing the recess oxide film is necessary, and thus the method is complicated.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 리세스 게이트산화막을 형성함에 있어서, 식각데미지를 줄이고 공정을 단순화시키기에 알맞은 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for reducing etching damage and simplifying a process in forming a recess gate oxide film.
도 1a 내지 도 1f는 종래 반도체소자의 제조방법을 나타낸 공정단면도1A to 1F are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2g는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도2A through 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 질화막31 semiconductor substrate 32 nitride film
33 : 산화막 33a : 게이트산화막33: oxide film 33a: gate oxide film
34,37 : 감광막 35 : 저농도 불순물영역34,37: photosensitive film 35: low concentration impurity region
36 : 폴리실리콘층 36a : 게이트전극36 polysilicon layer 36a gate electrode
38 : 측벽스페이서 39 : 고농도 소오스/드레인영역38 side wall spacer 39 high concentration source / drain region
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법 제 1 도전형의 반도체기판의 소정영역상에 절연막패턴을 형성하는 공정, 열산화공정으로 상기 노출된 제 1 도전형 반도체기판상에 절연막을 형성할 뿐만아니라, 버즈 빅(bird's beak)현상에 의해서 상기 절연막패턴 하면에도 상기 절연막이 연장 형성되도록 하여 상기 절연막패턴 하부에서 리세스되는 절연막을 형성하는 공정, 상기 절연막패턴을 제거하는 공정, 상기 절연막의 리세스된 부분만 남도록 상기 절연막을 식각해서 게이트절연막을 형성하는 공정, 상기 게이트절연막 양측의 상기 반도체기판에 제 1 불순물영역을 형성하는 공정, 상기 리세스된 게이트절연막상에 리세스된 게이트전극을 형성하는 공정을 포함함을 특징으로 한다.Method of manufacturing a semiconductor device of the present invention for achieving the above object Forming an insulating film pattern on a predetermined region of a first conductive semiconductor substrate, an insulating film on the exposed first conductive semiconductor substrate by a thermal oxidation process Forming an insulating film recessed under the insulating film pattern so that the insulating film extends to the lower surface of the insulating film pattern due to a bird's beak phenomenon, and removing the insulating film pattern. Etching the insulating film so that only the recessed portion of the insulating film remains, forming a gate insulating film, forming a first impurity region in the semiconductor substrate on both sides of the gate insulating film, and a gate recessed on the recessed gate insulating film. It characterized in that it comprises a step of forming an electrode.
첨부 도면을 참조하여 본 발명 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for manufacturing a semiconductor device of the present invention will be described.
도 2a 내지 도 2g는 본 발명 실시예에 따른 반도체소자의 제조방법을 나타낸 공정단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
본 발명의 실시예에 따른 반도체소자의 제조방법은 먼저, 도 2a에 도시한 바와 같이 P형의 반도체기판(31)상에 질화막(32)을 증착한 후에 차후에 게이트전극을 형성할 영역을 정의한다. 이후에 포토공정으로 정의된 부분의 질화막(32)만 남도록 이방성 식각한다.In the method of manufacturing a semiconductor device according to the embodiment of the present invention, first, as shown in FIG. . After that, anisotropic etching is performed so that only the nitride film 32 of the portion defined by the photo process remains.
그리고 도 2b에 도시한 바와 같이 전면에 열산화공정을 진행해서 노출된 P형 반도체기판(31)상에 게이트산화막의 두께에 해당하는 산화막(33)을 형성한다. 이때 산화막(33)은 버즈 빅(bird's beak)현상에 의해서 질화막(32)하면까지도 연장 형성되는데, 반도체기판(31)상에 형성된 산화막(33)보다 질화막(32) 하면에 연장 형성된 산화막(33)이 그 두께가 얇으므로 산화막(33)은 질화막(32) 하부에서 움푹 패인(리세스된) 구성을 하게 된다.As shown in FIG. 2B, an oxide film 33 corresponding to the thickness of the gate oxide film is formed on the exposed P-type semiconductor substrate 31 by thermal oxidation. At this time, the oxide film 33 extends to the lower surface of the nitride film 32 due to a bird's beak phenomenon. The oxide film 33 is formed to extend on the lower surface of the nitride film 32 rather than the oxide film 33 formed on the semiconductor substrate 31. Since the thickness thereof is thin, the oxide film 33 has a concave (recessed) configuration under the nitride film 32.
이후에 도 2c에 도시한 바와 같이 질화막(32)을 제거한다.Thereafter, as shown in FIG. 2C, the nitride film 32 is removed.
다음에 도 2d에 도시한 바와 같이 산화막(33)의 전면에 감광막(34)을 도포한 후에, 게이트전극 형성할 부분을 정의한 후에 정의된 부분의 감광막(34)만 남도록 노광 및 현상공정으로 선택적으로 감광막(34)을 패터닝한다.Next, as shown in FIG. 2D, after the photosensitive film 34 is applied to the entire surface of the oxide film 33, the portions to be formed on the gate electrode are defined, and then selectively exposed and developed so that only the photosensitive film 34 of the defined portion remains. The photosensitive film 34 is patterned.
그리고 도 2e에 도시한 바와 같이 패터닝된 감광막(34)을 마스크로 산화막(33)을 식각하여 게이트산화막(33a)을 형성한 후에 감광막(34)을 제거한다.As shown in FIG. 2E, the oxide film 33 is etched using the patterned photosensitive film 34 as a mask to form the gate oxide film 33a, and then the photosensitive film 34 is removed.
이후에 저농도 N형(N-) 불순물이온을 주입해서 게이트산화막(33a)의 양측에 저농도 불순물영역(35)을 형성한다. 이때 중앙에 리세스영역이 형성된 게이트산화막(33a)이 마스크 역할을 한다.Thereafter, low concentration N-type (N−) impurity ions are implanted to form low concentration impurity regions 35 on both sides of the gate oxide film 33a. In this case, the gate oxide film 33a having the recessed region formed in the center serves as a mask.
그리고 도 2f에 도시한 바와 같이 전면에 폴리실리콘층(36)을 증착한 후에 폴리실리콘층(36)상에 감광막(37)을 도포한 후에 노광 및 현상공정으로 게이트산화막(33a)상측에만 감광막(37)이 남도록 선택적으로 패터닝한다.As shown in FIG. 2F, after the polysilicon layer 36 is deposited on the entire surface, the photosensitive layer 37 is coated on the polysilicon layer 36, and then the photoresist layer is formed only on the upper side of the gate oxide layer 33a by an exposure and development process. Selectively pattern so that 37) remains.
다음에 도 2g에 도시한 바와 같이 패터닝된 감광막(37)을 마스크로 폴리실리콘층(36)을 식각하여 리세스된 게이트전극(36a)을 형성한다. 이때 게이트산화막(33a)의 중앙에 리세스된 부분이 있으므로 게이트전극(36a)도 리세스된 게이트산화막(33a)상부 를 따라서 굴곡을 갖고 형성된다. 이후에 감광막(37)을 제거한다.Next, as shown in FIG. 2G, the polysilicon layer 36 is etched using the patterned photosensitive film 37 as a mask to form a recessed gate electrode 36a. At this time, since there is a recessed portion in the center of the gate oxide film 33a, the gate electrode 36a is also formed along the upper portion of the recessed gate oxide film 33a. Thereafter, the photosensitive film 37 is removed.
그리고 전면에 산화막을 증착한 후에 에치백하여 게이트산화막(33a)과 게이트전극(36a)의 양측면에 측벽스페이서(38)를 형성한다.After the oxide film is deposited on the entire surface, it is etched back to form sidewall spacers 38 on both sides of the gate oxide film 33a and the gate electrode 36a.
다음에 측벽스페이서(38)와 게이트전극(33a)을 마스크로 양측 반도체기판(31)에 고농도 N형(N+) 불순물이온을 주입해서 고농도 소오스/드레인영역(39)을 형성한다.Next, high concentration N-type (N +) impurity ions are implanted into both semiconductor substrates 31 using the sidewall spacers 38 and the gate electrode 33a as a mask to form a high concentration source / drain region 39.
상기와 같은 본 발명 반도체소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the following effects.
한번의 산화공정으로 리세스된 게이트산화막을 형성할 수 있으므로 게이트산화막의 식각 데미지(damage)를 줄일 수 있고, 공정을 단순화할 수 있다.Since the gate oxide film is recessed in one oxidation process, the etch damage of the gate oxide film can be reduced, and the process can be simplified.
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