KR20010011002A - Forming method for transistor of semiconductor device - Google Patents
Forming method for transistor of semiconductor device Download PDFInfo
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- KR20010011002A KR20010011002A KR1019990030177A KR19990030177A KR20010011002A KR 20010011002 A KR20010011002 A KR 20010011002A KR 1019990030177 A KR1019990030177 A KR 1019990030177A KR 19990030177 A KR19990030177 A KR 19990030177A KR 20010011002 A KR20010011002 A KR 20010011002A
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- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 35
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 38
- 239000010937 tungsten Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 25
- -1 tungsten nitride Chemical class 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 19
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 특히 디램 소자에서 핫캐리어 ( hot carrier ) 에 의한 트랜지스터 펀치쓰루우 ( punchthrough ) 을 억제하기 위하여 엘.디.디. ( lightly doped drain, 이하에서 LDD 라 함 ) 구조의 트랜지스터를 형성하되, 절연막 스페이서 없이 금속게이트전극이 구비되도록 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor in a semiconductor device, and more particularly, to suppress transistor punchthrough due to hot carriers in DRAM devices. The present invention relates to a technique of forming a transistor having a lightly doped drain (hereinafter referred to as LDD) structure and having a metal gate electrode without an insulating layer spacer.
반도체소자가 고집적화될수록 열공정이 최소화되고 불순물의 농도가 더욱 얇게 진행되어 이에 따른 전류나 저항 특성이 더욱 열악해지고 있다.As semiconductor devices become more integrated, thermal processes are minimized and impurities are thinner, resulting in worse current or resistance characteristics.
이러한 문제점을 개선하고자 기판이나 트랜지스터의 전반적인 불순물 농도를 높혀가고 있는 추세이다.In order to improve this problem, the overall impurity concentration of a substrate or a transistor is increasing.
상기 트랜지스터를 동작시킬때 드레인 부근에서 큰 전계를 발생하게 되고, 이 전계에 의하여 핫 캐리어 ( hot carrier ) 가 형성되고, 이로 인하여 트랜지스터의 채널 길이가 길어지고 소오스 ( source ) 와 드레인 ( drain ) 사이에서 펀치쓰루 효과 ( punch through effect ) 가 발생됨으로써 문턱전압이 낮아져 낮은 전압에서도 브레이크다운 ( breakdown ) 이 발생된다.When the transistor is operated, a large electric field is generated in the vicinity of the drain, and a hot carrier is formed by the electric field, which causes a long channel length of the transistor and between the source and the drain. The punch through effect causes the threshold voltage to drop, resulting in breakdown even at low voltages.
한편, 상기 핫캐리어란 모스 트랜지스터 ( MOS transistor ) 에서 인가되는 게이트 전압이나 드레인 전압 혹은 기판 바이어스 등에 의하여 산화막 부근의 필드영역에 강한 전장이 형성되면, 상기 필드영역의 자유운반자 ( free carrier ) 들이 많은 운동에너지를 갖게되는데 이런 자유운반자를 핫캐리어라고 한다. 그리고, 상기 핫캐리어가 산화막과 실리콘간의 에너지 장벽을 넘어 산화막으로 주입되는 경우를 핫캐리어 효과 ( hot carrier effect ) 라고 한다.On the other hand, when a strong electric field is formed in the field region near the oxide film due to the gate voltage, the drain voltage, or the substrate bias applied by the MOS transistor, the free carriers in the field region move a lot. You have energy, and these free carriers are called hot carriers. In addition, a case in which the hot carrier is injected into the oxide film over the energy barrier between the oxide film and the silicon is called a hot carrier effect.
상기한 핫 캐리어에 의한 트랜지스터의 특성 열화를 방지하기 위하여, 현재는 LDD 구조의 트랜지스터를 형성하여 사용함으로써 드레인 부근의 전계를 감소시켜 트랜지스터의 신뢰성을 향상시켰다.In order to prevent the deterioration of the characteristics of the transistor by the hot carrier described above, by forming and using a transistor having an LDD structure, the electric field near the drain is reduced to improve the reliability of the transistor.
그러나, 회로의 동작을 고려하여 소오스와 드레인이 정해져 있는 트랜지스터에서 LDD 구조는 소오스쪽 저항을 크게 하여 트랜지스터의 전류-전압 특성이 열화되게 한다.However, in the transistor where the source and the drain are determined in consideration of the operation of the circuit, the LDD structure increases the source-side resistance so that the current-voltage characteristic of the transistor is degraded.
도시되진않았으나, 종래기술에 따른 LDD 구조의 트랜지스터를 설명하면 다음과 같다.Although not shown, the transistor of the LDD structure according to the prior art will be described.
먼저, 반도체기판 상의 활성영역을 정의하는 소자분리영역을 정의하고, 상기 활성영역을 포함한 전체표면상부에 게이트절연막과 게이트전극용 도전체를 증착하고 이를 패터닝하여 게이트전극을 형성한다.First, a device isolation region defining an active region on a semiconductor substrate is defined, and a gate insulating film and a conductor for a gate electrode are deposited on the entire surface including the active region and patterned to form a gate electrode.
그리고, 상기 게이트전극을 마스크로하여 상기 반도체기판에 저농도의 불순물을 주입하여 저농도의 소오스/드레인 접합영역을 형성한다.A low concentration source / drain junction region is formed by implanting a low concentration of impurities into the semiconductor substrate using the gate electrode as a mask.
그리고, 상기 게이트전극 측벽에 절연막 스페이서를 형성하고 상기 절연막 스페이서와 게이트전극을 마스크로하여 상기 반도체기판에 고농도의 불순물을 주입하여 고농도의 소오스/드레인 접합영역을 형성함으로써 LDD 구조의 트랜지스터를 형성한다.A transistor having an LDD structure is formed by forming an insulating film spacer on the sidewall of the gate electrode and injecting a high concentration of impurities into the semiconductor substrate using the insulating film spacer and the gate electrode as a mask to form a high concentration source / drain junction region.
상기한 종래기술은 0.13 ㎛ 이하의 디자인룰 ( degine rule ) 을 갖는 디램 소자의 제조시 워드라인의 높은 Rs 값으로 인하여 소자의 특성을 열화시킨다.The prior art deteriorates device characteristics due to the high Rs value of the word line in the fabrication of DRAM devices having a degine rule of 0.13 μm or less.
따라서, 최근에는 0.13 ㎛ 이하 디자인룰의 디램 제조시 워드라인의 Rs 값을 낮추기 위해 실리사이드나 금속-폴리실리콘의 적층구조를 형성하고 그 측벽에 절연막 스페이서를 형성하여 LDD 구조를 갖도록 형성하였다.Therefore, in recent years, in order to lower the Rs value of a word line when manufacturing a DRAM having a design rule of 0.13 μm or less, a lamination structure of silicide or metal-polysilicon was formed, and an insulating film spacer was formed on the sidewall thereof to have an LDD structure.
그러나, 순수하게 금속만으로 게이트전극을 형성하는 경우는 건식식각 패터닝 ( dry etch pattering ) 공정시 염소가스만으로는 건식식각이 어렵고 불소가스로는 게이트산화막이 충분한 식각선택비를 얻기 힘들기 때문에 실리콘 기판이 심하게 손상된다.However, in the case of forming the gate electrode using pure metal only, the silicon substrate is severely damaged because dry etching is difficult with chlorine gas only in the dry etching patterning process, and the gate oxide film cannot obtain sufficient etching selectivity with fluorine gas. do.
더구나, LDD 접합을 형성하기 위하여 워드라인의 형성공정후 절연막 스페이서를 형성하기 위한 이방성식각공정시 반도체기판의 표면이 손상되어 접합누설전류가 증가되고, LDD 이온주입공정시 반도체기판의 표면이 손상된다.In addition, the surface of the semiconductor substrate is damaged during the anisotropic etching process for forming the insulating film spacer after the word line forming process to form the LDD junction, thereby increasing the junction leakage current and the surface of the semiconductor substrate during the LDD ion implantation process. .
상기한 바와같이 종래기술에 따른 LDD 구조의 트랜지스터 형성방법은 반도체기판 표면에 많은 손상을 주어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, the method of forming a transistor having an LDD structure according to the prior art has a lot of damage to the surface of the semiconductor substrate, thereby degrading the characteristics and reliability of the semiconductor device and thereby making it difficult to integrate the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 텅스텐 질화막과 텅스텐막의 적층구조로 게이트전극을 형성하고 절연막 스페이서의 형성공정없이 0.13 ㎛ 이하의 디자인룰에 적용할 수 있는 LDD 구조의 트랜지스터를 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a transistor having a LDD structure that can be applied to a design rule of 0.13 μm or less without forming a gate electrode in a stacked structure of a tungsten nitride film and a tungsten film and forming an insulating film spacer is formed. Accordingly, an object of the present invention is to provide a method for forming a transistor of a semiconductor device, which improves the characteristics and reliability of the semiconductor device and thereby enables high integration of the semiconductor device.
도 1a 내지 도 1c 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a transistor forming method of a semiconductor device in accordance with an embodiment of the present invention.
〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>
11 : 반도체기판 13 : 게이트산화막11: semiconductor substrate 13: gate oxide film
15 : 텅스텐 질화막 17 : 텅스텐막15: tungsten nitride film 17: tungsten film
19 : 감광막패턴 21 : 고농도의 불순물 접합영역19: photosensitive film pattern 21: high concentration impurity junction region
23 : 저농도의 불순물 접합영역23: low concentration impurity junction region
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상부에 게이트절연막을 형성하는 공정과,Forming a gate insulating film over the semiconductor substrate;
상기 게이트절연막 상부에 텅스텐질화막과 텅스텐막 적층구조를 형성하는 공정과,Forming a tungsten nitride film and a tungsten film stacked structure on the gate insulating film;
상기 텅스텐막과 일정두께의 텅스텐질화막을 건식식각하는 공정과,Dry etching the tungsten film and the tungsten nitride film having a predetermined thickness;
상기 텅스텐 질화막을 습식식각하여 상기 적층구조를 언더컷이 구비되는 "T" 자 형태로 형성하되, 상기 게이트절연막은 남기는 공정과,Wet etching the tungsten nitride film to form the stacked structure in a “T” shape having an undercut, leaving the gate insulating film;
상기 반도체기판에 고농도의 불순물을 이온주입하여 상기 언더컷이 유발되는 부분 하측에 저농도의 불순물 접합영역이 구비되는 LDD 구조의 접합영역을 형성하는 공정을 포함하는 것을 특징으로한다.And implanting a high concentration of impurities into the semiconductor substrate to form an LDD structure junction region having a low concentration impurity junction region under a portion where the undercut is caused.
한편, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 텅스텐 질화막과 텅스텐막의 적층구조를 패터닝할때 건식식각공정과 습식식각공정을 조합하여 실시하되, 상기 텅스텐막과 일정두께의 텅스텐 질화막을 건식방법으로 패터닝하고 남아있는 상기 텅스텐 질화막을 습식방법으로 식각하여 상기 텅스텐막의 하부로 언더컷 ( under cut ) 이 구비되도록 형성하여 "T" 자 형태로 게이트전극을 형성하고 별도의 절연막 스페이서 없이 한번의 불순물 이온주입공정으로 LDD 구조의 불순물 접합영역을 형성함으로써 반도체기판의 손상없이 트랜지스터를 형성하여 표면 손상으로 인한 접합누설전류를 감소시킬 수 있도록 하는 것이다.Meanwhile, in order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention may be performed by combining a dry etching process and a wet etching process when patterning a layered structure of a tungsten nitride film and a tungsten film. Patterning the tungsten nitride film by a dry method and etching the remaining tungsten nitride film by a wet method to form an undercut under the tungsten film to form a gate electrode in a “T” shape and a separate insulating film spacer By forming an impurity junction region of the LDD structure by a single impurity ion implantation process, a transistor can be formed without damaging the semiconductor substrate to reduce the junction leakage current due to surface damage.
이때, 상기 텅스텐 질화막의 습식식각방법은, 실리콘산화막과의 식각선택비 차이로 인하여 실리콘산화막인 게이트산화막은 식각되지않고 않고 남게 하는 솔벤트 크리닝 ( cleaning ) 공정을 이용하여 실시함으로써 반도체기판 표면에 게이트산화막이 남고 후속공정인 이온주입공정에서 상기 게이트산화막이 스크린 산화막으로 사용되어 반도체기판의 표면손상을 방지한다.At this time, the wet etching method of the tungsten nitride film is performed by using a solvent cleaning process in which the gate oxide film, which is a silicon oxide film, is left without being etched due to the difference in etching selectivity with the silicon oxide film. In this remaining ion implantation process, the gate oxide film is used as the screen oxide film to prevent surface damage of the semiconductor substrate.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 활성영역을 정의하는 소자분리막(도시안됨)을 형성한다.First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 11.
그리고, 상기 반도체기판(11) 상부에 게이트산화막(13)을 일정두께 형성한다. 이때, 상기 게이트산화막(13)은 실리콘산화막으로 형성된 것이다A gate oxide film 13 is formed on the semiconductor substrate 11 at a predetermined thickness. In this case, the gate oxide film 13 is formed of a silicon oxide film.
그 다음, 상기 게이트산화막(13) 상부에 텅스텐질화막(15)과 텅스텐막(17)을 각각 일정두께 형성한다.Next, a tungsten nitride film 15 and a tungsten film 17 are formed on the gate oxide film 13, respectively.
그리고, 상기 텅스텐막(17) 상부에 감광막패턴(19)을 형성한다.A photosensitive film pattern 19 is formed on the tungsten film 17.
이때, 상기 감광막패턴(19)은 게이트전극마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 1a)In this case, the photoresist pattern 19 is formed by an exposure and development process using a gate electrode mask (not shown). (FIG. 1A)
그 다음, 상기 감광막패턴(19)을 마스크로하여 상기 텅스텐막(17)과 일정두께의 텅스텐질화막(15)을 건식식각한다.Next, the tungsten film 17 and the tungsten nitride film 15 having a predetermined thickness are dry-etched using the photosensitive film pattern 19 as a mask.
이때, 상기 텅스텐막(17)과 일정두께의 텅스텐질화막(15)의 건식식각공정은 불소계 식각가스를 이용하여 실시한다.At this time, the dry etching process of the tungsten film 17 and the tungsten nitride film 15 of a predetermined thickness is performed using a fluorine-based etching gas.
그 다음, 상기 감광막패턴(19)을 플라즈마를 이용하여 제거한다.Next, the photoresist pattern 19 is removed using plasma.
그리고, 상기 텅스텐질화막(17)을 습식방법으로 식각하되, 상기 게이트산화막(13)의 손상없이 실시할 수 있도록 솔벤트 케미컬을 이용하여 실시함으로써 상기 텅스텐막(17)의 하부에 위치한 상기 텅스텐 질화막(15)이 측면식각되어 상기 텅스텐막(17)의 하부로 언더컷이 형성된 "T" 형태의 텅스텐질화막(15)과 텅스텐막(17)의 적층구조를 갖는 게이트전극을 형성한다. (도 1b)In addition, the tungsten nitride film 17 is etched by a wet method, but the solvent is applied using a solvent chemical so as to be performed without damaging the gate oxide film 13. ) Is laterally etched to form a gate electrode having a lamination structure of a tungsten nitride film 15 having a "T" shape and a tungsten film 17 having an undercut formed under the tungsten film 17. (FIG. 1B)
그 다음, 상기 반도체기판(11)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역(21)과 저농도의 불순물 접합영역(23)이 구비되는 LDD 구조의 접합영역을 형성한다.Then, a high concentration of impurities are implanted into the semiconductor substrate 11 to form a junction region having an LDD structure including a high concentration impurity junction region 21 and a low concentration impurity junction region 23.
여기서, 상기 고농도의 불순물 이온주입공정은 상기 반도체기판(11) 표면에 형성된 상기 게이트산화막(13)이 스크린 산화막으로 사용되어 반도체기판(11)의 표면이 손상되는 현상을 방지한다. (도 1c)In the high concentration impurity ion implantation process, the gate oxide film 13 formed on the surface of the semiconductor substrate 11 is used as a screen oxide film to prevent the surface of the semiconductor substrate 11 from being damaged. (FIG. 1C)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 게이트산화막이 구비되는 반도체기판의 활성영역 상부에 "T" 자 형의 텅스텐 질화막과 텅스텐막 적층구조로 게이트전극을 형성하고 불순물 이온주입공정을 실시하여 LDD 구조의 불순물 접합영역을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 0.13 ㎛ 이하의 디자인룰을 갖는 고집적화된 반도체소자에 적용할 수 있는 효과를 제공한다.As described above, in the method of forming a transistor of a semiconductor device according to the present invention, a gate electrode is formed in a stacked structure of a “T” shaped tungsten nitride film and a tungsten film on an active region of a semiconductor substrate having a gate oxide film and impurity ions. The implantation process is performed to form the impurity junction region of the LDD structure, thereby improving the characteristics and reliability of the semiconductor device and providing an effect that can be applied to a highly integrated semiconductor device having a design rule of 0.13 μm or less.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100598051B1 (en) * | 2005-02-07 | 2006-07-10 | 삼성전자주식회사 | Method for fabricating semiconductor device |
| CN107706107A (en) * | 2017-11-15 | 2018-02-16 | 上海华力微电子有限公司 | A kind of process for eliminating wet etching blocking layer of metal silicide undercut flaw |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100598051B1 (en) * | 2005-02-07 | 2006-07-10 | 삼성전자주식회사 | Method for fabricating semiconductor device |
| CN107706107A (en) * | 2017-11-15 | 2018-02-16 | 上海华力微电子有限公司 | A kind of process for eliminating wet etching blocking layer of metal silicide undercut flaw |
| CN107706107B (en) * | 2017-11-15 | 2020-02-18 | 上海华力微电子有限公司 | Process method for eliminating undercut defect of wet etching metal silicide barrier layer |
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