KR940010923B1 - Mosfet and manufacturing method thereof - Google Patents

Abstract

The method includes the steps of sequentially forming a first gate insulating film (20), a first gate electrode layer, a second gate electrode layer and a third gate electrode on a substrate (10) to etch the second and third electrodes by using a gate mask, using the second and third gate electrodes as masks to implant impurities into the source and drain region of the substrate, forming a fourth gate electrode on the side wall of the second and third electrodes, removing the first electrode layer to form a second gate insulating film on the side wall of the first gate electrode, and forming a fifth gate electrode on the side wall of the fourth electrode, thereby reducing the gate sper imposed capacitance by controlling the thickness of second gate film (28), and preventing the gate induced drain leakage.

Description

MOSFET Structure and Manufacturing Method

(A)-(f) is a manufacturing process diagram of a conventional MOSFET.

(A)-(g) is a manufacturing process diagram of the MOSFET of this invention.

* Explanation of symbols for main parts of the drawings

10: substrate 20, 28: gate oxide film

21, 23: gate pulley 22, 27: TiN (titanium nitride)

24 nitride film 25 oxide film

26: n ^- zone 29: polysilicon sidewalls

30: n ⁺ area 31: BPSG

32: metal

The present invention relates to a structure and a manufacturing method of a MOSFET, and in particular, to make it suitable for improving gate overlap capacitance and gate induced drain leakage (GIDL) and hot carrier characteristics. The present invention relates to a structure and a manufacturing method of a cover on the LDD region-MOSFET and an improvement of device characteristics.

1A to 1F show a manufacturing process diagram of a conventional MOSFET. First, as shown in FIG. 1A, a gate oxide film 11 is grown on a silicon substrate 1, and polysilicon 12 is coated thereon to form a gate thereon. After that, the oxide film 13 is formed and the photosensitive film 14 is formed using a gate mask defining a gate.

Next, as shown in FIG. 1B, the oxide film 13 and the polysilicon 12 are etched to a predetermined thickness of the polysilicon 12 to form a polygate 15 having a thin thickness, and then the photoresist film 14 is formed. Remove

Another thin poly gate 15 for use as a mask, n on the substrate formed as shown in claim 1c ^{even-thickened,} as region 16 shown, and in claim 1d also form an ^oxide-ion injecting n After coating, the sidewall oxide layer 17 is formed by etching with reactive ion etching (RIE).

Next, as shown in FIGS. 1e and f, the thin polygate 15 of the remaining portion except for the portion covered with the oxide film 17 is etched, and then n ⁺ is implanted to form the n ⁺ region 18. The form of (15) is Inverse T MOSFET is manufactured.

However, the conventional MOSFET manufactured as described above is inverse form It is difficult to control the thickness of the polygate 15 when the polysilicon 12 is etched to form the gate 15 of the gate 15, and the gate overlapping capacities are provided since the n ⁻ regions 16 are covered with the polygate 15. There is a problem in that the turn increases and the generation of GIDL cannot be eliminated as the thickness of the gate oxide film 11 becomes thinner.

Accordingly, the present invention has been made to solve the above problems, the structure and manufacturing of the CLR-MOSFET that can reduce the gate overlap capacitance and prevent the generation of GILD by controlling the thickness of the gate oxide film located under the side wall The purpose is to provide a method.

In order to achieve the above object, there are second and second gate poly layers, and TiN (titanium nitride) is formed between and between the two gate poly layers, and a second gate oxide film is disposed under the polysilicon sidewalls. Referring to the present invention in more detail according to the accompanying drawings as follows.

As the completeness of the CLR-MOSFET according to the present invention of FIG. 2G, the structure of the MOSFET of the present invention is characterized in that the gate electrode formation region, the first gate oxide film 20 and the first gate poly layer 21 on the P-type substrate 10 are shown. And a first TiN layer 22 and a second gate poly layer 23 are stacked to form a second TiN 27 on both sides of the first TiN layer 22 and the second gate poly layer 23. Is formed vertically, and a second gate oxide film 28 thicker than the first gate oxide film 20 is grown on both sides of the first gate oxide film 20 and the first gate poly layer 21, and the second gate oxide film 28 is grown. The polysilicon sidewall 29 is formed from the sidewall of the TiN 27 to the upper portion of the second gate oxide layer 28, and the source and the drain of the LDD structure are formed on both side substrates of the gate electrode formation region, and the source and Boron Phosphorus Sillcate Glass (BPSG) 31 having contact holes formed in the drain and the gate is formed to form an image through the contact hole. The metal 32 is formed to be connected to the source, drain and gate.

Looking at the manufacturing process of the CLR-MOSFET of the present invention having the above structure as follows.

(A)-(g) of FIG. 2 are manufacturing process diagrams of the CLR-MOSFET according to the present invention, as shown in FIG. 2A. Grow a one-gate oxide film 20 thereon, a first gate poly layer 21 for a 300-500 kW thick gate, a first TiN 22 on the order of tens-100 kW and a thick second gate poly layer 1500-2000 kW (23) are formed in this order, and the nitride film 24 and the oxide film 25 are sequentially applied thereon.

As shown in FIG. 2B, the oxide film 25, the nitride film 24, the second gate poly layer 23, and the first TiN layer 22 in portions except the gate forming region are formed using a gate mask. After sequentially etching, n- is ion-implanted into the source and drain regions of the substrate to form a LDD (Lightly Doped Drain) region 26 by using them as a mask.

Next, as shown in FIGS. 1C and d, the nitride film 25 is etched and the second TiN 27 is coated on the entire surface, followed by isotropic etching, to form the first TiN layer 22 and the first TiN layer 22. Side walls of the second TiN 27 are formed on the two-gate poly layer 23 and on both sides of the nitride film 24.

Thereafter, as illustrated in FIG. 2E, the exposed first gate poly layer 21 is etched and thermally oxidized to form a second gate oxide layer 28 thicker than the first gate oxide layer 20. The second gate oxide film 20 becomes stepped here because the oxide film is grown not only on the silicon substrate 10 but also on the second gate poly layer 21.

As shown in FIG. 2F, the polysilicon sidewall 29 is formed by etching the nitride film 24 and applying polysilicon on the entire surface, as shown in the drawing, and then anisotropically etching the polysilicon.

Thereafter, n ⁺ is implanted into the source and drain regions to form the n ⁺ region 30.

As shown in FIG. 2G, a BPSG 31 for insulation is formed to selectively etch each source, drain, and gate top to form contact holes, and interconnected using metal 32. The CLR-MOSFET is complete.

The COR-MOSFET of the present invention manufactured as described above has an effect of reducing gate overlap capacitance and preventing generation of GIDL by adjusting the thickness of the second gate coral film 28.

Claims (3)

A first conductive semiconductor substrate, a first gate insulating film formed on a predetermined portion on the substrate 10, first, second, third gate electrodes formed on the first gate insulating film, and the first gate insulating film and the first A second gate insulating film formed on both sidewalls of the first gate electrode, a fourth gate electrode formed on both sidewalls of the second and third gate electrodes, a fifth gate electrode formed on the fourth gate electrode sidewall and the second gate insulating film And a source and a drain region of the LDD structure formed on the substrates on both sides of the first gate insulating film. 2. The gate electrode of claim 1, wherein the first, third, and fifth gate electrodes are formed of polysilicon, the second, fourth gate electrodes are formed of TiN, and the thickness of the first gate insulating film is 70 to 100 GPa. The thickness of the MOSFET is formed from 150 to 200Å, and the thickness of the first gate electrode is formed thinner than the thickness of the third gate electrode. Forming a first gate insulating layer, a first gate electrode layer, a second gate electrode layer, and a third gate electrode layer on the first conductive semiconductor substrate, and etching the second and third gate electrode layers by photolithography using a gate mask; And implanting low-concentration second conductivity type ion implants into the source / drain regions of the substrate using the patterned second and third gate electrodes as a mask, and applying a fourth gate electrode to sidewalls of the second and third gate electrodes. Forming a second gate insulating film on the sidewalls of the first gate electrode by removing the exposed first gate electrode layer and thermally oxidizing the first gate electrode layer; and forming a fifth gate insulating film on the sidewalls of the fourth gate electrode. And a step of forming a gate electrode.