KR0152937B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR0152937B1 KR0152937B1 KR1019950024979A KR19950024979A KR0152937B1 KR 0152937 B1 KR0152937 B1 KR 0152937B1 KR 1019950024979 A KR1019950024979 A KR 1019950024979A KR 19950024979 A KR19950024979 A KR 19950024979A KR 0152937 B1 KR0152937 B1 KR 0152937B1
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- Prior art keywords
- insulating layer
- gate pattern
- gate
- etching
- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 34
- 125000006850 spacer group Chemical group 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 제1도전형 반도체 기판 위의 제1절연막 상에 게이트 패턴을 형성하는 공정과; 게이트 패턴을 마스크로 제1절연막을 식각하되, 상기 게이트 패턴 하부 에지측의 제1절연막이 일부 제거되도록 식각처리하는 공정과; 제1절연막이 제거된 상기 게이트 패턴 하부 에지측 기판에 제1도전형 불순물을 포함한 제3절연막을 형성하는 공정과; 제2도전형 불순물 이온주입을 실시하는 공정 및; 어닐처리하여 제2도전형 불순물 영역 및 제1도전형 불순물 영역을 형성하는 공정을 구비하여 소자 제조를 완료하므로써, 1) 펀치 쓰루 특성을 개선시킬 수 있을 뿐 아니라 핫 캐리어에 의한 소자의 열화를 방지할 수 있으며, 2) p형 접합 영역을 이용한 문턱전압 조절이 가능해 쇼트 채널화됨에 따라 야기되던 임계전압의 롤 오프(roll off) 특성을 개선시킬 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a gate pattern on a first insulating film on a first conductive semiconductor substrate; Etching the first insulating layer using the gate pattern as a mask, and etching the first insulating layer to partially remove the first insulating layer on the lower edge of the gate pattern; Forming a third insulating film including a first conductive impurity on the gate pattern lower edge side substrate from which the first insulating film is removed; Performing a second conductive impurity ion implantation; By annealing to form the second conductive impurity region and the first conductive impurity region, the device fabrication is completed. 1) It is possible to improve the punch-through characteristics and to prevent deterioration of the device by hot carriers. 2) Threshold voltage can be adjusted using a p-type junction region, and thus a highly reliable semiconductor device capable of improving the roll off characteristic of the threshold voltage caused by short channelization can be realized.
Description
제1(a)도 내지 제1(i)도는 본 발명의 제1실시예에 따른 반도체 소자 제조공정을 도시한 공정수순도.1 (a) to 1 (i) are process steps showing a semiconductor device manufacturing process according to the first embodiment of the present invention.
제2(a)도 내지 제2(f)도는 본 발명의 제2실시예에 따른 반도체 소자 제조공정을 도시한 공정수순도.2 (a) to 2 (f) are process flowcharts showing a semiconductor device manufacturing process according to the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
100 : 실리콘 기판 102 : 산화막100 silicon substrate 102 oxide film
104 : 폴리실리콘 106 : PSG막104: polysilicon 106: PSG film
108 : 감광막 패턴 110 : BSG막108 photosensitive film pattern 110 BSG film
112 : n+접합 영역 114 : p-접합 영역112: n + junction region 114: p - junction region
116 : n-접합 영역 118 : 측벽 스페이서116: n - junction region 118 sidewall spacer
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 게이트 에지(edge)의 전계를 감소시켜 소자의 신뢰성을 향상시킨 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the reliability of the device is improved by reducing an electric field at a gate edge.
종래 일반적으로 사용되어 오던 반도체 소자는 실리콘 기판 위에 게이트 산화막과 폴리실리콘을 순차적으로 증착한 뒤, 감광막 패턴을 마스크로 한 사진식각공정으로 상기 산화막과 폴리실리콘을 식각처리하여 게이트를 형성하고, 저농도 n형 불순물을 이온주입하여 n-접합 영역을 형성한 후, 상기 게이트 측면에 측벽 스페이서(sidewall spacer)를 형성하고, 이어 상기 측벽 스페이서 및 게이트를 마스크로 고농도 n형 불순물을 주입하여 n+접합 영역을 형성하는 순으로 소자를 제조하여 왔다.A semiconductor device, which has been generally used in the related art, is formed by sequentially depositing a gate oxide film and polysilicon on a silicon substrate, and then etching the oxide film and polysilicon by a photolithography process using a photoresist pattern as a mask to form a gate, and low concentration n. After implanting an n - type impurity to form an n− junction region, a sidewall spacer is formed on the side of the gate, and then a high concentration of n-type impurity is implanted using the sidewall spacer and the gate as a mask to form an n + junction region. Devices have been manufactured in the order of formation.
그러나 상기 공정을 이용하여 소자를 제조할 경우, 게이트 산화막에 트랩(trap)되는 핫 캐리어(hot carrier)로 인해 게이트 에지에서의 전계(electric field)가 증가하게 되어 소자의 열화가 발생될 뿐 아니라 펀치 쓰루(punch through) 특성이 저하되는 등의 문제점이 야기되어 소자의 신뢰성이 저하되는 단점을 가지게 된다.However, when the device is manufactured using the above process, the hot field trapped in the gate oxide film causes an electric field at the gate edge to increase, resulting in deterioration of the device as well as punching. Problems such as deterioration of the through through property are caused, resulting in a decrease in reliability of the device.
따라서, 스캐일링 방법(scaling method)에 의해 인가전압이나 게이트 산화막의 두께 또는 농도 등을 조정하여 게이트 에지쪽의 전계를 떨어뜨려 주어야 하는데, 이 또한 기본적으로 소자의 전계는 더 이상 증가되지 않는 상태에서 스캐일링이 이루어져야 하므로 실질적으로 상기 단점을 개선하기에는 무리가 따르게 된다.Therefore, the electric field at the gate edge must be dropped by adjusting the applied voltage, the thickness or the concentration of the gate oxide film by the scaling method, and basically the electric field of the device is no longer increased. Since scaling has to be done, it is difficult to substantially improve the disadvantage.
이와 같은 현상은 소자가 고집적화됨에 따라 그 정도가 심화되어 쇼트 채널을 갖는 반도체 소자에 있어서의 신뢰성은 더욱 감소될 수 밖에 없다.This phenomenon is intensified as the device is highly integrated, and the reliability of the semiconductor device having a short channel is inevitably reduced.
이에 본 발명은 상기와 같은 단점을 개선하기 위하여 이루어진 것으로, n형 접합 영역을 감싸도록 채널 영역에 p형 접합 영역을 형성하므로써 핫캐리어에 의한 소자의 열화를 방지하여 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to improve the above disadvantages, and by forming a p-type junction region in the channel region to surround the n-type junction region to prevent deterioration of the device by the hot carrier to improve the reliability of the device It is an object to provide a method for manufacturing a semiconductor device.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자 제조방법은 제1도전형 반도체 기판 위의 제1절연막 상에 게이트 패턴을 형성하는 공정과; 게이트 패턴을 마스크로 제1절연막을 식각하되, 상기 게이트 패턴 하부 에지측의 제1절연막이 일부 제거되도록 식각처리하는 공정과; 제1절연막이 제거된 상기 게이트 패턴 하부 에지측 기판에 제1도전형 불순물을 포함한 제3절연막을 형성하는 공정과; 제2도전형 불순물 이온주입을 실시하는 공정 및; 어닐처리하여 제2도전형 불순물 영역 및 제1도전형 불순물 영역을 형성하는 공정을 구비하여 형성되는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate pattern on the first insulating film on the first conductive semiconductor substrate; Etching the first insulating layer using the gate pattern as a mask, and etching the first insulating layer to partially remove the first insulating layer on the lower edge of the gate pattern; Forming a third insulating film including a first conductive impurity on the gate pattern lower edge side substrate from which the first insulating film is removed; Performing a second conductive impurity ion implantation; And annealing to form a second conductive impurity region and a first conductive impurity region.
상기 제조공정 결과, 반도체 소자의 신뢰성을 향상시킬 수 있게 된다.As a result of the manufacturing process, the reliability of the semiconductor device can be improved.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제1(a)도 내지 제1(i)도는 본 발명의 제1실시예에 따른 반도체 소자 제조공정을 도시한 공정수순도를 나타낸 것으로, 상기 실시예는 소자의 신뢰성을 향상시키기 위하여 트랜지스터 제조시 게이트 측면의 측벽 스페이서 공정을 단순화하고, 게이트 에지에서의 전계를 감소시키는데 주안점을 두고 있다.1 (a) to 1 (i) show a process flow diagram showing a semiconductor device manufacturing process according to the first embodiment of the present invention, which is used to fabricate a transistor in order to improve the reliability of the device. The focus is on simplifying the sidewall spacer process on the gate side and reducing the field at the gate edge.
이를 제1도에 도시된 공정수순도를 참조하여 구체적으로 살펴보면 다음과 같다.This will be described in detail with reference to the process flowchart shown in FIG. 1.
먼저, 제1(a)도에 도시된 바와 같이 반도체 기판인 실리콘 기판(100) 위에 제1절연막인 게이트 산화막(102)과 게이트 폴리실리콘(104)을 증착한 후, 상기 게이트 폴리실리콘(104) 상에 제2절연막인 PSG 막(106)을 추가로 증착하고, 제1(b)도에 도시된 바와 같이 게이트가 정의(define)될 영역의 PSG막(106) 상에 사진식각공정을 이용하여 감광막 패턴(108)을 형성한다.First, as illustrated in FIG. 1A, a gate oxide layer 102 and a gate polysilicon 104, which are first insulating layers, are deposited on a silicon substrate 100, which is a semiconductor substrate, and then the gate polysilicon 104 is deposited. A second insulating film PSG film 106 is further deposited on the substrate, and a photolithography process is performed on the PSG film 106 in the region where the gate is to be defined as shown in FIG. 1 (b). The photosensitive film pattern 108 is formed.
그후, 게이트 폴리실리콘(104)을 테이퍼(taper)지도록 식각하기 위하여 제1(c)도에 도시된 바와 같이 상기 PSG막(106)을 감광막 패턴(108)의 에지측 밑 부분까지 제거되도록 식각처리하고, 이어 상기 감광막 패턴(108)을 마스크로 건식 식각(dry etching)을 실시하여 제1(d)도에 도시된 바와 같이 테이퍼진 형상의 게이트 폴리실리콘(104)을 형성한다.Thereafter, in order to etch the gate polysilicon 104 to taper, an etching process is performed such that the PSG film 106 is removed to the lower edge side of the photosensitive film pattern 108 as shown in FIG. 1 (c). Subsequently, dry etching is performed using the photoresist pattern 108 as a mask to form a gate polysilicon 104 having a tapered shape as shown in FIG.
이어서, 제1(e)도에 도시된 바와 같이 상기 감광막 패턴(108) 및 PSG막(106)을 제거하고, 기판 상의 게이트 산화막(102)을 게이트 폴리실리콘(104)의 테이퍼진 부분까지 식각하여 제1(f)도에 도시된 형태의 패턴을 형성한다.Subsequently, as shown in FIG. 1E, the photoresist pattern 108 and the PSG layer 106 are removed, and the gate oxide layer 102 on the substrate is etched to the tapered portion of the gate polysilicon 104. A pattern of the form shown in FIG. 1 (f) is formed.
그 다음, 제1(g)도에 도시된 바와 같이 상기 패턴 전면에 제3절연막인 BSG막(110)을 증착한다. 이때, 게이트 폴리실리콘의 테이퍼진 부분의 하측 기판 상에도 BSG막이 채워지도록 증착 공정이 이루어져야 한다.Next, as shown in FIG. 1 (g), a BSG film 110 as a third insulating film is deposited on the entire surface of the pattern. At this time, the deposition process should be performed so that the BSG film is also filled on the lower substrate of the tapered portion of the gate polysilicon.
이후, 제1(h)도에 도시된 바와 같이 에치-백 공정으로 게이트 폴리실리콘(104)의 경사(taper)진 부분 하측 기판 상의 BSG막을 제외한 모든 영역의 BSG막(110)을 제거하고, 제1(i)도에 도시된 바와 같이 고농도의 n형 불순물을 이온주입하여 n+접합(Junction) 영역(112)을 형성한 후, 어닐(anneal) 공정을 실시하여 채널 형성부에 p-접합 영역(114)를 형성하므로써 본 공정을 완료한다.Thereafter, as shown in FIG. 1 (h), the BSG film 110 of all regions except for the BSG film on the lower portion of the tapered portion of the gate polysilicon 104 is removed by an etch-back process. As shown in FIG. 1 (i), a high concentration of n-type impurities are ion-implanted to form an n + junction region 112, and then an annealing process is performed to form a p − junction region. This step is completed by forming 114.
이때, 상기 p-접합 영역(114)은 어닐 공정시 BSG막에 의해 n+와 반대되는 타입으로 실리콘 기판 표면에 형성된 것으로 n+접합 영역(112)을 감싸는 구조를 가지며, 상기 게이트 폴리실리콘의 경사진 부분과 그 하부의 BSG막은 게이트 측면에 형성된 측벽 스페이서 역할을 하게 된다. 이 경우, 게이트와 측벽 스페이서가 동시에 형성된 것이므로 그 만큼 공정을 단순화할 수 있게 된다.At this time, the p − junction region 114 is formed on the surface of the silicon substrate in a type opposite to n + by the BSG film during the annealing process, and has a structure surrounding the n + junction region 112. The photo portion and the lower BSG film serve as sidewall spacers formed on the side of the gate. In this case, since the gate and sidewall spacers are formed at the same time, the process can be simplified.
제1(i)도에서 알 수 있듯이 본 공정에 의해 제조된 반도체 소자는 기본적으로 게이트 에지부의 전계가 가장 높은 부분인 것을 감안해 볼때, 트랩되는 전자들이 측벽 스페이서 밑 에지 쪽 산화막인 BSG막(110)에 발생하게 되더라도 그 하부의 실리콘 기판 표면에 얇은 p-접합 영역(114)이 형성되어 있어 트랩되는 전자들이 상기 접합 영역의 홀과 결합되므로 상기 트랩 전자들을 상쇠시킬 수 있게 되어 결국, 핫 캐리어에 의한 소자의 열화를 방지할 수 있게 되므로 전하 증가에 따른 소자의 신뢰성 저하를 감소시킬 수 있을 뿐 아니라 펀치 쓰루(punch through) 특성을 개선할 수 있게 된다.As can be seen from FIG. 1 (i), the BSG film 110, in which the electrons trapped are oxide films under the sidewall spacers, in view of the fact that the semiconductor device fabricated by this process is basically the highest electric field of the gate edge portion. Even though the thin film is formed on the surface of the silicon substrate underneath, a thin p − junction region 114 is formed so that the trapped electrons are combined with the holes in the junction region, thereby canceling the trap electrons. Since the deterioration of the device can be prevented, not only the decrease in reliability of the device due to the increase in charge can be reduced, but also the punch through characteristics can be improved.
또한, 채널보다 고농도의 p-접합 영역(114)이 반도체 소자의 채널에 형성되므로 문턱 전압(threshold volatage)을 제어(control)할 수 있게 되어 특히, 쇼트 채널화됨에 따라 야기되는 임계전압의 롤 오프(roll off) 특성을 개선시킬 수 있게 된다.In addition, since the p − junction region 114 having a higher concentration than that of the channel is formed in the channel of the semiconductor device, it is possible to control the threshold voltage, in particular, the roll-off of the threshold voltage caused by short channelization. (roll off) characteristics can be improved.
한편, 제1실시예의 공정을 다소 변형한 제2실시예로서 제2(a)도 내지 제2(f)도에 도시된 공정수순도를 살펴보면 다음과 같다.On the other hand, as a second embodiment slightly modified the process of the first embodiment will be described in the process flow chart shown in Figs.
상기 실시예 또한 최종적으로는 n-접합 영역을 p-접합 영역이 감싸는 구조를 가지게 되므로 제1실시예와 같이 펀치 쓰루 특성 개선과, 핫 캐리어에 의한 소자의 열화 방지 및, 문턱 전압 조절 가능등의 잇점을 갖게 되며, 이를 제2도에 도시된 도면을 참조하여 구체적으로 설명한다.The embodiment also finally has a structure in which the p − junction region surrounds the n − junction region, thereby improving punch through characteristics, preventing deterioration of the device due to hot carriers, and adjusting the threshold voltage as in the first embodiment. Advantageous advantages will be described in detail with reference to the drawings shown in FIG. 2.
먼저, 제2(a)도에 도시된 바와 같이 반도체 기판인 실리콘 기판(100) 위에 제1절연막인 게이트 사화막(102) 및 게이트 폴리실리콘(104)을 증착하고, 게이트가 정의될 영역에 감광막 패턴을 형성한 뒤 이를 마스크로 상기 게이트 폴리실리콘(104) 및 게이트 산화막(102)을 식각하여 게이트 전극을 형성한다.First, as shown in FIG. 2 (a), a gate insulating film 102 and a gate polysilicon 104, which are first insulating films, are deposited on a silicon substrate 100, which is a semiconductor substrate, and a photoresist film is formed in a region where a gate is to be defined. After the pattern is formed, the gate polysilicon 104 and the gate oxide layer 102 are etched using a mask to form a gate electrode.
이후, 제2(b)도에 도시된 바와 같이 감광막 패턴을 제거한 뒤, 상기 게이트 폴리실리콘 에지측 밑 부분의 게이트 산화막(102)이 일부 제거되도록 식각처리하고, 제2(c)도에 도시된 바와 같이 게이트 폴리실리콘(104) 및 게이트 산화막(102)을 포함하도록 실리콘 기판 전 표면에 제3절연막인 BSG막(110)을 증착한다.Thereafter, as shown in FIG. 2 (b), after the photoresist pattern is removed, an etching process is performed to remove part of the gate oxide layer 102 at the bottom side of the gate polysilicon edge side, and as shown in FIG. As described above, the BSG film 110, which is the third insulating film, is deposited on the entire surface of the silicon substrate to include the gate polysilicon 104 and the gate oxide film 102.
그 다음, 제2(d)도에 도시된 바와 같이 상기 BSG막(110)을 에치-백하여 상기 게이트 폴리실리콘(104) 하부의 BSG막(110)만을 남기고, 저농도 n형 불순물을 이온주입하여 LDD(lightly doped drain)영역인 n-접합 영역(116)을 형성한다.Then, as shown in FIG. 2 (d), the BSG film 110 is etched back, leaving only the BSG film 110 under the gate polysilicon 104 and ion implanted with a low concentration n-type impurity. An n − junction region 116 is formed, which is a lightly doped drain (LDD) region.
이어서, 제2(e)도에 도시된 바와 같이 상기 게이트 전극 측면에 측벽 스페이서(118)를 형성하고, 다시 고농도의 n형 불순물을 이온주입하여 n+접합 영역(112)을 형성한 후, 어닐 공정을 실시하여 제2(f)도에 도시된 바와 같이 p-접합 영역(114)을 형성하므로써 본 공정을 완료한다.Subsequently, as shown in FIG. 2 (e), the sidewall spacers 118 are formed on the side of the gate electrode, and a high concentration of n-type impurities are ion implanted to form n + junction regions 112, followed by annealing. The process is completed by forming the p − junction region 114 as shown in FIG. 2 (f).
상술한 바와 같이 본 발명에 의하면, 1) 펀치 쓰루 특성을 개선시킬 수 있을 뿐 아니라 핫 캐리어에 의한 소자의 열화를 방지할 수 있고, 2) p형 접합 영역을 이용한 문턱전압 조절로 쇼트 채널화됨에 따라 야기되던 문턱전압의 롤 오프 특성을 개선시킬 수 있는 고신뢰성의 반도체 소자를 구현할 수 있게 된다.As described above, according to the present invention, 1) the punch-through characteristic can be improved, and the deterioration of the device due to the hot carrier can be prevented, and 2) the short channelization is made by adjusting the threshold voltage using the p-type junction region. It is possible to implement a highly reliable semiconductor device that can improve the roll-off characteristics of the threshold voltage caused by this.
Claims (5)
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