KR100869842B1 - Method for forming the DRAM memory cell - Google Patents

Method for forming the DRAM memory cell Download PDF

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KR100869842B1
KR100869842B1 KR1020020041804A KR20020041804A KR100869842B1 KR 100869842 B1 KR100869842 B1 KR 100869842B1 KR 1020020041804 A KR1020020041804 A KR 1020020041804A KR 20020041804 A KR20020041804 A KR 20020041804A KR 100869842 B1 KR100869842 B1 KR 100869842B1
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forming
region
source
film
gate electrode
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KR1020020041804A
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KR20040007146A (en
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김호웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

본 발명은 디램 메모리 셀의 제조방법에 관한 것으로, 특히, 트랜지스터의 소오스/드레인 제조방법에 있어서, 소자분리영역의 필드산화막 일부를 제거한 후, 에피택셜실리콘을 성장시켜 성장된 에피택셜실리콘 영역에 임플란트 공정을 진행함으로써, 소자분리영역 내에 소오스/드레인 접합영역을 형성하여 소오스/드레인 접합영역의 접합 누설전류에 의한 리프레쉬 특성을 개선시키고, 디램 셀 면적을 줄여 반도체소자의 고집적화 시킬 수 있는 기술이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a DRAM memory cell, and more particularly, in a method of manufacturing a source / drain of a transistor, after removing a part of a field oxide film of an isolation region, epitaxial silicon is grown to implant an epitaxial silicon region. By proceeding the process, a source / drain junction region is formed in the device isolation region to improve the refresh characteristics caused by the junction leakage current of the source / drain junction region, and reduce the DRAM cell area to increase the integration of semiconductor devices.

게이트, 소자분리영역, 트랜지스터Gate, isolation region, transistor

Description

디램 메모리 셀의 제조방법{Method for forming the DRAM memory cell} Method for forming the DRAM memory cell             

도 1은 종래 기술에 따른 디램 메모리 셀을 설명하기 위해 디램 메모리 셀 구조를 나타낸 단면도이다.1 is a cross-sectional view illustrating a DRAM memory cell structure in order to describe a DRAM memory cell according to the related art.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 디램 메모리 셀의 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.
2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention.

-- 도면의 주요부분에 대한 부호의 설명 -- -Explanation of symbols for the main parts of the drawing-

100 : 실리콘 기판 110 : 필드산화막100 silicon substrate 110 field oxide film

120 : 제1감광막 패턴 130 : 홈120: first photosensitive film pattern 130: groove

140 : 게이트산화막 150 : 게이트전극 패턴140: gate oxide film 150: gate electrode pattern

160 : 라이트산화막 170 : 소오스/드레인 접합영역160: light oxide film 170: source / drain junction region

180 : 스페이서 190 : LDD
180: spacer 190: LDD

본 발명은 디램 메모리 셀의 제조방법에 관한 것으로, 보다 상세하게는 트랜지스터의 소오스/드레인 제조방법에 있어서, 소자분리영역 내에 소오스/드레인 접합영역을 형성시켜 소오스/드레인 접합영역의 접합 누설전류에 의한 리프레쉬 특성을 개선시키고, 디램 셀 면적을 줄일 수 있도록 하는 디램 메모리 셀의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a DRAM memory cell, and more particularly, in a method of manufacturing a source / drain of a transistor, a source / drain junction region is formed in an isolation region by a junction leakage current of the source / drain junction region. The present invention relates to a method of manufacturing a DRAM memory cell that improves refresh characteristics and reduces DRAM cell area.

일반적으로 DRAM(Dynamic Random Access Memory, 이하 DRAM 이라 칭함)은 하나의 트랜지스터 및 하나의 커패시터로 이루어진 메모리 셀(Memory Cell)을 갖는다.In general, a DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) has a memory cell composed of one transistor and one capacitor.

최근 반도체 집적회로 공정 기술이 발달함에 따라 반도체 기판 상에 제조되는 소자의 최소 선폭 길이는 더욱 미세화되고, 단위 면적당 집적도는 증가하고 있다.With the recent development of semiconductor integrated circuit processing technology, the minimum line width length of devices fabricated on a semiconductor substrate is further miniaturized, and the degree of integration per unit area is increasing.

도 1은 종래 반도체소자의 트랜지스터 제조방법에 의해 제조된 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view showing a transistor manufactured by a transistor manufacturing method of a conventional semiconductor device.

도 1에 도시된 바와 같이, 실리콘기판(10)에 소자간 격리를 위한 필드산화막(20)을 형성하고 게이트산화막과 제 1폴리실리콘과 텅스텐 실리사이드와 제 2폴리실리콘 및 제 1절연막을 차례로 증착한 후 적층구조의 게이트전극(30)을 형성하고, LDD 이온주입을 통해 소오스/드레인 접합영역(40)을 형성한 후 게이트전극(30)의 측벽에 스페이서(50)을 형성하여 트랜지스터를 완성하게 된다.As shown in FIG. 1, a field oxide film 20 is formed on the silicon substrate 10 for isolation between devices, and a gate oxide film, first polysilicon, tungsten silicide, second polysilicon, and a first insulating film are sequentially deposited. After that, a gate electrode 30 having a stacked structure is formed, a source / drain junction region 40 is formed through LDD ion implantation, and spacers 50 are formed on sidewalls of the gate electrode 30 to complete the transistor. .

그러나, 상기와 같이 종래기술에 따른 반도체소자의 트랜지스터 제조방법은, 소오스/드레인 접합영역이 실리콘기판과 정션을 이루고 있기 때문에 활성 영역 내 에 소오스/드레인 접합영역이 형성함으로써 셀 면적을 차지하여 고집적화가 어려운 문제점이 있었다.However, in the transistor manufacturing method of the semiconductor device according to the prior art as described above, since the source / drain junction region forms a junction with the silicon substrate, the source / drain junction region is formed in the active region to occupy the cell area and thus high integration is achieved. There was a difficult problem.

또한, 소오스/드레인 접합영역의 누설전류 특성을 저하시켜 반도체소자의 리프레쉬(refresh) 특성 및 수율을 감소시키는 문제점이 있었다.
In addition, there is a problem in that the leakage current characteristics of the source / drain junction region are reduced to reduce the refresh characteristics and the yield of the semiconductor device.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 트랜지스터의 소오스/드레인 제조방법에 있어서, 소자분리영역의 필드산화막 일부를 제거한 후, 에피택셜실리콘을 성장시켜 성장된 에피택셜실리콘 영역에 임플란트 공정을 진행함으로써, 소자분리영역 내에 소오스/드레인 접합영역을 형성하여 소오스/드레인 접합영역의 접합 누설전류에 의한 리프레쉬 특성을 개선시키고, 디램 셀 면적을 줄여 반도체소자의 고집적화 시키도록 하는 반도체소자의 트랜지스터 제조방법을 제공하는 것이다.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to grow epitaxial silicon by removing epitaxial silicon after removing a part of a field oxide layer of a device isolation region in a method of manufacturing a source / drain of a transistor. The implant process is performed in the tactile silicon region to form a source / drain junction region in the device isolation region to improve refresh characteristics due to the junction leakage current of the source / drain junction region, and to reduce the DRAM cell area to increase the integration of semiconductor devices. It is to provide a transistor manufacturing method of a semiconductor device.

상기 목적을 달성하기 위하여, 본 발명은 필드산화막과 웰이 형성된 실리콘기판 상에 활성영역과 인접한 필드산화막의 일부분이 개방되도록 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 개방된 필드산화막의 상부를 소정 제거하고 애피택셜 실리콘막을 성장시킨 후 활성영역 상부에 게이트산화막을 형성하는 단계와, 상기 결과물 상에 도프드 폴리막과 텅스텐실리사이드와 질화막 및 반사 방지막을 순차적으로 적층한 후 노광 및 식각 공정을 진행하여 게이트전극 패턴을 형성하는 단계와, 상기 게이트전극 패턴을 마스크로 불순물 임플란트(Implant) 공정을 진행하여 소오스/드레인을 형성하는 단계와, 상기 게이트전극 패턴 측벽에 질화물 또는 산화물을 이용하여 측벽스페이스를 형성한 후 LDD를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 디램 메모리 셀의 제조방법을 제공한다. In order to achieve the above object, the present invention is to form a photoresist pattern so that a portion of the field oxide film adjacent to the active region is opened on the silicon substrate on which the field oxide film and wells are formed, and the field oxide film is opened using the photoresist pattern as a mask. Forming a gate oxide layer on the active region after removing the upper portion and growing an epitaxial silicon layer, and sequentially depositing a doped poly layer, a tungsten silicide, a nitride layer, and an anti-reflection layer on the resultant, followed by an exposure and etching process. Forming a gate electrode pattern; forming a source / drain by using an impurity implant process using the gate electrode pattern as a mask; and using a nitride or an oxide on the sidewall of the gate electrode pattern. Forming an LDD after forming the space To provide a method of manufacturing a dynamic random access memory cell according to claim.

본 발명은 필드산화막이 형성된 소자분리영역에 소오스/드레인 접합영역을 형성하여 디램 셀 면적을 줄여 반도체소자의 고집적화 시키는 것을 특징으로 한다.
The present invention is characterized in that the source / drain junction region is formed in the device isolation region in which the field oxide film is formed, thereby reducing the DRAM cell area to increase integration of the semiconductor device.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명의 일실시예에 따른 반도체소자의 트랜지스터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 실리콘기판(100) 상에 셀로우 트랜치 아이솔레이션(STI) 공정으로 필드산화막(110)을 형성하여 소자를 격리하는 소자분리영역(A)과 활성영역(B)으로 구분한다.As shown in FIG. 2A, a field oxide layer 110 is formed on a silicon substrate 100 by a shallow trench isolation (STI) process to divide the device isolation region A and the active region B to isolate the device. do.

그리고, 상기 결과물 전체에 감광막(미도시함)을 도포하고 노광 및 현상공정을 진행하여 활성영역(B)과 인접한 소자분리영역(A)의 필드산화막(110) 일부분이 개방되도록 제1감광막 패턴(120)을 형성한다.In addition, a photoresist (not shown) is applied to the entire resultant, and a process of exposing and developing the first photoresist layer pattern is performed to open a portion of the field oxide layer 110 in the device isolation region A adjacent to the active region B. 120).

도 2b에 도시된 바와 같이, 상기 제1감광막 패턴(미도시함)을 마스크로 필드산화막(110)을 소정부분 식각하여 홈(130)을 형성한다. As illustrated in FIG. 2B, the groove 130 is formed by etching a predetermined portion of the field oxide layer 110 using the first photoresist pattern (not shown) as a mask.                     

이때, 상기 홈(130)은 후속 공정에 의해 소오스/드레인 정션이 형성될 공간으로 식각 시, 소오스/드레인 접합영역이 형성될 정도의 깊이로 식각한다.In this case, the groove 130 is etched to a depth enough to form a source / drain junction region when the groove 130 is etched into a space where a source / drain junction is to be formed by a subsequent process.

이어서, 도 2c에 도시된 바와 같이, 상기 홈(미도시함)에 애피택셜 실리콘을 성장시켜 홈을 매립함으로써, 소자분리영역(A)에서 활성영역(B)으로 전환한 후, 필드산화막(110)으로 이루어진 소자분리영역을 제외한 활성영역(B) 상부에 산화막(미도시함)을 약 70 ~ 100Å의 두께로 얇게 성장시킴으로써 메모리 셀의 게이트산화막(140)을 형성한다.Subsequently, as shown in FIG. 2C, epitaxial silicon is grown in the groove (not shown) to fill the groove, thereby switching from the device isolation region A to the active region B, and then filling the field oxide film 110. A gate oxide layer 140 of the memory cell is formed by thinly growing an oxide film (not shown) to a thickness of about 70 to about 100 microseconds on the active region B except for the device isolation region formed of ().

그리고, 도 2d에 도시된 바와 같이, 결과물 상에 도프드 폴리실리콘막과 텅스텐실리사이드, 질화막 및 반사방지막을 순차적으로 적층한 후, 노광 및 식각 공정을 진행하여 게이트산화막, 도프드 폴리실리콘막, 텅스텐실리사이드 및 질화막으로 구성된 게이트전극 패턴(150)을 형성한다.As shown in FIG. 2D, a doped polysilicon film, a tungsten silicide, a nitride film, and an antireflection film are sequentially stacked on the resultant, followed by an exposure and etching process to perform a gate oxide film, a doped polysilicon film, and tungsten. A gate electrode pattern 150 formed of a silicide and a nitride film is formed.

이때, 상기 질화막(미도시함) 상부의 반사방지막(미도시함)은 게이트전극 패턴(150) 형성을 위한 식각 시, 패턴의 손상을 방지하기 위해 증착된 것으로 게이트전극 패턴(150)을 형성한 후, 제거한다.In this case, the anti-reflection film (not shown) on the nitride film (not shown) is deposited to prevent damage of the pattern when the gate electrode pattern 150 is formed, and the gate electrode pattern 150 is formed. After that, remove it.

이어서, 도 2e에 도시된 바와 같이, 상기 결과물 상에 라이트 옥시데이션 공정을 진행하여 소자분리영역(A)을 제외한 나머지 활성영역(B)과 게이트전극 패턴(150) 외곽에 라이트 산화막(160)을 형성한다.Next, as shown in FIG. 2E, a light oxidization process is performed on the resultant to form a light oxide layer 160 around the active region B and the gate electrode pattern 150 except for the device isolation region A. FIG. Form.

그 후, 상기 게이트전극 패턴(150)을 이온주입 마스크로 사용하여 불순물을 이온주입하여 실리콘기판(100) 내에 소오스/드레인 접합영역(170)을 형성한다.Thereafter, the source / drain junction region 170 is formed in the silicon substrate 100 by implanting impurities using the gate electrode pattern 150 as an ion implantation mask.

그리고, 도 2f에 도시된 바와 같이, 상기 게이트전극 패턴(150) 측벽에 질화 물 또는 산화물을 이용하여 스페이스(180)를 형성한 후 LDD(Lightly Doped Drain)(190)를 형성한다.
As shown in FIG. 2F, a space 180 is formed on the sidewall of the gate electrode pattern 150 using nitride or oxide to form a lightly doped drain (LDD) 190.

따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 트랜지스터 제조방법을 이용하게 되면, 트랜지스터의 소오스/드레인 제조방법에 있어서, 소자분리영역의 필드산화막 일부를 제거한 후, 에피택셜실리콘을 성장시켜 성장된 에피택셜실리콘 영역에 임플란트 공정을 진행함으로써, 소자분리영역 내에 소오스/드레인 접합영역을 형성하여 디램 셀 면적을 줄여 반도체소자의 고집적화 시킬 수 있는 효과가 있다. Therefore, as described above, when the transistor fabrication method of the semiconductor device according to the present invention is used, the epitaxial silicon is grown by removing part of the field oxide film in the isolation region in the transistor source / drain fabrication method. By performing an implant process on the epitaxial silicon region thus formed, a source / drain junction region is formed in the device isolation region to reduce the DRAM cell area, thereby increasing the integration of semiconductor devices.

그 결과, 핫캐리어효과 및 소오스/드레인 접합영역의 접합 누설전류 특성이 저하되는 것을 방지하고, 반도체소자의 리프레쉬(refresh) 특성 및 수율을 향상시키는 효과가 있다.As a result, the hot carrier effect and the junction leakage current characteristics of the source / drain junction region are prevented from deteriorating and the refresh characteristics and the yield of the semiconductor device are improved.

Claims (2)

필드산화막에 의해 활성영역 및 소자분리영역이 정의된 실리콘 기판상에 상기 활성영역과 인접한 필드산화막의 일부 영역을 노출시키는 감광막 패턴을 형성하는 단계;Forming a photoresist pattern exposing a portion of the field oxide film adjacent to the active region on a silicon substrate having an active region and an isolation region defined by a field oxide film; 상기 감광막 패턴을 식각마스크로 한 식각 공정으로 상기 필드산화막 내에 소정 깊이의 홈을 형성하는 단계;Forming a groove having a predetermined depth in the field oxide film by an etching process using the photoresist pattern as an etching mask; 상기 홈을 에피택셜실리콘막으로 매립하여 상기 소자분리영역 방향으로 연장된 활성영역을 형성하는 단계;Filling the groove with an epitaxial silicon film to form an active region extending toward the device isolation region; 상기 연장된 활성영역 상에 게이트산화막을 형성하는 단계;Forming a gate oxide layer on the extended active region; 상기 결과물 상에 도프드 폴리막과 텅스텐실리사이드 및 질화막을 순차적으로 적층한 후 노광 및 식각 공정을 진행하여 게이트전극 패턴을 형성하는 단계;Sequentially depositing a doped poly film, a tungsten silicide and a nitride film on the resultant to form a gate electrode pattern by performing an exposure and etching process; 상기 게이트전극 패턴을 이온주입배리어막으로 1차 이온주입공정을 진행하여 소오스/드레인 접합영역을 형성하는 단계; Forming a source / drain junction region by performing a first ion implantation process on the gate electrode pattern using an ion implantation barrier film; 상기 게이트전극 패턴 측벽에 측벽스페이스를 형성하는 단계; 및Forming sidewall spaces on sidewalls of the gate electrode patterns; And 상기 측벽스페이스를 이온주입배리어막으로 2차 이온주입공정을 진행하여 한 후 LDD 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 디램 메모리 셀의 제조방법.And forming an LDD region after performing a secondary ion implantation process using the sidewall space as an ion implantation barrier film. 제1항에 있어서,The method of claim 1, 상기 홈은 상기 소오스/드레인 접합영역과 대등한 깊이로 형성하는 디램 메모리 셀의 제조방법.And forming a groove having a depth equal to that of the source / drain junction region.
KR1020020041804A 2002-07-16 2002-07-16 Method for forming the DRAM memory cell KR100869842B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055063A (en) * 1997-12-27 1999-07-15 윤종용 Manufacturing method of MOS transistor which forms source / drain on field oxide film
KR20040046853A (en) * 2002-11-28 2004-06-05 주식회사 하이닉스반도체 Method for forming the DRAM memory cell
KR20040046164A (en) * 2002-11-26 2004-06-05 주식회사 하이닉스반도체 Method for forming gate of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990055063A (en) * 1997-12-27 1999-07-15 윤종용 Manufacturing method of MOS transistor which forms source / drain on field oxide film
KR20040046164A (en) * 2002-11-26 2004-06-05 주식회사 하이닉스반도체 Method for forming gate of semiconductor device
KR20040046853A (en) * 2002-11-28 2004-06-05 주식회사 하이닉스반도체 Method for forming the DRAM memory cell

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