KR100636669B1 - Method for forming the DRAM memory cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a DRAM memory cell, which can secure data retention time by preventing electric field concentration in the gate edge region of the DRAM memory cell according to high integration.

This method includes forming a channel region in an active region of a semiconductor substrate having an active region and an isolation region, forming a gate pattern on the substrate on which the channel region is formed, and depositing an insulating film on the entire surface of the substrate on which the gate pattern is formed; Forming an insulating spacer on the sidewall of the gate pattern by etching the insulating layer, removing the portion of the channel region formed in the substrate by excessive etching, and performing a silicon selective epitaxial growth process on the substrate from which the channel region is removed. Forming a silicon growth film to a surface height, and annealing the substrate on which the silicon growth film is formed.

Threshold Voltage, Channel Area, Storage Node Junction Area, Field Concentration, Gate

Description

Method for forming the DRAM memory cell             

FIG. 1A is a cross-sectional view schematically illustrating a cell transistor structure manufactured by a conventional method of manufacturing a DRAM memory cell, and B is a graph showing a concentration distribution of a channel region of a cell transistor.

A and B of FIGS. 2A to 2E are graphs showing sequential cross-sectional views and concentration distributions of channel regions of a cell transistor, in order to explain a method of manufacturing a DRAM memory cell according to a first embodiment of the present invention. to be.

3A to 3D are graphs showing the sequential cross-sectional views and concentration distributions of the channel regions of the cell transistors in order to explain a method of manufacturing a DRAM memory cell according to a second exemplary embodiment of the present invention. to be.

   -Explanation of symbols for the main parts of the drawings-

100 semiconductor substrate 110 device isolation film

120: channel region 130: gate pattern

145: insulating spacer 150: silicon growth film

160: interlayer insulating film 180: contact hole for the landing plug                 

A: storage node junction area

B: gate area

The present invention relates to a method for manufacturing a DRAM memory cell, and more particularly, to a method for manufacturing a DRAM memory cell capable of securing a data retention time in a DRAM memory cell according to high integration.

Generally, a DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) has a memory cell composed of one transistor and one capacitor.

As the design rule of the device is reduced due to the high integration of DRAM memory cells, the size of the cell transistor is reduced and the channel length of the transistor is also shortened. As the channel length becomes shorter, the short-channel effect of the transistor is deepened to reduce the threshold voltage.

Accordingly, in order to prevent the threshold voltage from decreasing due to the short channel effect of the transistor, the threshold voltage of a desired magnitude is obtained by increasing the doping concentration of the channel.

FIG. 1A is a cross-sectional view schematically illustrating a cell transistor structure manufactured by a conventional method of manufacturing a DRAM memory cell, and FIG. 1B is a graph showing a concentration distribution of a channel region of a cell transistor.

As shown in FIG. 1A, various ion implantation processes are performed in the active region of the substrate 100 which is divided into the device isolation region and the active region by the device isolation layer 110. And the channel region 120, and a plurality of gate patterns 130 in which a gate oxide film, a gate conductive film, and a hard mask are sequentially stacked thereon. Then, an ion implantation process for forming a junction is performed in the substrate 100 positioned on both bottom surfaces of the gate pattern 130 to form a source / drain junction (not shown). Transistors are formed by forming insulating spacers 145 on both side walls.

However, in the method of manufacturing a DRAM memory cell according to the related art, during the ion implantation process for forming a channel region of a cell transistor, the doping concentration of the channel is increased to prevent the threshold voltage from decreasing due to the short channel effect of the transistor. Therefore, as shown in FIG. 1B, the channel region 120 has a problem of being doped at the same high concentration not only under the gate region (b) but also in the storage node junction region (a).

Accordingly, when voltage is applied to the cell transistor, an electric field concentration phenomenon occurs in the storage node junction region. Increasing the field also increases field-enhanced junction leakage, which reduces the data retention time of the DRAM.

An object of the present invention is to provide a method of manufacturing a DRAM memory cell to secure the data retention time by preventing the electric field is concentrated in the gate edge region of the cell transistor to solve the above problems.

In order to achieve the above object, the present invention provides a method of forming a channel region in an active region of a semiconductor substrate having an active region and an isolation region, forming a gate pattern on the substrate on which the channel region is formed, and forming the gate pattern. Depositing an insulating film on the entire surface of the formed substrate, etching the insulating film to form insulating spacers on sidewalls of the gate pattern, and over-etching to remove a portion of the channel region formed in the substrate; Forming a silicon growth layer to a surface height of the substrate by performing a silicon selective epitaxial growth process on the removed substrate; and annealing the substrate on which the silicon growth layer is formed. .

The gate pattern may be formed by sequentially stacking a gate oxide film, a gate conductive film, and a hard mask on the substrate, and the insulation spacer may have a dual structure in which a buffer oxide film and a nitride film are sequentially stacked from sidewalls of the gate pattern. It is preferable.

The method may further include depositing an undoped poly film on the substrate from which the channel region is removed after removing a portion of the channel region formed in the substrate, and etching back the undoped poly film to a point where the surface of the substrate is exposed. And annealing the substrate.

Another method of manufacturing a DRAM memory cell according to the present invention includes forming a channel region in an active region of a semiconductor substrate having an active region and an isolation region, forming a gate pattern on the substrate on which the channel region is formed; Forming an insulating spacer on sidewalls of the gate pattern, forming an interlayer insulating film on the substrate on which the insulating spacer is formed, and etching the interlayer insulating film to form a contact hole for a landing plug, but excessively etching the insulating layer in the substrate Removing a portion of the formed channel region, and performing a silicon selective epitaxial growth process on the substrate from which the channel region is removed to form a silicon growth layer up to a surface height of the substrate, and forming the substrate on which the silicon growth layer is formed. A method of manufacturing a DRAM memory cell comprising the step of annealing The lotuses.

The gate pattern may be formed by sequentially stacking a gate oxide film, a gate conductive film, and a hard mask on the substrate, and the insulation spacer may have a dual structure in which a buffer oxide film and a nitride film are sequentially stacked from sidewalls of the gate pattern. It is preferable.

The method may further include depositing an undoped poly film on the substrate from which the channel region is removed after removing a portion of the channel region formed in the substrate, and etching back the undoped poly film to a point where the surface of the substrate is exposed. And annealing the substrate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

A method of manufacturing a DRAM memory cell according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

A and B of FIGS. 2A to 2E are graphs showing sequential cross-sectional views and concentration distributions of channel regions of a cell transistor, in order to explain a method of manufacturing a DRAM memory cell according to a first embodiment of the present invention. to be.

First, as shown in FIG. 2A, a well region (not shown) and a channel region 120 are sequentially formed in the substrate 100 which is divided into an isolation region and an active region by the isolation layer 110. In this case, the channel region 120 is heavily doped to prevent the threshold voltage from decreasing due to the short channel effect of the cell transistor.

As illustrated in FIG. 2B, a gate pattern 130 having a structure in which a gate oxide layer, a gate conductive layer, and a hard mask are sequentially stacked on the substrate 100 on which the channel region 120 is formed is formed.                     

In addition, an insulating layer 140 is formed on the entire surface of the substrate 100 on which the gate pattern 130 is formed. In this case, the insulating layer 140 may be formed of a double layer including a buffer oxide layer and a nitride layer.

As illustrated in FIG. 2C, the insulating layer 140 is selectively etched to form an insulating spacer 145 on the sidewall of the gate pattern 130, but over-etched to also form a portion of the channel region 120 of the substrate 100. Remove Accordingly, as shown in B of FIG. 2C, the concentration of the channel region 120 positioned below the gate region (B) is high, but the channel region 120 positioned below the storage node junction region (A) is increased. Removed, the concentration is near zero.

As shown in FIG. 2D, a silicon selective epitaxial growth process is performed on the substrate 100 from which the channel region 120 is removed to the height of the surface of the substrate 100 to form the silicon growth layer 150. In this case, since the silicon growth layer 150 is grown only to the height of the surface of the substrate 100, the silicon growth layer 150 may be prevented from being electrically connected by the silicon growth layer 150 between neighboring gate patterns.

Meanwhile, instead of forming the silicon growth layer 150 on the substrate 100 from which the channel region 120 is removed, an undoped poly layer (not shown) is deposited, and the surface of the substrate 100 is exposed. It is possible to etch back to the point to have the same function as the silicon growth film.

As shown in FIG. 2E, an annealing process is performed on the substrate 100 on which the silicon growth film 150 is formed. When the annealing process is performed, as shown in B of FIG. 2E, the doped concentration of the channel region 120 under the gate region (B) is changed by the concentration difference, and thus the silicon growth layer under the storage node junction region (A). Diffused to 150, the doping concentration of the channel region 120 positioned below the gate region (b) has a bell-shaped concentration profile. That is, by reducing the doping concentration at both edges of the gate region (B), it is possible to reduce the electric field in the region where the gate induced drain leakage current (GIDL) occurs.

Next, a method of manufacturing a DRAM memory cell according to a second embodiment of the present invention will be described with reference to FIGS. 3A to 3D and FIGS. 2A and 2B.

3A to 3D are graphs showing the sequential cross-sectional views and concentration distributions of the channel regions of the cell transistors in order to explain a method of manufacturing a DRAM memory cell according to a second exemplary embodiment of the present invention. to be.

First, since the steps of FIGS. 2A to 2B are the same as those of the first embodiment of the present invention, the description will be omitted.

As shown in FIG. 3A, the insulating layer 140 is selectively etched to form insulating spacers 145 on sidewalls of the gate pattern 130. Since the insulating spacer 145 has a double structure including a buffer oxide film and a nitride film, the insulating spacer 145 preferably has a structure in which the buffer oxide film and the nitride film are sequentially stacked from the sidewall of the gate pattern 130.

As shown in FIG. 3B, an interlayer insulating layer 160 is formed thick so that the insulating spacer 145 and the gate pattern 130 are sufficiently buried in the entire surface of the substrate 100 on which the insulating spacer 145 is formed.

Then, a photosensitive material (not shown) is coated on the interlayer insulating layer 160, and an exposure and development process is performed to form a photoresist pattern 170 that defines a region for forming a contact hole for a landing plug.

Subsequently, the interlayer insulating layer 160 is selectively etched using the photoresist pattern 170 as a mask to form a landing plug forming contact hole 180, but also excessively etches a portion of the channel region 120 of the substrate 100. Remove Accordingly, as shown in B of FIG. 3B, the concentration of the channel region 120 positioned below the gate region (B) is high, but the channel region 120 positioned below the storage node junction region (A) is increased. Removed, the concentration is near zero.

As shown in FIG. 3C, a silicon selective epitaxial growth process is performed on the substrate 100 from which the channel region 120 is removed to the height of the surface of the substrate 100 to form the silicon growth layer 150. In this case, since the silicon growth layer 150 is grown only to the height of the surface of the substrate 100, the silicon growth layer 150 may be prevented from being electrically connected between the neighboring gate patterns 130 by the silicon growth layer 150.

Meanwhile, instead of forming the silicon growth layer 150 on the substrate 100 from which the channel region 120 is removed, an undoped poly layer (not shown) is deposited, and the surface of the substrate 100 is exposed. It is possible to etch back to the point to have the same function as the silicon growth film 150.

As shown in FIG. 3D, an annealing process is performed on the substrate 100 on which the silicon growth film 150 is formed. When the annealing process is performed, as shown in B of FIG. 3D, the doped concentration of the channel region 120 under the gate region (b) is reduced by the difference in concentration, and thus the silicon growth layer under the storage node junction region (a). Diffused to 150, the doping concentration of the channel region 120 positioned below the gate region (b) has a bell-shaped concentration profile. That is, by reducing the doping concentration at both edges of the gate region (B), it is possible to reduce the electric field in the region where the gate induced drain leakage current (GIDL) occurs.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

As described above, the present invention reduces the concentration of the storage node junction region and the gate edge region of the cell transistor, thereby preventing electric field concentration from occurring in the storage node junction region and the gate edge region, thereby securing data retention time.

Claims (8)

Forming a channel region in an active region of the semiconductor substrate having an active region and an isolation region; Forming a gate pattern on the substrate on which the channel region is formed; Depositing an insulating film on an entire surface of the substrate on which the gate pattern is formed; Etching the insulating layer to form insulating spacers on sidewalls of the gate pattern, and over-etching to remove a portion of the channel region formed in the substrate; Performing a silicon selective epitaxial growth process on the substrate from which the channel region is removed to form a silicon growth film up to the surface height of the substrate; And annealing the substrate on which the silicon growth film is formed. The method of claim 1, The gate pattern may be formed by sequentially stacking a gate oxide film, a gate conductive film, and a hard mask on the substrate. The method of claim 1, And the insulating spacers are formed to have a dual structure in which a buffer oxide film and a nitride film are sequentially stacked from sidewalls of the gate pattern. The method of claim 1, Depositing an undoped poly film on the substrate from which the channel region has been removed after removing a portion of the channel region formed in the substrate, and etching back the undoped poly film to a time point at which the surface of the substrate is exposed; And annealing the substrate. Forming a channel region in an active region of the semiconductor substrate having an active region and an isolation region; Forming a gate pattern on the substrate on which the channel region is formed; Forming insulating spacers on sidewalls of the gate patterns; Forming an interlayer insulating film on the substrate on which the insulating spacer is formed; Etching the interlayer insulating film to form a contact hole for a landing plug, but over-etching to remove a portion of the channel region formed in the substrate; Performing a silicon selective epitaxial growth process on the substrate from which the channel region is removed to form a silicon growth film up to the surface height of the substrate; And annealing the substrate on which the silicon growth film is formed. The method of claim 5, The gate pattern may be formed by sequentially stacking a gate oxide film, a gate conductive film, and a hard mask on the substrate. The method of claim 5, And the insulating spacers are formed to have a dual structure in which a buffer oxide film and a nitride film are sequentially stacked from sidewalls of the gate pattern. The method of claim 5, Depositing an undoped poly film on the substrate from which the channel region has been removed after removing a portion of the channel region formed in the substrate, and etching back the undoped poly film to a time point at which the surface of the substrate is exposed; And annealing the substrate.

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