KR20120012224A - Peripheral transistor and method for fabricating the same - Google Patents

Abstract

PURPOSE: A peripheral transistor and a method fabricating thereof are provided to increase a channel area of peripheral transistor by filling a plurality of recess patterns through a gate. CONSTITUTION: A substrate(11) includes an active area(13) which is defined with a device isolation film. A plurality of recess pattern(14A,14B,14C) is formed on the active area. A gate(18) fills the plurality of the recess patterns. A spacer(19) is formed in a sidewall of the gate. A source and drain region are formed in the active area.

Description

PERITHERAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a ferrite transistor disposed in a peripheral circuit region and a manufacturing method thereof.

A semiconductor device such as a DRAM is composed of a cell region and a peripheral circuit region. In the cell region, a cell transistor and a capacitor are integrated to store data, and a peripheral circuit region includes a circuit for controlling the operation of the cell region. In this case, the peripheral circuit region constitutes a circuit using a plurality of peripheral transistors, and the peripheral transistors are planar type transistors.

The ferrite transistor has a relatively larger size than the cell transistor, but as the design rule becomes smaller, the size of the ferrite transistor is continuously decreasing. As such, as the size of the ferrite transistor is reduced, the channel area of the ferrite transistor is necessarily reduced. As a result, the amount of current that can be controlled by the ferrite transistor is reduced, resulting in a problem that the operation speed of the semiconductor device is lowered.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a ferrite transistor and a method of manufacturing the same that can increase the channel area of a ferrite transistor without increasing its overall size.

According to an aspect of the present invention, there is provided a substrate including an active region defined by an isolation layer; A plurality of recess patterns formed in the active region; A gate filling all of the plurality of recess patterns; And a spacer formed on the sidewall of the gate. Here, the ferrite transistor further includes a source and a drain region formed in the active region on both sides of the gate.

Both ends of the gate may have a structure extending above the device isolation layer. The gate may have a structure in which a portion of the gate fills the plurality of recess patterns, and a portion of the gate protrudes onto the substrate.

The width of the plurality of recess patterns in the channel length direction may be equal to or greater than 2/3 of the gate width. The width of the plurality of recess patterns in the channel length direction may be equal to or smaller than the sum of 2/3 of the gate width and the thickness of the spacer.

The plurality of recess patterns may have a slit shape.

According to another aspect of the present invention, there is provided a device isolation film on a substrate, the method comprising: defining an active region; Selectively etching the active region to form a plurality of recess patterns; Forming a gate filling the plurality of recess patterns; And it provides a ferrite transistor manufacturing method comprising the step of forming a spacer on both side walls of the gate. In this case, after the gate is formed, the ferrite transistor manufacturing method may further include forming source and drain regions by implanting impurities into the active regions on both sides of the gate.

The forming of the plurality of recess patterns may include forming a mask pattern on the substrate, the mask pattern having a slit-shaped opening that exposes the active region of a gate predetermined region; And etching the substrate using the mask pattern as an etch barrier.

In the forming of the plurality of recess patterns, the widths of the plurality of recess patterns in the channel length direction may be equal to or greater than 2/3 of the gate width. The width of the plurality of recess patterns in the channel length direction may be equal to or smaller than the sum of 2/3 of the gate width and the thickness of the spacer.

The forming of the gate may include forming a gate insulating film on a surface of the active region; Filling the plurality of recess patterns and forming a gate conductive layer to cover the entire surface of the substrate; Forming a gate hard mask layer on the gate conductive layer; And sequentially etching the gate hard mask layer, the gate conductive layer, and the gate insulating layer. The forming of the gate may include forming a structure in which both ends of the gate extend to an upper portion of the device isolation layer.

The present invention based on the above-described problem solving means has a structure in which the gate 18 of the ferrite transistor embedded all of the plurality of recess patterns 14A, 14B, 14C, so that the channel length and channel without increasing the overall size The effect is to increase the width at the same time. In other words, the channel area of the ferrite transistor can be increased without increasing the overall size.

As a result, the present invention can increase the amount of current that can be controlled by the ferrite transistor, and there is an effect of improving the operation speed of the semiconductor device.

1A to 1C are diagrams illustrating a ferrite transistor according to an embodiment of the present invention.
2a to 2c and 3a to 3c is a process diagram showing a method of manufacturing a ferrite transistor according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later provides a ferrite transistor and a method of manufacturing the same that can increase the channel area of the peristorer without increasing the size of the peripheral transistor (peripheral transistor) disposed in the peripheral circuit region.

1A to 1C are views illustrating a ferrite transistor according to an embodiment of the present invention, FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A, and FIG. 1C is a view. A cross-sectional view taken along the line Y-Y 'shown in 1a.

As shown in FIGS. 1A to 1C, a ferrite transistor according to an embodiment of the present invention may be formed on a substrate 11 and an active region 13 having an active region 13 defined by an isolation layer 12. And a plurality of recess patterns 14A, 14B, and 14C, a gate 18 filling all of the plurality of recess patterns 14A, 14B, and 14C, and spacers 19 formed on sidewalls of the gate 18. Although not shown, source and drain regions are formed in the active region 13 at both sides of the gate 18.

The plurality of recess patterns 14A, 14B, and 14C play a role of increasing the channel area of the ferrite transistor and may have a slit shape. In this case, the plurality of recess patterns 14A, 14B, and 14C having a slit shape may be formed such that the major axis is perpendicular to the channel width direction (ie, the second direction). In addition, the plurality of recess patterns 14A, 14B, and 14C may have the same shape as shown in the drawing, or each of the recess patterns 14A, 14B, and 14C may have a different shape. Here, the plurality of recess patterns 14A, 14B, and 14C may have various shapes and combinations of shapes other than those described above, and the restriction on the shapes and combinations of shapes within the range that can increase the channel area is none.

In addition, the plurality of recess patterns 14A, 14B, and 14C may have a depth in a range of 200 μs to 1500 μs based on the upper surface of the substrate 11. In this case, the depth of the plurality of recess patterns 14A, 14B, and 14C may be smaller than the depth of the device isolation layer 12.

Further, the width W1 of the plurality of recess patterns 14A, 14B, and 14C in the channel length direction (ie, the first direction) is equal to or greater than 2/3 of the width W2 of the gate 18. Can be. In addition, the width W1 of the plurality of recess patterns 14A, 14B, and 14C in the channel length direction is the sum (W2 + W3) of 2/3 of the width W2 of the gate 18 and the thickness W3 of the spacer 19. May be equal to or smaller than).

The gate 18 embeds all of the plurality of recess patterns 14A, 14B, and 14C on the gate insulating layer 15 and the gate insulating layer 15 formed on the surfaces of the plurality of recess patterns 14A, 14B, and 14C. The gate electrode 16 protruding from the substrate 11 and the gate hard mask layer 17 formed on the gate electrode 16 may be stacked.

In addition, the gate 18 may have a structure in which both ends of the gate 18 extend in the channel width direction (ie, the second direction) to the upper portion of the device isolation layer 12.

The ferrite transistor having the above-described structure has a structure in which the gate 18 embeds all of the plurality of recess patterns 14A, 14B, and 14C, thereby simultaneously increasing the channel length and the channel width without increasing the overall size. . That is, the channel area can be increased without increasing the overall size. At this time, if the channel length is increased, leakage current can be prevented. If the channel width is increased, the threshold voltage can be increased and the gate control power can be improved. Therefore, by increasing the channel area of the ferrite transistor, it is possible to increase the amount of current that the ferrite transistor can control, thereby increasing the operating speed of the semiconductor device.

2A to 2C and 3A to 3C are process diagrams illustrating a method of manufacturing a ferrite transistor according to an embodiment of the present invention. 2A and 3A are top views, FIGS. 2B and 3B are cross-sectional views taken along the line X-X 'shown in FIGS. 2A and 3A, respectively, and FIGS. 2C and 3C are Y- shown in FIGS. 2A and 3A, respectively. A cross-sectional view taken along the line Y '.

2A to 2C, an isolation region 12 is formed on the substrate 11 to define the active region 13. A silicon substrate may be used as the substrate 11, and the device isolation layer 12 may be formed by a shallow trench isolation (STI) process.

Next, a mask pattern (not shown) having an opening for exposing the active region 13 of the gate region to be formed is formed on the substrate 11. In this case, the opening of the mask pattern may have a slit shape.

Next, the substrate 11 is etched using the mask pattern as an etch barrier to form a plurality of recess patterns 14A, 14B, and 14C. Here, the plurality of recess patterns 14A, 14B, and 14C play a role of increasing the channel area of the ferrite transistor and may have a slit shape. In this case, the plurality of recess patterns 14A, 14B, and 14C having a slit shape may be formed such that the major axis is perpendicular to the channel width direction (ie, the second direction).

In addition, the plurality of recess patterns 14A, 14B, and 14C may be formed to have a depth smaller than that of the device isolation layer 12 based on the upper surface of the substrate 11. For example, the plurality of recess patterns 14A, 14B, and 14C may be formed to have a depth in a range of 200 ns to 1500 ns.

In addition, the width of the plurality of recess patterns 14A, 14B, and 14C in the channel length direction (ie, the first direction) may be equal to or larger than 2/3 of the gate width to be formed through a subsequent process. have. In addition, the width of the plurality of recess patterns 14A, 14B, and 14C in the channel length direction may be equal to or smaller than the sum of 2/3 of the gate width and the thickness of the spacer to be formed through a subsequent process.

Next, the mask pattern is removed, and a cleaning process for removing by-products generated in the process of forming the plurality of recess patterns 14A, 14B, and 14C is performed.

As shown in FIGS. 3A to 3C, a gate insulating film 15 is formed on the surface of the active region 13. The gate insulating film 15 may be formed of an oxide film, for example, a silicon oxide film (SiO ₂ ). The silicon oxide film can be formed using a thermal oxidation method.

Next, all of the plurality of recess patterns 14A, 14B, and 14C are embedded in the entire surface of the substrate 11 on which the gate insulating film 15 is formed, and a gate conductive film is formed to cover the entire surface of the substrate 11. In this case, the gate conductive film may be formed as a laminated film in which a polysilicon film and a metal film are stacked.

Next, a gate hard mask film 17 is formed on the gate conductive film. The gate hard mask film 17 may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or a laminated film in which they are stacked.

Next, the gate hard mask film 17, the gate conductive film, and the gate insulating film 15 are selectively etched to form a gate 18 filling all of the plurality of recess patterns 14A, 14B, and 14C. In this case, the gate 18 may be formed to have a structure in which both ends of the gate 18 extend above the device isolation layer 12 in the channel width direction (ie, the second direction). As a result, the gate 18 is a stacked structure in which the gate insulating film 15, the gate electrode 16, and the gate hard mask film 17 are stacked.

Next, a spacer 19 is formed on the sidewall of the gate 18. The spacer 19 may be formed through a series of processes in which an entire surface is etched, for example, etch back, after the insulating film is deposited on the entire surface.

Next, although not shown, impurities are implanted into the active regions 13 on both sides of the gate 18 to form source and drain regions.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

11 substrate 12 device isolation film
13: active area 14A, 14B, 14C: plurality of recess patterns
15 gate insulating film 16 gate electrode
17: gate hard mask film 18: gate
19: spacer

Claims (14)

A substrate having an active region defined by an isolation layer;
A plurality of recess patterns formed in the active region;
A gate filling all of the plurality of recess patterns; And
Spacers formed on the sidewalls of the gate
Ferrite transistor comprising a.
The method of claim 1,
And a source and a drain region formed in the active region at both sides of the gate.
The method of claim 1,
A ferrite transistor having a structure in which both ends of the gate extend above the device isolation layer.
The method of claim 1,
And the gate partially fills the plurality of recess patterns, and the rest protrudes onto the substrate.
The method of claim 1,
And the width of the plurality of recess patterns in the channel length direction is equal to or greater than two thirds of the gate width.
The method of claim 5,
And the width of the plurality of recess patterns in the channel length direction is equal to or smaller than the sum of two-thirds of the gate width and the thickness of the spacer.
The method of claim 1,
The plurality of recess patterns have a slit shape.
Forming an isolation region on the substrate to define an active region;
Selectively etching the active region to form a plurality of recess patterns;
Forming a gate filling the plurality of recess patterns; And
Forming spacers on both side walls of the gate
Ferry transistor manufacturing method comprising a.
The method of claim 8,
After forming the gate,
And implanting impurities into the active regions on both sides of the gate to form a source and a drain region.
The method of claim 8,
Forming the plurality of recess patterns may include:
Forming a mask pattern on the substrate, the mask pattern having a slit-shaped opening exposing the active region of a gate predetermined region; And
Etching the substrate using the mask pattern as an etch barrier
Ferry transistor manufacturing method comprising a.
The method of claim 8,
Forming the plurality of recess patterns may include:
And the width of the plurality of recess patterns in the channel length direction is equal to or greater than 2/3 of the gate width.
The method of claim 11,
And the width of the plurality of recess patterns in the channel length direction is equal to or smaller than the sum of two-thirds of the gate width and the thickness of the spacer.
The method of claim 8,
Forming the gate,
Forming a gate insulating film on a surface of the active region;
Filling the plurality of recess patterns and forming a gate conductive layer to cover the entire surface of the substrate;
Forming a gate hard mask layer on the gate conductive layer; And
Sequentially etching the gate hard mask layer, the gate conductive layer, and the gate insulating layer
Ferry transistor manufacturing method comprising a.
The method of claim 8,
Forming the gate,
A method of manufacturing a ferrite transistor, wherein both ends of the gate are formed to have a structure extending above the device isolation layer.

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