KR20020002706A - Transistor and method for manufacturing the same - Google Patents

Transistor and method for manufacturing the same Download PDF

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Publication number
KR20020002706A
KR20020002706A KR1020000036958A KR20000036958A KR20020002706A KR 20020002706 A KR20020002706 A KR 20020002706A KR 1020000036958 A KR1020000036958 A KR 1020000036958A KR 20000036958 A KR20000036958 A KR 20000036958A KR 20020002706 A KR20020002706 A KR 20020002706A
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South Korea
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substrate
layer
gate electrode
conductive layer
source
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KR1020000036958A
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Korean (ko)
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정혁제
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000036958A priority Critical patent/KR20020002706A/en
Publication of KR20020002706A publication Critical patent/KR20020002706A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

PURPOSE: A transistor is provided to reduce a junction leakage current and to increase retention time, by forming a conductive layer electrically connected to a source/drain region on an isolation oxide layer adjacent to the source/drain region. CONSTITUTION: An isolation layer(32) is formed in an isolation region of a substrate(31), having the conductive layer(34) adjacent to an active region. A gate electrode(36) is formed on the substrate by interposing a gate insulation layer. The transistor is formed in the surface of the substrate at both sides of the gate electrode, including the source/drain region(37) electrically connected to the conductive layer.

Description

트랜지스터 및 그의 제조 방법{TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME}Transistor and its manufacturing method {TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME}

본 발명은 트랜지스터 및 그의 제조 방법에 관한 것으로, 특히 소오스/드레인 영역에 인접한 소자 분리 산화막에 상기 소오스/드레인 영역과 전기적으로 연결되는 도전층을 형성하여 소자의 신뢰성을 향상시키는 트랜지스터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a transistor and a method for manufacturing the same, in which a conductive layer electrically connected to the source / drain region is formed in a device isolation oxide film adjacent to a source / drain region. It is about.

도 1a와 도 1b는 종래의 기술에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

종래의 트랜지스터의 제조 방법은 도 1a에서와 같이, p형인 반도체 기판(11)의 격리 영역에 일반적인 에스티아이(Shallow Trench Isolation : STI) 공정에 의해 소자 분리 산화막(12)을 형성한다.In the conventional method of manufacturing a transistor, as shown in FIG. 1A, the device isolation oxide film 12 is formed by a general shallow trench isolation (STI) process in an isolation region of the p-type semiconductor substrate 11.

그리고, 상기 반도체 기판(11)상에 열산화 공정으로 게이트 산화막(13)을 성장시킨 다음, 상기 게이트 산화막(13)상에 다결정 실리콘층과 감광막(도시하지 않음)을 순차적으로 형성한다.After the gate oxide film 13 is grown on the semiconductor substrate 11 by a thermal oxidation process, a polycrystalline silicon layer and a photosensitive film (not shown) are sequentially formed on the gate oxide film 13.

이어, 상기 감광막을 게이트 전극이 형성될 부위에서만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 감광막을 마스크로 상기 다결정 실리콘층과 게이트 산화막(13)을 선택 식각하여 게이트 전극(14)을 형성한 후, 상기 감광막을 제거한다.Subsequently, the photoresist film is selectively exposed and developed so that only the portion where the gate electrode is to be formed remains, and then the polycrystalline silicon layer and the gate oxide layer 13 are selectively etched using the selectively exposed and developed photoresist mask as a gate electrode 14. ), The photosensitive film is removed.

도 1b에서와 같이, 상기 게이트 전극(14)을 마스크로 전면에 n형 불순물 이온주입 공정을 실시하고, 드라이브-인(Drive-in) 확산함으로써 상기 게이트 전극(14) 양측의 반도체 기판(11) 표면내에 소오스/드레인 영역(15)을 형성한다.As shown in FIG. 1B, an n-type impurity ion implantation process is performed on the entire surface of the gate electrode 14 using a mask, and drive-in diffusion is used to form semiconductor substrates 11 on both sides of the gate electrode 14. Source / drain regions 15 are formed in the surface.

그러나 종래의 트랜지스터 및 그의 제조 방법은 소오스/드레인 영역의 면적에 따라 데이터(Data)가 하부전극에 저장되어 있는 동안의 캐패시터 등과의 접합누설전류가 증가하므로 소자의 리텐션 타임(Retention time)이 감소하는 문제점이 있었다.However, in the conventional transistor and its manufacturing method, the retention time of the device is reduced because the junction leakage current with the capacitor and the like while the data is stored in the lower electrode increases with the area of the source / drain regions. There was a problem.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 소오스/드레인 영역에 인접한 소자 분리 산화막에 상기 소오스/드레인 영역과 전기적으로 연결되는 도전층을 형성하여 상기 소오스/드레인 영역의 면적을 줄이므로 소자의 리텐션 타임을 증가시키는 트랜지스터 및 그의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned problem, and a conductive layer electrically connected to the source / drain region is formed in the device isolation oxide adjacent to the source / drain region to reduce the area of the source / drain region. It is an object of the present invention to provide a transistor for increasing the retention time and a method of manufacturing the same.

도 1a와 도 1b는 종래의 기술에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도1A and 1B are cross-sectional views illustrating a method of manufacturing a transistor according to the prior art.

도 2는 본 발명의 실시 예에 따른 트랜지스터를 나타낸 구조 단면도2 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도3A to 3D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

31 : 반도체 기판 32 : 소자 분리 산화막31 semiconductor substrate 32 device isolation oxide film

33 : 제 1 감광막 34 : 도전층33: first photosensitive film 34: conductive layer

35 : 게이트 산화막 36 : 게이트 전극35 gate oxide film 36 gate electrode

37 : 소오스/드레인 영역37 source / drain regions

본 발명의 트랜지스터는 기판의 격리 영역에 활성 영역과 인접하여 형성되는 도전층을 갖으며 형성되는 소자 분리막, 상기 기판상에 게이트 절연막을 개재하며 형성되는 게이트 전극 및 상기 게이트 전극 양측의 기판 표면내에 형성되며 상기 도전층과 전기적으로 연결되는 소오스/드레인 영역을 포함하여 구성됨을 특징으로 한다.The transistor of the present invention is formed in an isolation region of a substrate, the device isolation layer being formed adjacent to the active region, a gate electrode formed on the substrate with a gate insulating film interposed therebetween, and formed in the substrate surface on both sides of the gate electrode. And a source / drain region electrically connected to the conductive layer.

그리고, 본 발명의 트랜지스터의 제조 방법은 기판의 격리 영역에 소자 분리막을 형성하는 단계, 상기 활성 영역과 인접한 부위의 소자 분리막을 선택 식각하는 단계, 상기 소자 분리막의 식각 부위에 도전층을 형성하여 메꾸는 단계, 상기 기판상에 게이트 절연막을 개재한 게이트 전극을 형성하는 단계 및 상기 게이트 전극 양측의 반도체 기판 표면내에 상기 도전층과 전기적으로 연결되는 소오스/드레인 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a transistor of the present invention, forming an isolation layer in an isolation region of a substrate, selectively etching an isolation layer in a region adjacent to the active region, and forming a conductive layer in an etching portion of the isolation layer Forming a gate electrode through a gate insulating film on the substrate, and forming a source / drain region electrically connected to the conductive layer in a surface of the semiconductor substrate on both sides of the gate electrode. It is done.

상기와 같은 본 발명에 따른 트랜지스터 및 그의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the transistor according to the present invention and a manufacturing method thereof as follows.

도 2는 본 발명의 실시 예에 따른 트랜지스터를 나타낸 구조 단면도이다.2 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.

본 발명의 실시 예에 따른 트랜지스터는 도 2에서와 같이, 반도체 기판(31)의 격리 영역에 활성 영역과 인접하여 형성되는 도전층(34)을 갖으며 형성되는 소자 분리 산화막(32), 상기 반도체 기판(31)상에 게이트 산화막(35)을 개재하며 형성되는 게이트 전극(36), 상기 게이트 전극(36) 양측의 반도체 기판(31) 표면내에 형성되는 전기적으로 연결되는 소오스/드레인 영역(37)으로 구성된다.In the transistor according to the embodiment of the present invention, as shown in FIG. 2, the device isolation oxide layer 32 formed with the conductive layer 34 formed adjacent to the active region in the isolation region of the semiconductor substrate 31, the semiconductor A gate electrode 36 formed on the substrate 31 via a gate oxide film 35, and an electrically connected source / drain region 37 formed in a surface of the semiconductor substrate 31 on both sides of the gate electrode 36. It consists of.

도 3a 내지 도 3d는 본 발명의 실시 예에 따른 트랜지스터의 제조 방법을 나타낸 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

본 발명의 실시 예에 따른 트랜지스터의 제조 방법은 도 3a에서와 같이, p형인 반도체 기판(31)의 격리 영역에 일반적인 STI 공정에 의해 소자 분리 산화막(32)을 형성한다.In the method of manufacturing a transistor according to the embodiment of the present invention, as shown in FIG. 3A, the device isolation oxide layer 32 is formed by a general STI process in an isolation region of the p-type semiconductor substrate 31.

여기서, 상기 소자 분리 산화막(32)을 종래의 소자 분리 산화막보다 넓게 형성한다.Here, the device isolation oxide film 32 is formed wider than the conventional device isolation oxide film.

그리고, 상기 소자 분리 산화막(32)을 포함한 반도체 기판(31)상에 제 1 감광막(33)을 도포한 후, 상기 제 1 감광막(33)을 활성 영역과 인접한 부위로써 소오스/드레인 영역과 전기적으로 연결되는 도전층이 형성될 부위에서만 제거되도록 선택적으로 노광 및 현상한다.After the first photoresist layer 33 is applied onto the semiconductor substrate 31 including the device isolation oxide layer 32, the first photoresist layer 33 is electrically connected to the source / drain regions as a portion adjacent to the active region. It is selectively exposed and developed to remove only at the site where the conductive layer to be joined is to be formed.

이어, 상기 선택적으로 노광 및 현상된 제 1 감광막(33)을 마스크로 상기 소자 분리 산화막(32)을 선택 식각한다.Subsequently, the device isolation oxide layer 32 is selectively etched using the selectively exposed and developed first photoresist layer 33 as a mask.

도 3b에서와 같이, 상기 제 1 감광막(33)을 제거한 후, 상기 식각된 소자 분리 산화막(32)을 포함한 반도체 기판(31)상에 도전층(34)을 형성하고, 상기 도전층(34)을 상기 반도체 기판(31)의 식각 종말점으로 에치백(Etch back)하여 상기 소자 분리 산화막(32)의 식각된 부위를 메꾼다.As shown in FIG. 3B, after removing the first photoresist layer 33, a conductive layer 34 is formed on the semiconductor substrate 31 including the etched device isolation oxide layer 32, and the conductive layer 34 is formed. Is etched back to the etching end point of the semiconductor substrate 31 to fill the etched portion of the device isolation oxide layer 32.

도 3c에서와 같이, 상기 반도체 기판(31)상에 열산화 공정으로 게이트 산화막(35)을 성장시킨 다음, 상기 게이트 산화막(35)상에 다결정 실리콘층과 제 2 감광막(도시하지 않음)을 순차적으로 형성한다.As shown in FIG. 3C, a gate oxide film 35 is grown on the semiconductor substrate 31 by a thermal oxidation process, and then a polycrystalline silicon layer and a second photoresist film (not shown) are sequentially formed on the gate oxide film 35. To form.

이어, 상기 제 2 감광막을 게이트 전극이 형성될 부위에서만 남도록 선택적으로 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 2 감광막을 마스크로 상기 다결정 실리콘층과 게이트 산화막(35)을 선택 식각하여 게이트 전극(36)을 형성한 후, 상기 제 2 감광막을 제거한다.Subsequently, after selectively exposing and developing the second photoresist film so as to remain only at a portion where a gate electrode is to be formed, the polycrystalline silicon layer and the gate oxide layer 35 are selectively etched using the selectively exposed and developed second photoresist film as a mask. After the gate electrode 36 is formed, the second photosensitive film is removed.

도 3d에서와 같이, 상기 게이트 전극(36)을 마스크로 전면에 n형 불순물 이온주입 공정을 실시하고, 드라이브-인 확산함으로써 상기 게이트 전극(36) 양측의 반도체 기판(31) 표면내에 소오스/드레인 영역(37)을 형성한다.As shown in FIG. 3D, an n-type impurity ion implantation process is performed on the entire surface with the gate electrode 36 as a mask and drive-in diffusion to form a source / drain in the surface of the semiconductor substrate 31 on both sides of the gate electrode 36. The area 37 is formed.

이때, 상기 소오스/드레인 영역(37)은 상기 도전층(34)과 전기적으로 연결된다.In this case, the source / drain region 37 is electrically connected to the conductive layer 34.

상술한 본 발명에 있어서, 상기 도전층(34)을 상기 게이트 전극(36) 형성용 다결정 실리콘층으로 상기 식각된 소자 분리 산화막(32)을 메꾸어 형성할 수 있다.In the present invention described above, the etched device isolation oxide layer 32 may be formed by filling the conductive layer 34 with the polycrystalline silicon layer for forming the gate electrode 36.

그리고, 후속 공정에서 형성될 캐패시터가 상기 도전층(34)에 접하여 형성된다.A capacitor to be formed in a subsequent step is formed in contact with the conductive layer 34.

본 발명의 트랜지스터 및 그의 제조 방법은 소오스/드레인 영역에 인접한 소자 분리 산화막에 상기 소오스/드레인 영역과 전기적으로 연결되는 도전층을 형성하므로, 소오스/드레인 영역의 면적을 종래보다 작게 형성하여 접합 누설 전류를 감소시켜 소자의 리텐션 타임을 증가시키므로 소자의 신뢰성을 향상시키는 효과가 있다.In the transistor of the present invention and a method of manufacturing the same, a conductive layer electrically connected to the source / drain region is formed in an element isolation oxide film adjacent to the source / drain region, so that the area of the source / drain region is smaller than that of the conventional junction leakage current. Since the increase of the retention time of the device is reduced, the reliability of the device is improved.

Claims (2)

기판의 격리 영역에 활성 영역과 인접하여 형성되는 도전층을 갖으며 형성되는 소자 분리막;An isolation layer having a conductive layer formed adjacent to the active region in an isolation region of the substrate; 상기 기판상에 게이트 절연막을 개재하며 형성되는 게이트 전극;A gate electrode formed on the substrate with a gate insulating film interposed therebetween; 상기 게이트 전극 양측의 기판 표면내에 형성되며 상기 도전층과 전기적으로 연결되는 소오스/드레인 영역을 포함하여 구성됨을 특징으로 하는 트랜지스터.And a source / drain region formed in the substrate surface on both sides of the gate electrode and electrically connected to the conductive layer. 기판의 격리 영역에 소자 분리막을 형성하는 단계;Forming an isolation layer in an isolation region of the substrate; 상기 활성 영역과 인접한 부위의 소자 분리막을 선택 식각하는 단계;Selectively etching the device isolation layer adjacent to the active region; 상기 소자 분리막의 식각 부위에 도전층을 형성하여 메꾸는 단계;Forming a conductive layer on the etched portion of the device isolation layer to fill it; 상기 기판상에 게이트 절연막을 개재한 게이트 전극을 형성하는 단계;Forming a gate electrode on the substrate with a gate insulating film interposed therebetween; 상기 게이트 전극 양측의 반도체 기판 표면내에 상기 도전층과 전기적으로 연결되는 소오스/드레인 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 트랜지스터의 제조 방법.And forming a source / drain region electrically connected to the conductive layer in the surface of the semiconductor substrate on both sides of the gate electrode.
KR1020000036958A 2000-06-30 2000-06-30 Transistor and method for manufacturing the same KR20020002706A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100446312B1 (en) * 2002-06-29 2004-09-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device induced junction leakage
KR20190051671A (en) 2017-11-07 2019-05-15 정혁제 Semiconductor device and preparing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100446312B1 (en) * 2002-06-29 2004-09-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device induced junction leakage
KR20190051671A (en) 2017-11-07 2019-05-15 정혁제 Semiconductor device and preparing method thereof

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