KR970054340A - Method of manufacturing transistor of semiconductor device - Google Patents

Method of manufacturing transistor of semiconductor device Download PDF

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Publication number
KR970054340A
KR970054340A KR1019950048748A KR19950048748A KR970054340A KR 970054340 A KR970054340 A KR 970054340A KR 1019950048748 A KR1019950048748 A KR 1019950048748A KR 19950048748 A KR19950048748 A KR 19950048748A KR 970054340 A KR970054340 A KR 970054340A
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KR
South Korea
Prior art keywords
forming
etching
entire structure
semiconductor device
junction region
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Application number
KR1019950048748A
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Korean (ko)
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KR0172743B1 (en
Inventor
김상용
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950048748A priority Critical patent/KR0172743B1/en
Publication of KR970054340A publication Critical patent/KR970054340A/en
Application granted granted Critical
Publication of KR0172743B1 publication Critical patent/KR0172743B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

Abstract

본 발명은 접합영역과 채널영역을 산화막 스페이서에 의해 격리시키므로서 단 채널 효과 억제 및 소자의 안정성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 트랜지스터 제조 방법이 개시된다.The present invention discloses a method for fabricating a transistor of a semiconductor device capable of improving the stability and reliability of a device and suppressing short channel effects by isolating the junction region and the channel region by an oxide film spacer.

Description

반도체 소자의 트랜지스터 제조 방법Method of manufacturing transistor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (1)

반도체 소자의 트랜지스터 제조 방법에 있어서, 실리콘 기판상에 웰이 형성된 후, 소자 분리를 위해 필드 산화막을 형성하는 단계와, 상기 전체 구조 상부에 감광막이 도포되고 포토리소그라피공정으로 상기 감광막을 패턴닝하는 단계와, 상기 웰이 감광막을 마스크로 이용한 식각공정으로 식각되어 트랜치를 형성하고, 상기 전체 구조 상부에 산화막을 증착하는 단계와, 상기 산화막을 식각 공정에 의해 접합영역의 트랜치 측벽에 산화막 스페이서를 형성하는 단계와, 상기 전체 구조 상부에 폴리실리콘층을 형성하고, 상기 폴리실리콘층과 필드 산화막이 CMP공정으로 식각되어 접합영역의 트랜치에는 폴리실리콘이 남게 되고, 필드 산화막을 평탄화시키는 단계와, 상기 웰 상부에 게이트 전극을 형성하고, 게이트 전극 측벽에 산화막 스페이서를 형성하는 단계와, 상기 전체 구조 상부에 불순물이 주입되어 접합영역이 형성하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.In the method of manufacturing a transistor of a semiconductor device, after the well is formed on a silicon substrate, forming a field oxide film for device isolation, a photosensitive film is applied on the entire structure and patterning the photosensitive film by a photolithography process And forming a trench by etching the well by an etching process using a photoresist as a mask, depositing an oxide film on the entire structure, and forming an oxide spacer on the trench sidewalls of the junction region by etching the oxide film. And forming a polysilicon layer on the entire structure, and etching the polysilicon layer and the field oxide layer by a CMP process to leave polysilicon in the trench of the junction region, and planarizing the field oxide layer, and A gate electrode is formed on the gate electrode, and an oxide spacer is formed on the sidewall of the gate electrode. And implanting impurities into the entire structure to form a junction region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950048748A 1995-12-12 1995-12-12 Method of manufacturing transistor in semiconductor device KR0172743B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950048748A KR0172743B1 (en) 1995-12-12 1995-12-12 Method of manufacturing transistor in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950048748A KR0172743B1 (en) 1995-12-12 1995-12-12 Method of manufacturing transistor in semiconductor device

Publications (2)

Publication Number Publication Date
KR970054340A true KR970054340A (en) 1997-07-31
KR0172743B1 KR0172743B1 (en) 1999-02-01

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Application Number Title Priority Date Filing Date
KR1019950048748A KR0172743B1 (en) 1995-12-12 1995-12-12 Method of manufacturing transistor in semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100345522B1 (en) * 1999-12-31 2002-07-24 아남반도체 주식회사 Method for forming gate of transistor
KR100345521B1 (en) * 1999-12-31 2002-07-24 아남반도체 주식회사 Method for forming gate of transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100345522B1 (en) * 1999-12-31 2002-07-24 아남반도체 주식회사 Method for forming gate of transistor
KR100345521B1 (en) * 1999-12-31 2002-07-24 아남반도체 주식회사 Method for forming gate of transistor

Also Published As

Publication number Publication date
KR0172743B1 (en) 1999-02-01

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