KR960026570A - Highly Integrated Semiconductor Device Manufacturing Method - Google Patents

Highly Integrated Semiconductor Device Manufacturing Method Download PDF

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Publication number
KR960026570A
KR960026570A KR1019940037517A KR19940037517A KR960026570A KR 960026570 A KR960026570 A KR 960026570A KR 1019940037517 A KR1019940037517 A KR 1019940037517A KR 19940037517 A KR19940037517 A KR 19940037517A KR 960026570 A KR960026570 A KR 960026570A
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KR
South Korea
Prior art keywords
oxide film
forming
film
field oxide
silicon
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Application number
KR1019940037517A
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Korean (ko)
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KR0147428B1 (en
Inventor
고요환
박찬광
황성민
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940037517A priority Critical patent/KR0147428B1/en
Publication of KR960026570A publication Critical patent/KR960026570A/en
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Publication of KR0147428B1 publication Critical patent/KR0147428B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

본 발명은 버즈빅에 의한 활성영역의 감소와 필드산화막과 주변의 활성영역과의 단차 발생을 방지하기 위한 고집적 반도체 소자 제조방법에 관한 것으로, 반도체 소자에 사용되는 소자와 소자 사이를 절연시켜 주는 필드 산화막의 제조과정 중 실리콘 기판 상부에 마스크를 사용하여 필드 산화막을 형성할 영역 이외의 영역에 감광 물질을 형성한 다음, O2임플란트를 한 후 열처리를 함으로써 필드산화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a highly integrated semiconductor device for reducing the active area caused by Buzzvik and preventing the step difference between the field oxide film and the surrounding active area. by a using a mask in the silicon substrate during the manufacturing process of the oxide film to form a photosensitive material in a region other than the region to form the field oxide film and then the next, O 2 implant the heat treatment that comprises the steps of forming a field oxide film It features.

Description

고집적 반도체 소자 제조방법Highly Integrated Semiconductor Device Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 및 제1B도는 본 발명의 제1실시예에 따른 제조과정을 나타내는 단면도, 제2A도 내지 제2C도는 본발명의 제2실시예에 따른 제조과정3을 나타내는 단면도, 제3A도 내지 제3C도는 본 발명의 제3실시예에 따른 제조과정을 나타내는 단면도.1A and 1B are cross-sectional views showing a manufacturing process according to the first embodiment of the present invention, Figures 2A to 2C are cross-sectional views showing a manufacturing process 3 according to a second embodiment of the present invention, Figures 3A to 3C is a sectional view showing a manufacturing process according to the third embodiment of the present invention.

Claims (7)

반도체 소자에 사용되는 소자와 소자 사이를 절연시켜 주는 필드산화막의 제조과정 중 실리콘 기판 상에 필드산화막을 형성할 영역 이외의 영역에 이온주입 마스크를 형성하는 단계; 상기 이온주입 마스크를 차단막으로 O2임플란트를 한 후 열처리 함으로써 필드산화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.Forming an ion implantation mask in a region other than a region in which a field oxide film is to be formed on a silicon substrate during a process of manufacturing a field oxide film that insulates the device and the device used in the semiconductor device; And forming a field oxide film by performing heat treatment after the O 2 implant is formed using the ion implantation mask as a blocking film. 제1항에 있어서, 상기 이온주입 마스크를 형성하는 단계는 반도체기판 상부에 감광막을 도포한 다음, 게이트전극용 마스크로 리소그래피 공정을 진행하여 필드산화막이 형성될 영역의 상기 반도체기판을 노출시키는 단계를 포함하여 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.The method of claim 1, wherein the forming of the ion implantation mask comprises applying a photoresist film over the semiconductor substrate and then performing a lithography process with a mask for a gate electrode to expose the semiconductor substrate in a region where a field oxide film is to be formed. Highly integrated semiconductor device manufacturing method comprising a. 제1항에 있어서, 상기 이온주입 마스크를 형성하는 단계는 반도체기판 상부에 제1차 질화층을 형성한 후 마스크를 사용하여 필드산화막을 형성할 부분 이외의 영역에 형성된 상기 제1차 질화층을 식각하는 단게; 제2차 질화층을 사용하여 상기 제1차 질화층 측면에 스페이서를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.The method of claim 1, wherein the forming of the ion implantation mask comprises forming the first nitride layer on the semiconductor substrate, and then forming the first nitride layer formed in a region other than a portion where a field oxide film is to be formed using a mask. Etching steps; And forming a spacer on the side of the first nitride layer by using a second nitride layer. 제3항에 있어서, 상기 제1차 질화층 및 제2차 질화층 사이에 O2임플란트를 한 후 열처리 함으로써 필드산화층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.4. The method of claim 3, further comprising forming a field oxide layer by performing a heat treatment after the O 2 implant is formed between the first nitride layer and the second nitride layer. 5. 제1항에 있어서, 상기 이온주입 마스크는 실리콘산화막, 다결정실리콘막, 실리콘산화막과 실리콘질화막의 이중구조, 또는 실리콘산화막과 다결정실리콘막과 실리콘질화막의 삼중구조 중 어느 하나로 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.The semiconductor device of claim 1, wherein the ion implantation mask comprises any one of a silicon oxide film, a polycrystalline silicon film, a double structure of a silicon oxide film and a silicon nitride film, or a triple structure of a silicon oxide film, a polycrystalline silicon film, and a silicon nitride film. Device manufacturing method. 제1항 내지 제5항 중 어느 한 항에 있어서, 상기 반도체기판은 실리콘기판으로 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.The method of manufacturing a highly integrated semiconductor device according to any one of claims 1 to 5, wherein the semiconductor substrate is made of a silicon substrate. 제4항에 있어서, 상기 임플란트 후 소스/드레인을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 고집적 반도체 소자 제조방법.5. The method of claim 4, further comprising forming a source / drain after the implant. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037517A 1994-12-27 1994-12-27 High integrated semiconductor device and the manufacturing method thereof KR0147428B1 (en)

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KR1019940037517A KR0147428B1 (en) 1994-12-27 1994-12-27 High integrated semiconductor device and the manufacturing method thereof

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KR960026570A true KR960026570A (en) 1996-07-22
KR0147428B1 KR0147428B1 (en) 1998-11-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100734651B1 (en) * 2002-12-30 2007-07-02 동부일렉트로닉스 주식회사 Method for manufacturing semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100400918B1 (en) * 2001-06-28 2003-10-10 동부전자 주식회사 Method For Manufacturing Semiconductor Devices
JP4175650B2 (en) * 2004-08-26 2008-11-05 シャープ株式会社 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100734651B1 (en) * 2002-12-30 2007-07-02 동부일렉트로닉스 주식회사 Method for manufacturing semiconductor device

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