KR940001442A

KR940001442A - Semiconductor device manufacturing method

Info

Publication number: KR940001442A
Application number: KR1019920009802A
Authority: KR
Inventors: 김학렬; 인재식; 황준; 정운재; 최용근
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-06-05
Filing date: 1992-06-05
Publication date: 1994-01-11

Abstract

반도체소자 제조방법에서, N-MOS 소자와 P-MOS 소자로 구성되는 C-MOS 소자를 제조할때, N-MOS소자와 P-MOS 소자가 확연히 구분되므로, N+소스/드레인마스크 및 P+소스/드레인 마스크를 사용하여. 식각공정을 함으로써, 종래의 포토마스크 제조공정중의 한 공정을 단축시켜서 소정의 N-MOS소자 및 P-MOS소자의 소오스 및 드레인전극을 형성할 수 있다.In the method of manufacturing a semiconductor device, when manufacturing a C-MOS device composed of an N-MOS device and a P-MOS device, the N-MOS device and the P-MOS device are clearly distinguished, so that the N + source / drain mask and P + source / Using a drain mask. By performing the etching process, one of the conventional photomask manufacturing processes can be shortened to form source and drain electrodes of predetermined N-MOS devices and P-MOS devices.

Description

Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도는 본 발명의 제1실시예에 따라 실리콘기판 상부에 게이트 산화막과 폴리 실리콘층을 증착시키고 그 상부에 실리사이드층을 증착시킨후, 포토레지스트층을 코팅시켜, N+ 소스/드레인 마스크를 형성하는 단계를 나타내는 반도체소자의 단면도, 제Ib도는 상기 N+소스/드레인 마스크를 이용하여 하부의 실리사이드층 및 폴리 실리콘층의 일부를 식 각한 후, LDD (Lightly Doped Drain) 영역을 형성하는 단계를 나타내는 반도체소자의 단면도, 제1c도는 상기 폴리실리콘층 및 실리사이드층 측벽에 스페이서 산화막을 형성한후, N+소스/드레인 이온주입하는 단계를 나타내는 반도체 소자의 단면도. 제Id도는 상기 N웰영역 상부 및 P웰영역 상부에 포토레지스트층을 코팅하여 P+소스/드레인 마스크를 형성하는 단계를 나타내는 반도체소자의 단면도 제le도는 상기 N웰영역 상부의 포토레지스트층을 이용하여 그 하부의 실리 사이드층 및 폴러실리콘층의 일부를 식각한후 P+소스/드레인 이온 주입하는 단계를 나타내는 반도체소자의 단면도, 제If도는 제le도의 공정을 완료한후 잔존 포토레지스트층을 완전 히 제거하여 형성된 반도체 소자의 단면도. 제2a도는 본 발명의 제2실시예에 따라 제 la도의 공정 이 완료된 후, 제Ib도의 공정이 완료되기전 실리사이드층 상부에 포토레지스트층이 잔존하는 상태를 나타내는 반도체소자의 단면도, 제2b도는 상기 실리사이드층 상부의 포토레지스트층을 플로우시킨후 그 상부에서 N+소스/드레인 이온주입하는 단계를 나타내는 반도체소자외 단면도 제2c도는 제2b도에서 잔존하는 포토레지스트층을 제거한후, P+소스/드레인 마스크를 형성하는 단계를 나타내는 반도체소자의 단면도 제2d도는 제2c도에 도시된 P +소스/드레인 마스크를 이용하여 그 하부의 실리사이드 층 및 실리콘충의 일부를 식각한 후 P+소스/드레인 이온주입을 나타내는 반도체 소자의 단면도. 제2e도는 제2d도의 공정 이 완료된후 잔존하는 포토레지스트층을 제거하여 형성된 반도체소자의 단면도. 제3a도는 본 발명의 제3실시예에 따라 제1실시예의 제1교도 및 Ib도에 도시된 공정이 완료된후, 폴리실리콘층 및 실리사이드층 측벽에 스페이서 산화막을 형성하는 단계를 나타내는 반도체소자의 단면도, 제3b도는 제3a도에 도시된 스페이서 산화막 상부로부터 DDD (Dooble Diffused Drain)이온주입공정을 나타내는 반도체소자의 단면도, 제3c도는 P-웰영역 및 N-웰영역 상부에 포토레지스트층을 코팅하여 P+소스/드레인 마스크를 형성하는 단계를 나타내는 반도체 소자의 단면도, 제3d도는 제3c도에 도시된 P +소스/드레인 마스크를 이용하여 그 하부의 실 리사이드 층 및 실리콘 층의 일부를 식각한 후 P +소스/드레인 이온주입하는 단계를 나타내는 반도체소자의 단면도, 제3e도는 제3d도의 공정 이 완료된후 잔존하는 포토레지스트층을 제거하여 형성된 반도체소자의단면도 .FIG. 1A illustrates a method of forming an N + source / drain mask by depositing a gate oxide film and a polysilicon layer on a silicon substrate, a silicide layer on the silicon substrate, and then coating a photoresist layer according to the first embodiment of the present invention. A cross-sectional view of a semiconductor device showing a step, and FIG. Ib illustrates a step of forming a lightly doped drain (LDD) region after etching a part of a lower silicide layer and a polysilicon layer using the N + source / drain mask. 1C is a cross-sectional view of a semiconductor device, after forming a spacer oxide film on the sidewalls of the polysilicon layer and the silicide layer, and implanting N + source / drain ions. FIG. ID is a cross-sectional view of a semiconductor device showing a step of forming a P + source / drain mask by coating a photoresist layer on the N well region and on the P well region. A cross-sectional view of a semiconductor device showing a step of implanting P + source / drain ions after etching a portion of a lower silicide layer and a polysilicon layer, and if is a completely removed photoresist layer after completing the process of FIG. Cross-sectional view of the semiconductor device formed by. FIG. 2A is a cross-sectional view of a semiconductor device showing a state in which a photoresist layer remains on the silicide layer after the process of FIG. La is completed and before the process of FIG. Ib is completed, according to the second embodiment of the present invention. FIG. After the photoresist layer is flowed on top of the silicide layer and the N + source / drain ions are implanted thereon, the cross-sectional view of FIG. 2C and FIG. 2B removes the remaining photoresist layer. FIG. 2D is a cross-sectional view of a semiconductor device showing a step of forming a semiconductor device showing P + source / drain ion implantation after etching a part of the silicide layer and silicon charges below by using the P + source / drain mask shown in FIG. Section. FIG. 2E is a cross-sectional view of a semiconductor device formed by removing a photoresist layer remaining after the process of FIG. 2D is completed. FIG. 3A is a cross-sectional view of a semiconductor device showing forming a spacer oxide film on sidewalls of a polysilicon layer and a silicide layer after completion of the processes shown in FIGS. FIG. 3B is a cross-sectional view of a semiconductor device showing a DDD (Dooble Diffused Drain) ion implantation process from the spacer oxide film shown in FIG. 3A. FIG. 3C is a photoresist layer coated on the P-well region and the N-well region. A cross-sectional view of a semiconductor device showing the step of forming a P + source / drain mask, FIG. 3D is a portion of the silicide layer and the silicon layer underneath using the P + source / drain mask shown in FIG. 3C A cross-sectional view of a semiconductor device showing a step of implanting P + source / drain ions, and FIG. 3e illustrates a semiconductor device formed by removing a photoresist layer remaining after the process of FIG. 3d is completed. Cross-section .

Claims

A method of manufacturing a semiconductor device, comprising: forming a P-well region (2) and an N-well region (3) in a silicon substrate (1), a gate oxide film (4) and polysilicon on the silicon substrate (1) Depositing layers 5 and silicide layers 6 sequentially and coating a photoresist layer 7 over the silicide layers 6 to form an N + source / drain mask

And etching one part of the lower polysilicon layer 5 and the silicide layer 6 by using the N + source / drain mask, and removing the photoresist layer 7 remaining after the etching process. Forming a shadow oxide film on the polysilicon layer (5), and forming a lightly doped drain (LDD) region by an ion implantation process from above the new oxide film. After the oxide film is formed on the silicide layer 6 and the polysilicon layer 5, an oxide film etching process is performed to form a spacer oxide film 8, annealing the entire structure, and the annealing process. After implanting the N + source / drain ions, forming a P + source / drain mask by coating a layer 9 of photoresist on the P-well region 2 and the N-well region 3; Etching a silicon layer (5) and silicide layer (6) on the N-well region (3) using a P + source / drain mask; and removing the remaining photoresist layer after the p + source / drain ion implantation process.

A method of manufacturing a semiconductor device, comprising: forming a P-well region (2) and an N-well region (3) in a silicon substrate (1), a gate oxide film (4) and polysilicon on the silicon substrate (1) Depositing a layer 5 and a silicide layer 6 sequentially, coating a photoresist layer 7 on the silicide layer 6 to form an N + source / drain mask, and the silicide layer ( 6) curing and baking the upper photoresist layer (7) and ion implanting N + source / drain quote impurities from the flowed photoresist layer (7); Completely removing the photoresist layer (7) on the silicide layer (6). Coating a photoresist layer 9 on the P-well region 2 and the N-well region 1 to form a P + source / drain mask, and polysilicon on the N-well region 1 Etching portions of the layer 5 and the silicide layer 6 using a P + source / drain mask, and removing the remaining photoresist layer after the P + source / drain ion implantation process; A semiconductor device manufacturing method.

A method of manufacturing a semiconductor device, comprising: forming a P-well region (2) and an N-well region (3) in a silicon substrate (1). Sequentially depositing a gate oxide film 4, a polysilicon layer 5, and a silicide layer 6 on the silicon substrate 1, and coating a photoresist layer 7 on the silicide layer 5. To form an N + source / drain mask

And etching a portion of the lower polysilicon layer 5 and the silicide layer 6 using the N + source / drain mask, and removing the photoresist layer 7 remaining after the etching process. After forming a shadow oxide film on the polysilicon layer (5) and forming an oxide film on the silicide layer (6) and the polysilicon layer (5), through an oxide film etching process, a spacer oxide film (8) forming, annealing the entire structure, forming a double diffusion drain (DDD) region by an N + source / drain ion implantation process after the annealing process, and the P-well region (2) and coating a photoresist layer 9 on the N-well region 3 to form a P + source / drain mask, and a polysilicon layer 5 on the N-well region 3. And a part of the silicide layer 6 is etched using a P + source / drain mask. And step, P + semiconductor device manufacturing method comprising the step of removing the remaining photoresist layer after the source / drain ion implantation process.

※ Note: The disclosure is based on the initial application.