KR100231479B1 - Method of fabricating field transistor - Google Patents

Abstract

In the method of manufacturing a field transistor according to the present invention, a first insulating film doped with an impurity of a first conductivity type is formed on a semiconductor substrate having a first conductivity type region and a second conductivity type region, and on the first insulating layer. Forming a second insulating film having a different etching selectivity sequentially and patterning the first and second insulating films so as to remain only on the first conductivity type region of the semiconductor substrate; and forming the first and second insulating films on the semiconductor substrate. Forming a third insulating film doped with a second conductivity type impurity so as to cover the third insulating film, and patterning the third insulating film to remain only on the second conductive type region of the semiconductor substrate; And forming a fourth insulating film on the semiconductor substrate on which the first and third insulating films are formed, and forming an interface between the first and third insulating films and the first and second conductive regions. Patterning the fourth insulating film to remain on the substrate to form a gate insulating film and a field insulating film, and depositing polysilicon doped with impurities to cover the gate insulating film and the field insulating film, and patterning the patterned so as to remain only on the gate insulating film. And forming sidewalls on the sidewalls of the gate, and forming source and drain regions in the first and second conductivity-type regions using the gate and the sidewalls as masks, respectively, to define channel regions and And diffusing the doped impurities in the third insulating film into the channel region between the source and drain regions. Therefore, the field transistor manufacturing method according to the present invention forms a thick insulating film on an insulating film doped with a conductive type impurity such as a thin substrate as a gate insulating film and another thick insulating film on an insulating film doped with a conductive type impurity such as the substrate. Impurity doped in the thin insulating film by the process is diffused in the channel region to increase the concentration of impurities, even if the channel length is reduced by reducing the size of the unit device to prevent the punch-through phenomenon.

Description

Manufacturing method of field transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field transistor, and more particularly, to a method of manufacturing a field transistor which can prevent punch-through even if the channel length is reduced by the size of a unit device.

In general, field transistors for high voltage, high current, and erase operation field transistors around a flash memory are manufactured by increasing the threshold voltage by making the gate insulating layer as thick as the thickness of the field insulating layer. Use

As semiconductor devices are highly integrated, the size of unit devices, in particular, the size of transistor devices, becomes finer, thereby increasing the degree of integration.

1A to 1D are flowcharts illustrating a method of manufacturing a field transistor according to an exemplary embodiment of the prior art.

According to the prior art, as illustrated in FIG. 1A, P-type 13 is formed by selectively ion-implanting P-type impurities into a predetermined portion of the N-type semiconductor substrate 11. Then, an insulating layer 14 is formed by thickly depositing silicon oxide on the N-type semiconductor substrate 11 on which the P well 13 is formed by chemical vapor deposition (CVD). After the photoresist is applied on the insulating layer 14, the photoresist is exposed and developed to remain only at the interface between the P well 13 and the N-type semiconductor substrate 11 formed on the surface and between the intermediate portions of each interface. The first mask pattern 15 is formed.

1B, the insulating film 14 is selectively removed using the first mask pattern 15 as a mask. At this time, the insulating film 14 remaining on the interface between the P well 13 and the N-type semiconductor substrate 11 formed on the surface becomes a field insulating film 17 which defines an active region, and each of the field insulating films 17 The insulating film 14 remaining between the layers becomes the gate insulating film 19. After the impurity doped polysilicon layer 20 is formed on the semiconductor substrate 11 so as to cover the field insulating layer 17 and the gate insulating layer 19 by applying a photoresist, The second mask pattern 21 is formed so as to remain only on the gate insulating layer 19 by exposure and development.

As shown in FIG. 1C, the polysilicon layer 20 is patterned to remain on the gate insulating layer 19 using the second mask pattern 21 as a mask to define the gate 23, and the second mask pattern 21 is formed. ). Then, after thickly depositing silicon oxide or the like on the semiconductor substrate 11 on which the gate 23 is formed by a CVD method, a side-wall is formed on the side of the gate 23 through an etch-back process. (25).

As shown in FIG. 1D, N-type impurities are selectively implanted into the P well 13 and P-type impurities are selectively implanted into the N-type semiconductor substrate 11 using the gate 23 and the sidewall 25 as masks. The first impurity region 27 of the type and the second impurity region 29 of the P type are formed.

As described above, the field transistor according to the prior art defines a gate by forming a thick gate insulating film and depositing and patterning polysilicon on the gate insulating film. After forming sidewalls on the sidewalls of the gate, field transistors were fabricated by a method of selectively implanting ions using the gate and the sidewalls as a mask to form impurity regions.

However, the field transistor manufactured according to the related art has a problem in that punch-through is easily generated because the channel length of the transistor is reduced as the size of the unit device decreases due to high integration.

Accordingly, an object of the present invention is to provide a method for manufacturing a field transistor that can prevent the punch-through phenomenon without increasing the gap between the source and the drain.

A method of manufacturing a field transistor according to the present invention for achieving the above object is to form a first insulating film doped with impurities of a first conductivity type on a semiconductor substrate having a first conductivity type region and a second conductivity type region, Sequentially forming a second insulating film having a different etching selectivity on the first insulating film and patterning the first and second insulating films so as to remain only on the first conductivity type region of the semiconductor substrate; Forming a third insulating film doped with an impurity of a second conductivity type to cover the first and second insulating films, and patterning the third insulating film to remain only on the second conductive type region of the semiconductor substrate; Removing a second insulating film on the semiconductor substrate; and forming a fourth insulating film on the semiconductor substrate on which the first and third insulating films are formed, and forming the first and third insulating films on the first and third insulating films. Patterning the fourth insulating film to remain on the interface of the second conductive region to form a gate insulating film and a field insulating film, and depositing polysilicon doped with impurities to cover the gate insulating film and the field insulating film and remaining only on the gate insulating film. Forming a sidewall on the side surface of the gate after patterning to define the gate; and defining a channel region by forming source and drain regions in the first and second conductive regions using the gate and the sidewall as masks, respectively. And simultaneously dispersing impurities doped in the first and third insulating layers to the channel region between the source and drain regions.

1A to 1D are process diagrams illustrating a method of manufacturing a field transistor according to an embodiment of the prior art.

2A to 2F are process drawings showing a method of manufacturing a field transistor according to the embodiment of the present invention.

<Simple explanation of the code | symbol about the main part of drawing>

31: N-type semiconductor substrate 33: P well

35: BSG 41: PSG

46: field insulating film 47: gate insulating film

51: gate 53: sidewall

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are process diagrams illustrating a method of manufacturing a field transistor according to an embodiment of the present invention.

According to this method, as shown in Fig. 2A, P-type 33 is formed by selectively implanting P-type impurities into a predetermined portion in the N-type semiconductor substrate 31. After the first insulating film 35 and the second insulating film 37 are sequentially formed by the CVD method on the semiconductor substrate 31 on which the P well 33 is formed, a photo on the second insulating film 37 is formed. After applying the resist, it is exposed and developed to form the first mask pattern 39 so that the first and second insulating films 35 and 37 remain only on the P well 33. Here, the first insulating layer 35 is formed of an insulating material doped with a P-type impurity, for example, boron-silicate glass (hereinafter referred to as BSG), and the second insulating layer 37 The silver is formed of an insulating material having a different etching selectivity from the silicate glass such as BSG or the like forming the first insulating film 35, for example, silicon oxide or silicon nitride.

As shown in FIG. 2B, after the first insulating layer 37 and the first insulating layer 35 are sequentially anisotropically dry-etched using the first mask pattern 39 as a mask, only the P well 33 is left. The first mask pattern 41 is removed. A third insulating film 41 is formed on the patterned first and second insulating films 35 and 37 and the exposed semiconductor substrate 31 by a CVD method. After the photoresist is applied on the third insulating film 41, the photomask is exposed and developed to expose the second mask pattern on the portion where the first and second insulating films 35 and 37 of the semiconductor substrate 31 are not formed. To form 43. The third insulating film 41 is formed of an insulating material doped with N-type impurities, for example, Phospho-Silicate Glass (hereinafter, referred to as PSG).

As shown in FIG. 2C, the third insulating film 41 is patterned using the second mask pattern 43 as a mask. Since the second insulating film 37 has an etching selectivity different from that of the first and third insulating films 35 and 41, when the third insulating film 41 is patterned, the second insulating film 37 is formed of the first insulating film 35. ) Is protected from etching. After the second mask pattern 43 is removed, the second insulating film 37 remaining on the first insulating film 35 is selectively removed.

Thereafter, silicon oxide is thickly deposited by CVD to cover the first and third insulating films 35 and 41 on the semiconductor substrate 31 to form a fourth insulating film 44, and the fourth insulating film 44 After the photoresist is applied onto the photoresist, the photoresist is exposed and developed to form portions corresponding to the first and third insulating layers 35 and 41 and the interface portions of the P well 33 and the N-type semiconductor substrate 31 formed on the surface thereof. The third mask pattern 45 is formed to remain in the.

As shown in FIG. 2D, the fourth insulating layer 44 is selectively removed using the third mask pattern 45 as a mask. At this time, the fourth insulating film 44 remaining on the interface between the P well 33 and the N-type semiconductor substrate 31 formed on the surface becomes the field insulating film 46 defining the active region. The third insulating films 35 and 41 and the fourth insulating film 44 remaining on the first and third insulating films 35 and 41 become the gate insulating film 47.

Next, a polysilicon layer 48 doped with impurities by a CVD method is formed on the semiconductor substrate 31 so as to cover the field insulating film 46 and the gate insulating film 47. Then, a photoresist is applied on the polysilicon layer 48, and the fourth mask pattern 49 is formed to expose only the portion corresponding to the gate insulating layer 47 by exposing and developing the photoresist.

As shown in FIG. 2E, after the gate layer 51 is formed by selectively anisotropically etching the polysilicon layer 48 using the fourth mask pattern 49 as a mask, the fourth mask pattern 49 is formed. Remove Then, a thick silicon oxide is deposited on the semiconductor substrate 31 on which the gate 51 is formed by a CVD method, followed by an etch back process to form sidewalls 53 on the side surfaces of the gate 51.

Next, as shown in FIG. 2F, N-type impurities are selectively implanted into the P well 33 and P-type impurities are selectively implanted into the N-type semiconductor substrate 31 using the gate 51 and the sidewall 53 as a mask. Thereafter, the implanted ions are annealed to diffuse, thereby forming respective N-type first impurity regions 55 and P-type second impurity regions 57. The first impurity region 55 and the second impurity region 57 are used as channel regions, and ion implantation and implantation are performed to form the first and second impurity regions 55 and 57. When annealing to diffuse ions, doped impurities of the BSG layer and the PSG layer used as the first and third insulating layers 35 and 41 are transferred to the channel region of the P well 33 and the N-type semiconductor substrate 31. Diffusion increases the concentration of impurities.

As described above, the field transistor manufactured according to the present invention forms a BSG layer doped with P-type impurities on the P wells, and a PSG layer doped with N-type impurities on the N wells when the gate insulating layer is formed. A thick insulating film is further formed on the BSG and PSG, and boron (B) of the BSG layer and phosphorus (P) of the PSG layer diffuse in the channel region of the N-type semiconductor substrate and the P well by heat during the subsequent process. In this way, the punch-through phenomenon is prevented by increasing the impurity concentration.

Therefore, the field transistor manufacturing method according to the present invention forms a thick insulating film on an insulating film doped with a conductive type impurity such as a thin substrate as a gate insulating film and another thick insulating film on an insulating film doped with a conductive type impurity such as the substrate. Impurity doped in the thin insulating film by the process is diffused in the channel region to increase the concentration of impurities, even if the channel length is reduced by reducing the size of the unit device to prevent the punch-through phenomenon.

Claims (3)

A first insulating layer doped with an impurity of a first conductivity type is formed on a semiconductor substrate having a first conductivity type region and a second conductivity type region, and a second insulating layer having a different etching selectivity is sequentially formed on the first insulating layer. Thereafter, patterning the first and second insulating films so as to remain only on the first conductivity type region of the semiconductor substrate; Forming a third insulating layer doped with a second conductivity type impurity to cover the first and second insulating layers on the semiconductor substrate, and patterning the third insulating layer to remain only on the second conductivity type region of the semiconductor substrate; Fair, Removing a second insulating film on the first insulating film; Forming a fourth insulating film on the semiconductor substrate on which the first and third insulating films are formed, and patterning the fourth insulating film to remain on the interface between the first and third insulating films and the first and second conductive regions. Defining a field insulating film; Depositing polysilicon doped with impurities so as to cover the gate insulating film and the field insulating film, and patterning the doped polysilicon to remain only on the gate insulating film to define a gate and to form sidewalls on the side of the gate; Source and drain regions are formed in the first and second conductivity-type regions, respectively, using the gate and sidewalls as masks to define channel regions, and at the same time, impurities doped in the first and third insulating layers are transferred to the source and drain regions. A method of manufacturing a field transistor, comprising the step of diffusing into a channel region therebetween. The method of manufacturing a field transistor according to claim 1, wherein the first insulating film is formed of PSG and the third insulating film is formed of BSG. The method of manufacturing a field transistor according to claim 1, wherein the gate insulating film is formed thick by a CVD method.

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