KR970030792A - Manufacturing method of CMOS device - Google Patents

Manufacturing method of CMOS device Download PDF

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KR970030792A
KR970030792A KR1019950043563A KR19950043563A KR970030792A KR 970030792 A KR970030792 A KR 970030792A KR 1019950043563 A KR1019950043563 A KR 1019950043563A KR 19950043563 A KR19950043563 A KR 19950043563A KR 970030792 A KR970030792 A KR 970030792A
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source
ion implantation
manufacturing
insulating film
cvd insulating
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KR0179860B1 (en
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이상돈
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문정환
엘지반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

본 발명의 씨모스(CMOS) 소자의 제조방법은, 활성영역과 비활성영역을 정의하기 위한 필드산화막을 형성하는 공정과, 상기 필드산화막이 형성된 반도체 기판 위에 게이트 산화막을 성장시킨 후 그 위에 다결정실리콘층과 제1 CVD 절연막을 순차증착시키고 상기 다결정 실리콘층 및 제1 CVD 절연막을 동일한 패턴으로 패터닝하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극 형성 후 결과물 전면에 제2, 제3 CVD 절연막을 증착시키는 공정과, 엔모스 소스／드레인 마스크를 형성하고 이를 적용하여 상기 제3 CVD 절연막을 식각한 후 n+소스／드레인 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 적용하여 상기 제2 CVD 절연막을 식각한 후 n-LDD 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 제거하고, 피모스 소스／드레인 마스크를 형성하여 이를 적용하여 제3절연막을 통해 직접 p+소스／드레인 이온주입하는 공정과, 상기 제3 CVD 절연막을 식각한 후 p-LDD 이온주입하는 공정과, 제2 CVD 절연막을 식각한 후 n Halo 이온주입하는 공정 및 상기 피모스의 소스／드레인 마스크를 제거하는 공정을 포함하여 이루어지며, 종래의 측벽스페이서를 사용한 LDD 엔모스／피모스 제조시에 비해 마스크 수를 절반으로 감소시킴으로써 제조가 절감과 함께 상기 마스크를 형성하기 위한 사진 식각공정으로 인한 오염을 방지할 수 있으며, 피모스의 LDD이온주입을 게이트 가장자리에서 일정거리만큼 떨어지게 하여 p-와 p+영역의 보론이 확산되도록 하고, Halo 이온주입도 상기 엔모스와 피모스가 각각 다른 간격으로 실시함으로써 동일 피모스의 SCE 특성이 엔모스의 특성보다 나빠지는 것을 방지할 수 있으며, 상기 측벽스페이서를 형성하기 위해 식각되는 절연막을 다층화하여 CVD 질화막 또는 CVD 산화막이 되게 함으로써 상기 측벽스페이서 형성을 위한 절연막 식각시 필드산화막이 과다하게 식각되는 것을 방지하여 소자분리특성이 저하되는 것을 최소화할 수 있는 효과가 있다.The method of manufacturing a CMOS device of the present invention includes forming a field oxide film for defining an active region and an inactive region, growing a gate oxide film on a semiconductor substrate on which the field oxide film is formed, and then forming a polysilicon layer thereon. And depositing a first CVD insulating film sequentially and patterning the polycrystalline silicon layer and the first CVD insulating film in the same pattern to form a gate electrode, and depositing second and third CVD insulating films on the entire surface of the resultant after forming the gate electrode. Forming an NMOS source / drain mask and etching the third CVD insulating film to apply n + source / drain ion implantation; and applying the NMOS source / drain mask to the second CVD insulating film. after etching the n - LDD ion implantation step of the, and wherein the NMOS source / drain removing the mask, the PMOS source / drain mask Formed by the steps of first injecting directly p + source / drain ion over the third insulating film by applying it, and then etching the first three-CVD insulating film p - after etching the LDD ion implantation step, the 2 CVD insulating film n Halo It includes the process of ion implantation and the process of removing the source / drain mask of the PMOS, the manufacturing cost is reduced by halving the number of masks compared with the conventional LDD NMOS / PMOS fabrication using sidewall spacers. Contamination due to the photolithography process for forming the mask can be prevented together, and the LDD ion implantation of PMOS is separated by a certain distance from the gate edge so that boron in p - and p + regions can be diffused, and Halo ion implantation is performed. Also, since the NMOS and the PMOS are performed at different intervals, the SCE characteristic of the same PMOS can be prevented from being worse than that of the NMOS. The insulating layer to be etched to form the sidewall spacers may be multilayered to become a CVD nitride film or a CVD oxide film to prevent excessive etching of the field oxide layer during the etching of the insulating film for forming the sidewall spacers, thereby degrading device isolation characteristics. There is an effect that can be minimized.

Description

씨모스(CMOS) 소자의 제조방법Manufacturing method of CMOS device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 씨모스(CMOS) 소자의 제1실시예의 제조방법을 도시한 단면도.3 is a cross-sectional view showing the manufacturing method of the first embodiment of the CMOS device according to the present invention.

Claims (15)

활성영역과 비활성영역을 정의하기 위한 필드산화막을 형성하는 공정과, 상기 필드산화막이 형성된 반도체 기판 위에 게이트 산화막을 성장시킨 후 그 위에 다결정실리콘층과 제1 CVD 절연막을 순차증착시키고 상기 다결정 실리콘층 및 제1 CVD 절연막을 동일한 패턴으로 패터닝하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극 형성 후 결과물 전면에 제2, 제3 CVD 절연막을 증착시키는 공정과, 엔모스 소스／드레인 마스크를 형성하고 이를 적용하여 상기 제3 CVD 절연막을 식각한 후 n+소스／드레인 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 적용하여 상기 제2 CVD 절연막을 식각한 후 n-LDD 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 제거하고, 피모스 소스／드레인 마스크를 형성하여 이를 적용하여 제3절연막을 통해 직접 p+소스／드레인 이온주입하는 공정과, 상기 제3 CVD 절연막을 식각한 후 p-LDD 이온주입하는 공정과, 제2 CVD 절연막을 식각한 후 n Halo 이온주입하는 공정 및 상기 피모스의 소스／드레인 마스크를 제거하는 공정을 포함하여 이루어 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.Forming a field oxide film for defining an active region and an inactive region, growing a gate oxide film on the semiconductor substrate on which the field oxide film is formed, and sequentially depositing a polycrystalline silicon layer and a first CVD insulating film thereon, and forming the polycrystalline silicon layer; Forming a gate electrode by patterning a first CVD insulating film in the same pattern, depositing second and third CVD insulating films on the entire surface of the resultant after forming the gate electrode, forming an NMOS source / drain mask, and applying the same N + source / drain ion implantation after etching the third CVD insulating film, n - LDD ion implantation after etching the second CVD insulating film by applying the NMOS source / drain mask, and The NMOS source / drain mask is removed, and a PMOS source / drain mask is formed and applied thereto to pass through the third insulating film. Direct p + source / drain ion implantation process, and the third after etching the CVD insulating film p for - LDD ion injection etching step of claim 2 CVD insulating film after n Halo ion implantation process and a source of the PMOS which / The manufacturing method of the CMOS element characterized by including the process of removing a drain mask. 제1항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은 게이트 전극 형성 한 후 제2 CVD 절연막을 증착시키기 전에 게이트 전극 전면에 산화막을 형성하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 1, wherein the manufacturing method of the CMOS device further comprises forming an oxide film on the entire surface of the gate electrode after forming the gate electrode and before depositing the second CVD insulating film. (CMOS) Device manufacturing method. 제1항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, n-LDD 이온주입 후 엔모스의 소스／드레인 마스크를 제거하기 전에 p Halo 이온주입하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 1, wherein the CMOS device manufacturing method further comprises a step of implanting p Halo after n − LDD ion implantation before removing the source / drain mask of the NMOS. Method of manufacturing CMOS device. 제1항에 있어서, 상기 제2／제3 CVD 절연막을 산화막／질화막, 질화막／산화막, 산화막／다결정실리콘층 및 질화막／다결정실리콘층 중 어느 하나임을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of manufacturing a CMOS device according to claim 1, wherein the second / third CVD insulating film is any one of an oxide film / nitride film, a nitride film / oxide film, an oxide film / polycrystalline silicon layer, and a nitride film / polycrystalline silicon layer. . 제1항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, 상기 엔모스의 소스／드레인 마스크를 제거한 후 p+소스 드레인 이온주입 전에 n-LDD 이온주입하고 열처리하는 하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 1, wherein the manufacturing method of the CMOS device further includes performing n - LDD ion implantation and heat treatment after removing the source / drain mask of the NMOS before p + source drain ion implantation. A method of manufacturing a CMOS device, characterized in that made. 제1항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, 상기 제3 CVD 절연막 식각 후 p-LDD이온주입 전에 제2 CVD 절연막을 식각하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 1, wherein the manufacturing method of the CMOS device further comprises etching the second CVD insulating film after etching the third CVD insulating film and before p - LDD ion implantation. (CMOS) Device manufacturing method. 제1항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, n Halo 이온주입 후 열처리하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 1, wherein the manufacturing method of the CMOS device further comprises a step of performing heat treatment after n Halo ion implantation. 활성영역과 비활성영역을 정의하기 위한 필드산화막을 형성하는 공정과, 상기 필드산화막이 형성된 반도체 기판 위에 게이트 산화막을 성장시킨 후 그 위에 다결정실리콘층과 제1 CVD 절연막을 증착시키고 상기 다결정 실리콘층 및 제1 CVD 절연막을 동일한 패턴으로 패터닝하여 게이트 전극을 형성하는 공정과, 상기 게이트 전극 형성 후 결과물 전면에 제2, 제3 및 제4 CVD 절연막을 순차적층시키는 공정과, 엔모스 소스／드레인 마스크를 형성하고 이를 적용하여 상기 제4 CVD 절연막을 식각한 후 n+소스／드레인 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 적용하여 상기 제3 CVD 절연막을 식각한 후 n-LDD 이온주입하는 공정과, 상기 엔모스 소스／드레인 마스크를 제거하고, 피모스 소스／드레인 마스크를 형성하고 이를 적용하여 제4절연막을 통해 직접 p+소스／드레인 이온주입하는 공정과, 상기 제4, 제3, 제2 CVD 절연막을 식각한 후 p-LDD 이온주입하는 공정과, 제2 CVD 절연막을 식각한 후 상기 피모스의 소스／드레인 마스크를 제거하는 공정을 포함하여 이루어진 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.Forming a field oxide film for defining an active region and an inactive region, growing a gate oxide film on the semiconductor substrate on which the field oxide film is formed, depositing a polysilicon layer and a first CVD insulating film thereon, and depositing the polycrystalline silicon layer and A process of forming a gate electrode by patterning a CVD insulating film in the same pattern, sequentially forming second, third and fourth CVD insulating films on the entire surface of the resultant after forming the gate electrode, and forming an NMOS source / drain mask N + source / drain ion implantation after etching the fourth CVD insulating film by applying the same, and n − LDD ion implantation after etching the third CVD insulating film by applying the NMOS source / drain mask Removes the NMOS source / drain mask, forms a PMOS source / drain mask, and applies the fourth insulating layer A p + source / drain ion implantation step, directly through the fourth, third, then second etch the CVD insulating film p - in then etching the LDD ion implantation step and the second CVD insulating film for the PMOS A method for manufacturing a CMOS device, comprising the step of removing a source / drain mask. 제8항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은 게이트 전극 형성 후 제2 CVD 절연막을 증착시키기 전에 게이트 전극 전면에 산화막을 형성하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 8, wherein the method of manufacturing the CMOS device further comprises forming an oxide film on the entire surface of the gate electrode after the gate electrode is formed and before the second CVD insulating film is deposited. CMOS) device manufacturing method. 제8항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, n-LDD 이온주입 후 엔모스의 소스／드레인 마스크를 제거하기 전에 p Halo 이온주입하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.9. The method of claim 8, wherein the CMOS device manufacturing method further comprises a step of implanting p Halo after n − LDD ion implantation and before removing the source / drain mask of the NMOS. Method of manufacturing CMOS device. 제8항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, p-LDD 이온주입 후 피모스 소스／드레인 마스크를 제거하기 전에 n Halo 이온주입하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method according to claim 8, wherein the CMOS device manufacturing method further comprises a step of implanting n Halo ion after p − LDD ion implantation and before removing the PMOS source / drain mask. Manufacturing method of MOS device. 제8항에 있어서, 상기 제2／제3／제4 CVD 절연막을 질화막／산화막／질화막, 산화막／질화막／산화막, 질화막／다결정실리콘층／질화막 및 산화막／다결정 실리콘층／산화막 중 어느 하나임을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The method of claim 8, wherein the second, third, and fourth CVD insulating films are any one of a nitride film, an oxide film, a nitride film, an oxide film, a nitride film, an oxide film, a nitride film, a polycrystalline silicon layer, a nitride film, and an oxide film, a polycrystalline silicon layer, and an oxide film. A method of manufacturing a CMOS device. 제8항에 있어서, 상기 씨모스(CMOS) 소자의 제조방법은, 상기 엔모스의 소스／드레인 마스크를 제거한 후 p+소스／드레인 이온주입 전에 열처리하는 공정을 더 포함하여 이루어지는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.9. The method of claim 8, wherein the method of manufacturing the CMOS device further comprises a step of removing the source / drain mask of the NMOS and then performing heat treatment before p + source / drain ion implantation. Manufacturing method of MOS device. 제10항에 있어서, 상기 n-LDD 이온주입 및 p Halo이온주입공정은 엔모스 소스／드레인 마스크를 적용하여 상기 제3 CVD 절연막을 식각한 후 순차적으로 실시하는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The CMOS method of claim 10, wherein the n - LDD ion implantation and the p Halo ion implantation process are performed sequentially after etching the third CVD insulating layer by applying an NMOS source / drain mask. Method of manufacturing the device. 제10항에 있어서, 상기 n-LDD 이온주입 및 p Halo 이온주입공정은 엔모스 소스／드레인 마스크를 적용하여 상기 제3, 제2 CVD 절연막을 식각한 후 순차적으로 실시하는 것을 특징으로 하는 씨모스(CMOS) 소자의 제조방법.The CMOS method of claim 10, wherein the n - LDD ion implantation and the p Halo ion implantation process are performed sequentially after etching the third and second CVD insulating layers by applying an NMOS source / drain mask. (CMOS) Device manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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