KR100823451B1 - Semiconductor device and method of manufacturing the semiconductor device - Google Patents

Abstract

A semiconductor device and a fabricating method thereof are provided to make characteristics of a transistor uniform by improving a process of forming a spacer when a polysilicon gate is formed. A gate oxide layer pattern(20) is formed on a semiconductor substrate(10), and a polysilicon pattern(30) is formed on the gate oxide layer pattern. A first gate spacer(40) has a first spacer pattern(42) formed at both sidewalls of the polysilicon pattern at a height lower than an upper surface of the polysilicon pattern and a second spacer pattern(44) formed at both sidewalls of the polysilicon pattern at the same height as the upper surface of the polysilicon pattern. A second gate spacer(50) is disposed at both sidewalls of the first gate spacer, and a gate silicide pattern(60) is formed on the upper surface of the polysilicon pattern.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having improved electrical characteristics of the semiconductor device and a manufacturing method thereof.

Recently, with the development of technology in the field of semiconductor devices, semiconductor devices such as transistors having finer dimensions have been developed. In particular, various methods have recently been proposed for implementing shallow junctions in low voltage MOSFET transistors having dimensions of 90 nm or less. Conventionally, a method such as spike RTP or laser annealing is used to implement a shallow junction in a low voltage MOSFET transistor. In addition, when using an offset spacer using a TEOS film of 20 nm or less in a low voltage MOSFET transistor, there is a problem in that the characteristics of the low voltage MOSFET transistor are greatly changed due to the thickness uniformity problem of the TEOS film.

Accordingly, an aspect of the present invention is to provide a semiconductor device in which a process of forming a spacer when forming a polysilicon gate is improved to uniformly implement characteristics of a transistor in a wafer.

Another object of the present invention is to provide a manufacturing process of the semiconductor device.

A semiconductor device for realizing one object of the present invention is a gate oxide film pattern formed on a semiconductor substrate, a polysilicon pattern formed on the gate oxide pattern, and both sidewalls of the polysilicon pattern than the upper surface of the polysilicon pattern. A first gate spacer including a lower first spacer pattern, a second spacer pattern formed on both sidewalls of the polysilicon pattern, the same as an upper surface of the polysilicon pattern, and a second gate spacer disposed on both sidewalls of the first gate spacer The gate spacer may include a gate silicide pattern disposed on an upper surface of the polysilicon pattern.

In addition, a method of manufacturing a semiconductor device for implementing another object of the present invention comprises the steps of forming a gate oxide film and a polysilicon layer on a semiconductor substrate, patterning the gate oxide film and the polysilicon layer to form a preliminary gate structure Forming an oxide layer on the semiconductor substrate with a thickness lower than a height of the polysilicon pattern with the photoresist pattern formed thereon, and removing the photoresist pattern to form an oxide layer pattern on the oxide layer pattern. Forming a nitride film pattern having a height equal to that of a polysilicon pattern, patterning the nitride film pattern and the oxide pattern to form a multilayer first gate spacer on a side surface of the polysilicon pattern, and inclining ions on the semiconductor substrate The lower side of the first gate spacer Forming a low concentration source and a low concentration drain on the second gate spacer; forming a second gate spacer on a side surface of the first gate spacer; Forming a high concentration drain, a high concentration source, and forming a silicide on an upper surface of the polysilicon;

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Semiconductor device

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device 100 may include a semiconductor substrate 10, a gate oxide layer pattern 20, a polysilicon pattern 30, a first gate spacer 40, a second gate spacer 50, and a gate. Silicide pattern 60.

In this embodiment, the semiconductor substrate 10 includes a silicon wafer, for example, the semiconductor substrate 10 is a P-type semiconductor substrate that is lightly doped with P-type impurities.

The gate oxide pattern 20 may be formed on the semiconductor substrate 10, and the gate oxide pattern 20 may be a silicon oxide layer.

Meanwhile, in the semiconductor substrate 10 corresponding to the lower portion of the gate oxide pattern 20, a low concentration source 12 and a low concentration source are formed by implanting N-type impurities at a low concentration so as to form an LDD structure. The high concentration source 13 bonded to the (12), the low concentration drain 14 formed by the low concentration ion implantation of N-type impurities, and the high concentration drain 15 bonded to the low concentration drain 14 by the high concentration ion implantation, Include.

The polysilicon pattern 30 is formed on the gate oxide layer pattern 20, and the polysilicon pattern 30 includes polysilicon.

The first gate spacer 40 is disposed on sidewalls of the gate oxide layer pattern 20 and the polysilicon pattern 30, respectively. In the present embodiment, the first gate spacer 40 includes a first spacer pattern 42 and a second spacer pattern 44.

The first spacer pattern 42 is disposed on both sidewalls of the polysilicon pattern 30, and the height of the first spacer pattern 42 has a height lower than that of the polysilicon pattern 30. In the present embodiment, the first spacer pattern 42 is an oxide film containing an oxide.

The second spacer pattern 44 is disposed on both sidewalls of the polysilicon pattern 30, and is disposed on the top surface of the first spacer pattern 42. In this embodiment, the height of the second spacer pattern 44 is substantially the same as the height of the polysilicon pattern 30.

In this embodiment, the width of the first gate spacer 40 disposed on either side of the polysilicon pattern 30 may be about 10 nm to about 30 nm, preferably 20 nm.

The second gate spacer 50 is disposed on the outer surface of the first gate spacer 40.

The gate silicide pattern 60 is disposed on the top surface of the polysilicon pattern 30. In the present embodiment, the gate silicide pattern 50 may be formed by heat-treating a metal disposed on the polysilicon and the polysilicon pattern 30 included in the polysilicon pattern 30. At this time, examples of the metal which reacts with polysilicon to form silicide include titanium and tungsten.

Meanwhile, a source silicide pattern 62 may be formed on the semiconductor substrate 10 corresponding to the high concentration source 13 formed on the semiconductor substrate 10, and correspond to the high concentration drain 15 formed on the semiconductor substrate 10. A drain silicide pattern 54 may be formed on the semiconductor substrate 10.

Manufacturing Method of Semiconductor Device

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2, a gate oxide layer pattern 20 and a polysilicon pattern 30 are formed on the semiconductor substrate 10.

Specifically, in order to form the gate oxide film pattern 20 and the polysilicon pattern 30, first, a gate oxide film (not shown) and a polysilicon layer (not shown) are sequentially formed on the semiconductor substrate 10.

In this embodiment, the gate oxide film may be formed by oxidizing the semiconductor substrate 10, and the polysilicon layer may be formed on the gate oxide film through a chemical vapor deposition process. In this embodiment, the thickness of the polysilicon layer may be formed to a thickness of about 100nm to about 150nm.

After the gate oxide film and the polysilicon layer are formed on the semiconductor substrate 10, a photoresist film is formed on the upper surface of the polysilicon layer, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form polysilicon. The photoresist pattern 35 is formed on the upper surface of the layer.

The polysilicon layer and the gate oxide layer are patterned using the photoresist pattern 35 as an etch mask, and as a result, the polysilicon pattern 30 and the gate oxide layer pattern 20 are formed on the semiconductor substrate 10. In this embodiment, even after the polysilicon pattern 30 and the gate oxide layer pattern 20 are formed, the photoresist pattern 35 formed on the polysilicon pattern 30 is left without being removed.

After the gate oxide layer pattern 20 and the polysilicon pattern 30 are formed on the semiconductor substrate 10, the oxide layer pattern 41 is formed on the semiconductor substrate 10 using a chemical vapor deposition process over the entire surface of the semiconductor substrate 10. ). At this time, a portion of the oxide film pattern 41 is deposited on the photoresist pattern 35, and only the oxide film pattern 41 remains on the semiconductor substrate 10 by removing the photoresist pattern 35.

Referring to FIG. 3, a nitride film (not shown) is formed on the semiconductor substrate 10 on which the oxide film pattern 41 is formed. In this embodiment, the nitride film is formed so thin that it covers the oxide film pattern 41 and the polysilicon pattern 30. Subsequently, the nitride film is patterned by a chemical mechanical polishing process using the polysilicon pattern 30 as an endpoint, so that the nitride film pattern 43 exposing the polysilicon pattern 30 is formed on the oxide film pattern 41.

Referring to FIG. 4, after the nitride film pattern 43 is formed on the oxide film pattern 41, the photoresist pattern 46 is formed on the nitride film pattern 43.

The photoresist pattern 46 is formed to be somewhat wider than the width of the polysilicon pattern 30.

Subsequently, the nitride layer pattern 43 is patterned using the photoresist pattern 46 as an etch mask to form a second spacer pattern 44 on the oxide layer pattern 41.

Referring to FIG. 5, the oxide layer pattern 41 is patterned by a dry etching process so that the first spacer pattern 42 is formed under the second spacer pattern 44 to form the first gate spacer 40.

Referring to FIG. 6, after the first spacer pattern 42 is formed, the photoresist pattern 46 covering the first spacer pattern 42 is removed from the first spacer pattern 42.

Subsequently, ions are implanted at a low concentration on the semiconductor substrate 10 by a gradient ion implantation process to form a low concentration source 12 and a low concentration drain 14 on both sides of the polysilicon pattern 30.

Referring to FIG. 7, after the low concentration source 12 and the low concentration drain 14 are formed on the semiconductor substrate 10, a nitride film (not shown) is formed on the semiconductor substrate 10, and the nitride film is formed by an etch back process. The second gate spacer 50 is formed on the sidewall of the first gate spacer 40 by patterning.

Referring to FIG. 8, after the second gate spacer 50 is formed, the high concentration source 13 and the high concentration drain 15 are formed in the semiconductor substrate 10 on which the second gate spacer 50 is formed by a gradient ion implantation process. To form an LDD structure.

Subsequently, a metal layer for forming silicide is formed on the semiconductor substrate 10 and heat treated, so that the gate silicide 60 is formed on the upper surface of the polysilicon pattern 30, the source silicide 62 is formed on the high concentration source 13, and the high concentration drain is formed. A high concentration silicide 64 is formed in the semiconductor device.

As described in detail above, the electrical characteristics of the transistor are improved by improving the gate spacer for improving the characteristics of the transistor.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (5)

A gate oxide film pattern formed on the semiconductor substrate; A polysilicon pattern formed on the gate oxide pattern; A first gate pattern formed on both sidewalls of the polysilicon pattern to be lower than an upper surface of the polysilicon pattern, and a first gate including a second spacer pattern formed on both sidewalls of the polysilicon pattern to be the same as the top surface of the polysilicon pattern Spacers; Second gate spacers disposed on both sidewalls of the first gate spacer; And A semiconductor device comprising a gate silicide pattern disposed on an upper surface of the polysilicon pattern. The semiconductor device of claim 1, wherein a low concentration source, a high concentration source, a low concentration drain, and a high concentration drain are disposed in the semiconductor substrate corresponding to the lower portion of the gate oxide layer pattern. The semiconductor device of claim 2, wherein a source silicide pattern is disposed in the high concentration source, and a drain silicide pattern is disposed in the high concentration drain. The semiconductor device of claim 1, wherein a width of the first gate spacer disposed on one side of the polysilicon pattern is 10 nm to 30 nm. Forming a gate oxide film and a polysilicon layer on the semiconductor substrate; Forming a photoresist pattern on the polysilicon layer and etching the gate oxide layer and the polysilicon layer using the photoresist pattern as a mask to form a gate oxide pattern and a polysilicon pattern; Forming an oxide film on the semiconductor substrate with a thickness lower than a height of the polysilicon pattern while the photoresist pattern is formed; Removing the photoresist pattern to form an oxide film pattern; Forming a nitride film pattern on the oxide film pattern at the same height as that of the polysilicon pattern; Patterning the nitride layer pattern and the oxide layer pattern to form a multilayer first gate spacer on side surfaces of the polysilicon pattern; Implanting ions into the semiconductor substrate inclinedly to form a low concentration source and a low concentration drain under the first gate spacer; Forming a second gate spacer on a side of the first gate spacer; Implanting ions into the semiconductor substrate at an angle to form a high concentration source and a high concentration drain under the second gate spacer; And Forming a silicide on the high concentration drain, the high concentration source, and the polysilicon top surface.

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