KR100734142B1 - Semiconductor device and method of manufacturing the semiconductor device - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to enhance electrical properties of a transistor by using an improved silicide process which does not have an effect on a gate oxide layer. A semiconductor device includes a gate oxide pattern(20) on a semiconductor substrate(10), a polysilicon pattern(30) on the gate oxide pattern, a first gate spacer, a gate silicide pattern, and a second gate spacer. The first gate spacer(40) is formed at both sidewalls of the polysilicon pattern. The first gate spacer is higher than the polysilicon pattern. The gate silicide pattern(50) is formed on the polysilicon pattern and the first gate spacer. The second gate spacer(60) is formed at lateral portions of the gate silicide pattern and the first gate spacer.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having improved electrical characteristics of a semiconductor device using silicide and a method of manufacturing the same.

Recently, with the development of technology in the field of semiconductor devices, semiconductor devices such as transistors having finer dimensions have been developed. In particular, in recent years, development of MOSFET transistors having a dimension of 90 nm or less has been rapidly made.

However, as the size of the MOSFET transistors is gradually reduced, unexpected problems, such as an increase in resistance due to a decrease in the height of the polysilicon gate, occur.

Recently, technologies such as a fully silicide gate or a metal gate have been developed to overcome this problem. However, there are many problems to replace full silicide gates or metal gates with polysilicon gates that are currently widely used. For example, in the case of the full silicide gate, the characteristics of the gate oxide film during the process of forming the full silicide gate have a great influence, and in the case of the metal gate, metal or metal ions included in the metal gate diffuse into the gate oxide film and / or the semiconductor substrate. Has the problem.

Accordingly, the present invention provides a semiconductor device manufactured by a silicide process that does not affect the gate oxide film.

Another object of the present invention is to provide a manufacturing process of the semiconductor device.

A semiconductor device for realizing one object of the present invention is a gate oxide film pattern formed on a semiconductor substrate, a polysilicon pattern formed on the gate oxide pattern, and both sidewalls of the polysilicon pattern than the upper surface of the polysilicon pattern. A first gate spacer formed high, a gate silicide pattern disposed on an upper surface of the polysilicon pattern and an upper surface of the first gate spacer, a sidewall of the gate silicide pattern, and a second gate spacer disposed on a side of the first gate spacer Include.

In addition, a method of manufacturing a semiconductor device for realizing another object of the present invention includes forming a gate oxide pattern and a first polysilicon pattern on a semiconductor substrate, the sidewalls of the gate oxide pattern and the first polysilicon pattern Forming a first gate spacer having the same height as a top surface of the first polysilicon pattern on sidewalls, a second polysilicon pattern, a first metal pattern on the top surface of the first gate spacer and the first polysilicon pattern, and Sequentially forming a third polysilicon pattern; forming a second gate spacer surrounding sidewalls of the first gate spacer, the second polysilicon pattern, the first metal pattern, and the third polysilicon pattern; Forming a second metal layer on the semiconductor substrate to cover the top surface of the polysilicon pattern; and the first metal pattern and the second metal layer Heat treatment includes the step of forming the first polyester is such that leave the silicide portion of a silicon pattern on the gate oxide film pattern.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

Semiconductor devices Semiconductor device )

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device 100 may include a semiconductor substrate 10, a gate oxide pattern 20, a polysilicon pattern 30, a first gate spacer 40, a gate silicide pattern 50, and a second The gate spacer 60 is included.

In this embodiment, the semiconductor substrate 10 includes a silicon wafer, for example, the semiconductor substrate 10 is a P-type semiconductor substrate that is lightly doped with P-type impurities.

The gate oxide pattern 20 may be formed on the semiconductor substrate 10, and the gate oxide pattern 20 may be a silicon oxide layer.

Meanwhile, in the semiconductor substrate 10 corresponding to the lower portion of the gate oxide pattern 20, a low concentration source 12 and a low concentration source are formed by implanting N-type impurities at a low concentration so as to form an LDD structure. The high concentration source 13 bonded to the (12), the low concentration drain 14 formed by the low concentration ion implantation of the N type impurities, and the low concentration drain 15 bonded to the low concentration drain 14 by the high concentration ion implantation of the N type impurities Include.

The polysilicon pattern 30 is formed on the gate oxide layer pattern 20, and the polysilicon pattern 30 includes polysilicon.

The first gate spacer 40 is disposed on sidewalls of the gate oxide layer pattern 20 and the polysilicon pattern 30, respectively. In the present exemplary embodiment, the first gate spacer 40 has a thickness higher than the sum of the height of the gate oxide layer pattern 20 and the height of the polysilicon pattern 30. In the present embodiment, the first gate spacer 40 may have a rectangular cross section, and the width of the first gate spacer 40 may be about 10 nm to about 30 nm.

The gate silicide pattern 50 is disposed on the top surface of the polysilicon pattern 30 and the top surface of the first gate spacer 40. In the present embodiment, the gate silicide pattern 50 may be formed by heat-treating the polysilicon and the metal. At this time, examples of the metal reacting with the polysilicon include titanium, tungsten and the like.

Meanwhile, a source silicide pattern 52 may be formed on the semiconductor substrate 10 corresponding to the high concentration source 13 formed on the semiconductor substrate 10, and correspond to the high concentration drain 15 formed on the semiconductor substrate 10. A drain silicide pattern 54 may be formed on the semiconductor substrate 10.

The second gate spacer 60 covers the side surface of the first gate spacer 40 and the side surface of the gate silicide pattern 50 disposed on the top surface of the first gate spacer 40. In the present embodiment, the width of the second gate spacer 60 may be about 20 nm to about 30 nm.

The above-described semiconductor device reduces the influence of silicide on the gate oxide film when forming the silicide on the polysilicon gate, thereby preventing the deterioration of the characteristics of the semiconductor device and enabling the LDD structure to be formed more efficiently. To improve.

Manufacturing method of semiconductor device Method of Manufactruing the Semiconductor device )

2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2, a gate oxide layer pattern 20 and a first polysilicon pattern 30 are formed on the semiconductor substrate 10.

Specifically, in order to form the gate oxide film pattern 20 and the first polysilicon pattern 30, first, a gate oxide film (not shown) and a first polysilicon layer (not shown) are sequentially formed on the semiconductor substrate 10. Is formed. In this embodiment, the gate oxide layer may be formed by oxidizing the semiconductor substrate 10, and the first polysilicon layer may be formed on the gate oxide layer through a chemical vapor deposition process. In this embodiment, the thickness of the first polysilicon layer may be formed to a thickness of about 30nm to about 50nm.

After the gate oxide film and the first polysilicon layer are formed on the semiconductor substrate 10, a photoresist film is formed on an upper surface of the first polysilicon layer, and the photoresist film is formed by a photo process including an exposure process and a developing process. Patterned to form a photoresist pattern (not shown) on the upper surface of the first polysilicon layer.

The first polysilicon layer and the gate oxide layer are patterned using the photoresist pattern as an etching mask, and as a result, the first polysilicon pattern 30 and the gate oxide layer pattern 20 are formed on the semiconductor substrate 10.

3 to 5, after the gate oxide layer pattern 20 and the first polysilicon pattern 30 are formed on the semiconductor substrate 10, the first gate spacers 40 and 5 are formed on the semiconductor substrate 10. Are formed).

In order to form the first gate spacer 40, an insulating film is first formed as shown in FIG. 3. In this embodiment, the insulating film is formed by a chemical vapor deposition process, and the insulating film is formed so that the first polysilicon pattern 30 is sufficiently covered.

Next, the insulating film is planarized by a planarization process. At this time, the planarization of the insulating film is planarized by a chemical mechanical polishing (CMP) process. The top surface of the first polysilicon pattern 30 is exposed while the insulating film is planarized by the planarization process to form the insulating film pattern 42 and the insulating film pattern 42.

Referring to FIG. 4, after the insulating film pattern 42 exposing the top surface of the first polysilicon pattern 30 is formed, a sacrificial film (not shown) is formed on the top surface of the insulating film pattern 42. In the present exemplary embodiment, the sacrificial layer may be a nitride layer and is formed on the top surface of the insulating layer pattern 42 to have a thickness of about 20 nm to about 40 nm.

After the sacrificial film is formed, a photoresist film is formed on the top surface of the sacrificial film, and the photoresist film is patterned by a photo process including an exposure process and a developing process to form a photoresist pattern on the top surface of the sacrificial film.

The sacrificial layer is patterned using the photoresist pattern as an etching mask to form a sacrificial layer pattern 44 on the insulating layer pattern 42.

In plan view, the overlapping length of the sacrificial film pattern 44 and the insulating film pattern 42 with respect to the side surface of the first polysilicon pattern 30 is preferably about 20 nm to about 40 nm.

Referring to FIG. 5, after the sacrificial layer pattern 44 is formed on the insulating layer pattern 42, the insulating layer pattern 42 is etched using the sacrificial layer pattern 44 as an etching mask, thereby causing the semiconductor substrate 10 to be etched. ) Is formed on the first gate spacer 40. In this embodiment, the insulating film pattern 42 is etched by, for example, an anisotropic etching process.

Thereafter, the thin film pattern 44 disposed on the first gate spacer 40 and the first polysilicon pattern 30 is removed from the first gate spacer 40.

Referring to FIG. 6, after the first gate spacer 40 is formed, an LDD ion implantation process and a pocket ion implantation process are performed to form a shallow junction source and a drain. The LDD ion implantation process is performed at a high dose, and the pocket ion implantation process is formed to be inclined about 45 degrees to about 60 degrees with respect to the semiconductor substrate.

For this reason, low concentration source and low concentration drain are formed in each of the gate oxide film pattern 20, respectively.

7 to 9, after the low concentration source 12 and the low concentration drain 14 are formed in the semiconductor substrate 10, the second poly on the first gate spacer 40 and the first polysilicon pattern 30 is formed. The silicon pattern 52, the first metal pattern 54, and the third polysilicon pattern 56 are sequentially formed.

In order to sequentially form the second polysilicon pattern 52, the first metal pattern 54, and the third polysilicon pattern 56, a first gate spacer (not shown) may be formed on the semiconductor substrate 10 as shown in FIG. 7. 40 and a second polysilicon layer 51 covering the first polysilicon pattern 30 are formed. At this time, the thickness of the second polysilicon layer 51 is preferably about 50 nm or more.

After the second polysilicon layer 51 is formed, a high concentration of N-type impurities are implanted into the second polysilicon layer 51, and a high concentration source 13 and a high concentration drain 14 are formed on the semiconductor substrate 10, thereby providing LDD. The structure is formed.

After the LDD structure is formed, the first metal layer 53 is formed on the top surface of the second polysilicon layer 51 as shown in FIG. 8. In the present embodiment, the first metal layer 53 may be formed of titanium, tungsten, or the like, and the thickness of the first metal layer 53 is preferably 10 nm or less.

Subsequently, referring again to FIG. 8, a third polysilicon layer 55 is formed on the top surface of the first metal layer 53. In the present embodiment, the thickness of the third polysilicon layer 55 is preferably formed to about 30 nm or less. In this embodiment, the resistance of the gate structure can be greatly reduced by making the thickness of the first metal ts 53 about 10 nm or less and the thickness of the third polysilicon layer 55 about 30 nm or less.

9, a second polysilicon layer 51, a first metal layer 53, and a third polysilicon layer 55 are formed on the first gate spacer 40 and the first polysilicon pattern 30. After that, a photoresist pattern is formed on the third polysilicon layer 55 again.

Subsequently, the third polysilicon layer 55, the first metal layer 53, and the second polysilicon layer 51 are sequentially anisotropically etched using the photoresist pattern as an etching mask, and as a result, the first gate spacer 40 ) And a second polysilicon pattern 52, a first metal pattern 54, and a third polysilicon pattern 56 are formed on the first polysilicon pattern 30.

Referring to FIG. 10, after the third polysilicon pattern 56, the first metal pattern 54, and the second polysilicon pattern 52 are formed, a second gate spacer is formed on the semiconductor substrate 10 again. An insulating layer is formed, and the insulating layer is etched by an etch back process, thereby forming a second gate spacer 60 on the semiconductor substrate 10.

Referring to FIG. 11, after the second gate spacer 60 is formed, the second metal layer 58 is formed on the semiconductor substrate 10 again. In the present embodiment, the second metal layer 58 may include, for example, titanium and tungsten.

In the present embodiment, the first metal layer 53 and the second metal layer 58 may be formed of different metals or may be formed of the same metal. For example, when the first metal layer 53 includes tungsten, the second metal layer 58 may be formed of titanium. Alternatively, the first metal layer 53 and the second metal layer 58 may be formed of the same metal, for example, titanium or tungsten.

The second metal layer 58 is, for example, locally formed on the third polysilicon pattern 56, or the third polysilicon pattern 56, the high concentration source 13 and / or the semiconductor substrate 10. The high concentration drain 15 of the semiconductor substrate 10 may be formed.

Subsequently, as shown in FIG. 1, the semiconductor substrate on which the second metal layer 58 is formed is heat-treated to thereby form the second metal layer 58, the third polysilicon pattern 56, the second metal layer 58, and the semiconductor substrate ( The high concentration source 13, the second metal layer 58, and the high concentration drain 15 of the semiconductor substrate 10 react with each other. As a result, the third polysilicon pattern 56 reacts with the second metal layer 58, and a part of the second polysilicon pattern 56, the third polysilicon pattern 58, and the first polysilicon pattern 30 is formed. The silicide pattern 50 is formed by reacting with the first metal pattern 54. In this case, a portion of the first polysilicon pattern 30 may remain on the top surface of the gate oxide pattern 20 without reacting with the first metal pattern 54.

As described in detail above, the silicide process for improving the characteristics of the transistor may be improved, and thus the electrical characteristics of the transistor may be greatly improved.

Although the detailed description of the present invention has been described with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art will have the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

Claims (14)

A gate oxide film pattern formed on the semiconductor substrate; A polysilicon pattern formed on the gate oxide pattern; First gate spacers formed on both sidewalls of the polysilicon pattern higher than an upper surface of the polysilicon pattern; A gate silicide pattern disposed on an upper surface of the polysilicon pattern and an upper surface of the first gate spacer; And a second gate spacer disposed on a side of the gate silicide pattern and a side of the first gate spacer. The semiconductor device of claim 1, wherein a low concentration source, a high concentration source, a low concentration drain, and a high concentration drain are disposed in the semiconductor substrate corresponding to the lower portion of the gate oxide layer pattern. The semiconductor device of claim 2, wherein a source silicide pattern is disposed in the high concentration source, and a drain silicide pattern is disposed in the high concentration drain. The semiconductor device of claim 1, wherein a width of the first gate spacer is 10 nm to 30 nm. The semiconductor device of claim 1, wherein a width of the second gate spacer is 20 nm to 30 nm. Forming a gate oxide pattern and a first polysilicon pattern on the semiconductor substrate; Forming a first gate spacer on a sidewall of the gate oxide layer pattern and a sidewall of the first polysilicon pattern, the first gate spacer having the same height as an upper surface of the first polysilicon pattern; Sequentially forming a second polysilicon pattern, a first metal pattern, and a third polysilicon pattern on an upper surface of the first gate spacer and the first polysilicon pattern; Forming a second gate spacer surrounding sidewalls of the first gate spacer, the second polysilicon pattern, the first metal pattern, and the third polysilicon pattern; Forming a second metal layer on the semiconductor substrate to cover the top surface of the third polysilicon pattern; And And heat-treating the first metal pattern and the second metal layer to form silicide so that a portion of the first polysilicon pattern remains on the gate oxide layer pattern. The method of claim 6, wherein the forming of the gate oxide layer pattern and the first polysilicon pattern is performed. Forming a gate oxide film on the semiconductor substrate; Forming a first polysilicon layer on the gate oxide film; Forming a photoresist pattern on the first polysilicon layer; And And dry etching the first polysilicon layer and the gate oxide layer using the photoresist pattern as an etch mask. The method of claim 7, wherein the first polysilicon layer has a thickness of 30 nm to 50 nm. The method of claim 6, wherein the forming of the first gate spacer is performed. Forming an insulating film covering the first polysilicon pattern; Planarizing the insulating film to form an insulating film pattern exposing an upper surface of the first polysilicon pattern; Forming a sacrificial film on the insulating film pattern; Patterning the sacrificial layer to form a sacrificial layer pattern having a width wider than the width of the first polysilicon pattern; Etching the insulating layer pattern by dry etching using the sacrificial layer pattern as an etching mask; And Removing the sacrificial layer pattern. 10. The method of claim 9, wherein the sacrificial film is a nitride film, the thickness of the sacrificial film is 20nm to 40nm, the sacrificial film pattern and the insulating film pattern is characterized in that 20nm to 30nm overlap from both sidewalls of the first polysilicon pattern Method of manufacturing a semiconductor device. The semiconductor device of claim 6, further comprising forming a low concentration source and a low concentration drain on the semiconductor substrate by forming a first gate spacer and then implanting impurities into the semiconductor substrate. Way. The method of claim 11, wherein the inclined ion implantation angle is 45 degrees to 60 degrees with respect to the surface of the semiconductor substrate. The method of claim 6, wherein the forming of the second polysilicon pattern, the first metal pattern, and the third polysilicon pattern is performed. Forming a second polysilicon layer covering the first gate spacer on the semiconductor substrate; Implanting high concentration impurities into the semiconductor substrate; Forming a first metal layer on the second polysilicon layer; Forming a third polysilicon layer on the first metal layer; And Patterning the second polysilicon layer, the first metal layer, and the third polysilicon layer. The method of claim 6, wherein the forming of the second gate spacer is performed. Forming an insulating film covering the third polysilicon pattern on the semiconductor substrate; And And patterning the insulating film by an etch back process.

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