KR100791690B1 - Method for manufacturing in semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to suppress deterioration due to an overlap by adjusting a structure of a junction having the overlap. An insulating layer(301) and a silicon nitride are deposited on a semiconductor substrate. An SiN pattern is formed by performing an etching process using a PR pattern as a mask. An insulating layer is deposited on a part of the deposited insulating layer and the SiN pattern. An insulating layer spacer is formed by performing an etching process. The insulating layer is removed by using the insulating layer spacer as a barrier. A gate oxide layer(307) is deposited on a part of the removed insulating layer in order to deposit a gate conductor(309a) on the gate oxide layer and the SiN pattern. The SiN pattern is removed by performing an etching process. The insulating layer of the remaining region except to the lower part of the gate is removed by performing the etching process. An LDD ion implantation process is performed to form a source/drain junction. A gate spacer(317) is formed by using the oxide layer and SiN. A source(321) and a drain(323) are formed by implanting high-density ions.

Description

Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}

1A to 1F illustrate a method of manufacturing a conventional semiconductor device,

2 illustrates a structure of a junction having an overlap generated by diffusion into a lower portion of a conventional gate oxide film;

3A to 3K are diagrams illustrating processes for manufacturing a semiconductor device according to a preferred embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More particularly, in forming a transistor, the region to be a gate channel is opened by photolithography and etching, and then deposited on a gate insulating film and a conductor. And a method capable of proceeding with a gate fine process.

As is well known, the process for forming the source / drain of a conventional transistor formed in a logic process is as shown in FIG.

First, a device isolation process and a well process are performed on a semiconductor substrate, followed by sequentially depositing the gate oxide film 101 and the gate material 103, and then performing a photo lithography process to perform a PR pattern. And remove the gate material 103 and the gate oxide film 101 which are sequentially deposited by performing an etching process with the mask on the formed PR pattern, for example, as shown in FIG. 1A. Pattern.

Subsequently, a thin oxide film 105 is deposited on the patterned gate and the semiconductor substrate before the LDD ion implantation, for example, as illustrated in FIG. 1B.

Next, a low concentration of LDD ions are implanted 107 to form a source / drain junction of the peripheral circuit device to form a source / drain junction 109 as an example, as shown in FIG. 1C, and then the streaming process is performed. The thin oxide film 105 deposited on the front surface is removed.

Next, an oxide film 111 and a silicon nitride (SiN) 113 are sequentially deposited on the substrate on which the source / drain junction 109 is formed and the patterned gate, for example, as shown in FIG. 1D. do.

Next, an anisotropic etching process is performed on the deposited oxide film 111 and silicon nitride (SiN) 113 to form the gate spacer 115 as illustrated in FIG. 1E, for example.

Finally, referring to FIG. 1F, a high concentration of source / drain ion implantation 117 is performed, and the source / drain 119 of the transistor is formed through the PMD and the wiring process.

However, the conventional device fabrication method as described above is a plasma damage (S1) applied to the edge portion of the gate oxide film 101 as shown in Figure 1a during the etching process for forming the gate As a result, the gate insulating film exhibiting a weak characteristic to the gate oxide deterioration due to the hot carrier is maintained, thereby reducing the reliability of the device.

In addition, as shown in Fig. 2, there is a problem that it is very difficult to control the structure of the section having an overlap caused by diffusion into the gate oxide film lower portion.

Accordingly, the present invention has been made to solve the above-described problems, the object of the present invention is to open the area to be the gate channel using photolithography and etching process, and then the deposition and gate definition of the gate insulating film and the conductor The present invention provides a method for manufacturing a semiconductor device capable of performing a (define) process.

In order to achieve the above object, a method of manufacturing a semiconductor device includes (a) sequentially depositing an insulating film and silicon nitride (SiN) on a semiconductor substrate, and using a PR pattern as a mask on the deposited SiN. Forming an SiN pattern by performing an etching process; and (b) depositing an entire surface of an insulating film for forming a spacer on the SiN pattern and a part of the insulating film deposited in the step (a), and then performing an etching process. Forming a spacer; (c) removing the lower insulating film deposited in step (a) as a barrier using the insulating film spacer formed in step (b), depositing a gate oxide film on a portion of the removed lower insulating film region, Depositing a gate conductor over the deposited gate oxide and the SiN pattern, and then planarizing the SiN pattern as a barrier; and (d) removing the SiN pattern by etching. Next, in step (c), the planarized gate conductor is etched to remove the insulating layer in the remaining region except the lower portion of the gate as a barrier, and (e) the concentration is low in the remaining region except the lower portion of the gate in (d). Implanting LDD ions to form a source / drain junction, forming a gate spacer using an oxide film and SiN on the formed source / drain junction and the gate, and performing a high concentration of ion implantation to form a source / drain Characterized in that.

Hereinafter, a plurality of embodiments of the present invention may exist, and a preferred embodiment will be described in detail with reference to the accompanying drawings. Those skilled in the art will appreciate the objects, features and advantages of the present invention through this embodiment.

3A to 3K are diagrams illustrating processes for manufacturing a semiconductor device according to a preferred embodiment of the present invention.

That is, referring to FIG. 3A, an insulating film (for example, an oxide film) 301 is formed on a semiconductor substrate (P-Substrate) (for example, a silicon substrate, a ceramic substrate, a polymer substrate, etc.) by performing a coating process such as spin coating. ) And silicon nitride (SiN) 303 are deposited sequentially as shown in FIG. 3A. Here, the insulating film 301 and SiN 303 are respectively deposited to a thickness of 800 to 1200 kPa.

Next, a PR pattern using a reticle designed in an arbitrary pattern of interest and a photo lithography process, which is a developing process, are selectively removed to remove a part of the PR deposited entirely on the silicon nitride 303. An etching process is performed using a mask to remove a portion of the deposited silicon nitride 303, thereby forming the SiN pattern 303a as illustrated in FIG. 3B. At this time, the thickness of the insulating film 301 is set in consideration of the gate poly.

Subsequently, an entire surface of the insulating film 301 and an insulating film (for example, an oxide film) 305 for forming a spacer is formed on the SiN pattern 303a which is partially removed, as shown in FIG. 3C. Next, an etching process is performed to form an insulating film spacer 305a as shown in FIG. 3D, for example. Here, the insulating film 305 is deposited to a thickness within 300 to 600 GPa.

The lower insulating layer 301 is removed as the barrier spacer 305a as an example, as illustrated in FIG. 3E.

Thereafter, the gate oxide layer 307 is deposited on a portion of the region where the lower insulating layer 301 is removed, and the gate conductor 309 is disposed on the deposited gate oxide layer 307 and the SiN pattern 303a as an example. After depositing the entire surface as shown, CMP, which is a planarization process using the SiN pattern 303a as a barrier, is performed to form, for example, a planarized gate conductor 309a as shown in FIG. 3G.

Next, through the etching process, for example, the SiN pattern 303a is removed as shown in FIG. 3H, and then the planarized gate conductor 309a is used as a barrier, except for the lower portion of the gate as shown in FIG. 3I. The insulating film 301 is removed through an etching process. Here, the etching uses a wet method.

Next, low concentration (e.g., 2E13-14) LDD ions are implanted (311) to form source / drain junctions of the peripheral circuit elements, for example, the source 313 / drain 315 as shown in FIG. 3J. Form a junction.

Finally, referring to FIG. 3K, an oxide layer and SiN are sequentially deposited on a substrate on which a source 313 / drain 315 junction is formed and a gate spacer, and anisotropic etching process is performed on the deposited oxide layer and SiN. To form the gate spacers 317, to perform source / drain ion implantation 319 at high concentration (e.g., 2E15), and to form the source 321 / drain 323 of the transistor through a PMD and a wiring process. do.

Therefore, according to the present invention, the region to be the gate channel is opened by photolithography and etching processes, and then the deposition and gate definition processes for the gate insulating film and the conductor are performed, so that the edge portion of the gate oxide film as in the prior art is removed. Maintaining the gate insulating film exhibiting a weak characteristic to the gate oxide deterioration due to hot carriers due to plasma damage can solve the main cause of reducing the reliability of the device. The structure of the section with overlap caused by diffusion can be adjusted to prevent the device performance from being reduced due to the overlap.

In addition, since the present invention is disclosed as a right within the spirit and claims of the present invention, the present invention may include any modification, use and / or adaptation using general principles, and the present invention as a matter deviating from the description of the present specification. It includes everything that falls within the scope of known or customary practice in the art to which it belongs and falls within the scope of the appended claims.

As described above, the present invention uses the photolithography and etching process to open the region to be the gate channel, and then deposits and gates the gate insulating film and the conductor to the edge of the gate oxide film, as before. Plasma damage applied to the portion maintains a gate insulating film exhibiting weak characteristics for gate oxide deterioration due to hot carriers, thereby reducing the main cause of reducing the reliability of the device.

In addition, the structure of the section having an overlap generated by diffusion into the gate oxide film can be adjusted to prevent the reduction of device performance due to the overlap, thereby improving the yield and reliability of the semiconductor device.

Claims (5)

As a manufacturing method of a semiconductor device, (a) sequentially depositing an insulating film and silicon nitride (SiN) on a semiconductor substrate, and forming an SiN pattern by performing an etching process on the deposited SiN using a PR pattern as a mask; (b) depositing an insulating film for forming a spacer on the SiN pattern and a part of the insulating film deposited in step (a), and then performing an etching process to form an insulating film spacer; (c) removing the lower insulating film deposited in step (a) as a barrier using the insulating film spacer formed in step (b), depositing a gate oxide film on a portion of the removed lower insulating film area, and depositing the gate oxide film; Depositing a gate conductor over the SiN pattern, and then planarizing the SiN pattern as a barrier; (d) removing the SiN pattern by etching, and then removing the insulating film in the remaining region except for the lower portion of the gate as the barrier by using the planarized gate conductor in step (c); (e) implanting low concentration LDD ions into regions other than the lower gate in step (d) to form a source / drain junction, and forming a gate spacer using an oxide film and SiN on the formed source / drain junction and the gate Forming a source / drain by implanting a high concentration of ions; Method for manufacturing a semiconductor device comprising a. The method of claim 1, The insulating film and SiN in said step (a) are each deposited in thickness of 800-1200 GPa, The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 1, The insulating film in the step (b) is deposited to a thickness within 300 ~ 600∼. The method according to any one of claims 1 to 3, The said insulating film is an oxide film (Oxide), The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 1, The etching in the step (d) is a method of manufacturing a semiconductor device, characterized in that the wet method.

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