KR950021765A - Transistor Formation Method of Semiconductor Device - Google Patents

Transistor Formation Method of Semiconductor Device Download PDF

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Publication number
KR950021765A
KR950021765A KR1019930031860A KR930031860A KR950021765A KR 950021765 A KR950021765 A KR 950021765A KR 1019930031860 A KR1019930031860 A KR 1019930031860A KR 930031860 A KR930031860 A KR 930031860A KR 950021765 A KR950021765 A KR 950021765A
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KR
South Korea
Prior art keywords
forming
well
ion implantation
semiconductor device
transistor
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Application number
KR1019930031860A
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Korean (ko)
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KR0126652B1 (en
Inventor
우영탁
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김주용
현대전자산업 주식회사
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Priority to KR1019930031860A priority Critical patent/KR0126652B1/en
Publication of KR950021765A publication Critical patent/KR950021765A/en
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Publication of KR0126652B1 publication Critical patent/KR0126652B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 게이트 하부의 well형성시 서로 농도가 다른 p-well과 p+well을 형성함으로서 소오스와 드레인을 바꾸어서 트랜지스터를 동작시킬때 문턱전압을 달리하는 소자를 구현하여 트랜지스터의 회로적용에 유연성을 가질 수 있게 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor of a semiconductor device, and to forming a p-well and a p + well having different concentrations when forming a well under a gate, a device having a different threshold voltage when operating a transistor by changing a source and a drain. The present invention relates to a method for implementing a circuit having flexibility in application of a transistor.

Description

반도체소자의 트랜지스터 형성방법Transistor Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1F도는 본 발명에 의하여 형성된 트랜지스터의 단면도.1A to 1F are cross-sectional views of transistors formed in accordance with the present invention.

Claims (3)

반도체소자의 트랜지스터 형성방법에 있어서, 실리콘 기판상부에 산화막, 폴리실리콘막, 질화막을 적층하고 사진 식각법으로 활성영역의 패턴을 형성하는 공정과, 소자분리절연막을 형성한 후, 남아있는 패턴을 식각하고 이온주입으로 p-well을 형성하는 공정과, p-well의 중간부분까지 덮어지는 감광막 패턴을 형성한 후 이온주입을 실시하여 p+well을 형성하는 공정과, 상기 감광막 패턴을 제거하고 p-well과 p+well상부에 게이트를 형성하고, 열산화막을 형성한 다음, 이온주입으로 n-소오스/드레인을 형성한 후 그 상부에 스페어서 산화막을 적층하는 공정과, 게이트측벽에 스페이서를 형성하고 이온주입을 실시하여 n+소오스/드레인을 형성하는 공정을 포함하는 반도체소자의 트랜지스터 형성방법.A method of forming a transistor of a semiconductor device, comprising: forming an active region pattern by photolithography and stacking an oxide film, a polysilicon film, and a nitride film on a silicon substrate, and etching the remaining pattern after forming the device isolation insulating film. And forming a p-well by ion implantation, forming a photoresist pattern covering the middle portion of the p-well, followed by ion implantation to form a p + well, and removing the photoresist pattern and removing the p-well. forming a gate on the well and the p + well, forming a thermal oxide layer, and then forming an n-source / drain by ion implantation, and stacking the spacer oxide layer thereon; forming a spacer on the gate sidewall; A method of forming a transistor in a semiconductor device comprising the step of ion implantation to form n + source / drain. 제1항에 있어서, p+well형성을 위한 이온주입시 일정한 각도를 주어서 이온주입을 실시하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.The method of claim 1, wherein ion implantation is performed at a predetermined angle during ion implantation for p + well formation. 제1항에 있어서, p+well형성을 위한 이온주입시 B 또는 BF2를 사용하고 이온주입 에너지를 낮게 하는 것을 특징으로 하는 반도체소자의 트랜지스터 형성방법.The method of claim 1, wherein B or BF 2 is used and ion implantation energy is lowered during ion implantation for p + well formation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031860A 1993-12-31 1993-12-31 Formation method of mosfet KR0126652B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031860A KR0126652B1 (en) 1993-12-31 1993-12-31 Formation method of mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031860A KR0126652B1 (en) 1993-12-31 1993-12-31 Formation method of mosfet

Publications (2)

Publication Number Publication Date
KR950021765A true KR950021765A (en) 1995-07-26
KR0126652B1 KR0126652B1 (en) 1998-04-02

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Application Number Title Priority Date Filing Date
KR1019930031860A KR0126652B1 (en) 1993-12-31 1993-12-31 Formation method of mosfet

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102109010B1 (en) 2017-10-11 2020-06-03 (주)세종인더스트리 Light transmissive print article having a double metal deposition layer and manufacturing method

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