KR0172743B1 - Method of manufacturing transistor in semiconductor device - Google Patents
Method of manufacturing transistor in semiconductor device Download PDFInfo
- Publication number
- KR0172743B1 KR0172743B1 KR1019950048748A KR19950048748A KR0172743B1 KR 0172743 B1 KR0172743 B1 KR 0172743B1 KR 1019950048748 A KR1019950048748 A KR 1019950048748A KR 19950048748 A KR19950048748 A KR 19950048748A KR 0172743 B1 KR0172743 B1 KR 0172743B1
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- South Korea
- Prior art keywords
- oxide film
- semiconductor device
- entire structure
- etching
- trench
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005304 joining Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
본 발명은 접합영역과 채널영역을 산화막 스페이서에 의해 격리시키므로서 단 채널 효과 억제 및 소자의 안정성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 트랜지스터 제조 방법이 개시된다.The present invention discloses a method for fabricating a transistor of a semiconductor device capable of improving the stability and reliability of a device and suppressing short channel effects by isolating the junction region and the channel region by an oxide film spacer.
Description
제1a도 내지 제1f도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 웰1: silicon substrate 2: well
3 : 필드 산화막 4 : 감광막3: field oxide film 4: photosensitive film
5 : 트랜치 6A : 제1차산화막5: trench 6A: primary oxide film
6B : 제1차산화막 스페이서 7 : 제1차폴리실리콘층6B: primary oxide film spacer 7: primary polysilicon layer
8 : 게이트 산화막 9 : 제2차폴리실리콘층8 gate oxide film 9 secondary polysilicon layer
10 : 게이트 전극 11 : 제2차산화막 스페이서10 gate electrode 11 secondary oxide film spacer
12 : 접합영역 13 : 채널영역12: junction area 13: channel area
본 발명은 반도체 소자의 트랜지스터의 제조 방법에 관한 것으로서, 특히 트랜지스터의 접합영역과 채널영역을 격리시킬 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly to a method of manufacturing a transistor of a semiconductor device in which a junction region and a channel region of a transistor can be isolated.
일반적으로 종래의 반도체 소자의 트랜지스터 제조 방법에 의해 트랜지스터를 형성하면 채널 길이가 1㎛이하 단-채널(Short-Channel) 효과에 의해 항복 전압 현상, 핫 캐리어 현상등에 의해 소자 사용에 따라 소자 특성이 저하되는 단점이 있고, 트랜지스터 간의 절연을 하기 위한 필드 산화막은 두께가 매우 커서 초기 공정부터 평탄화가 이루어지지 않아 후속 공정에 커다란 문제를 유발시키는 단점이 있다. 따라서, 본 발명은 채널영역에 트랜치를 형성한 후, 트랜치의 양측에 스페이서 산화막을 형성하여 접합 영역과 채널 영역을 격리시킬 수 있도록 한 반도체 소자의 트랜지스터 제조 방법을 제공하는데 그 목적이 있다. 상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 웰이 형성된 후, 소자 분리를 위해 필드 산화막을 형성하는 단계와, 상기 전체 구조 상부에 감광막이 도포되고 포토리소그라피공정으로 상기 감광막을 패턴닝하는 단계와, 상기 웰이 감광막을 마스크로 이용한 식각공정으로 식각되어 트랜치를 형성하고, 상기 전체 구조 상부에 산화막을 증착하는 단계와, 상기 산화막을 식각공정에 의해 접합영역의 트랜치 측벽에 산화막 스페이서를 형성하는 단계와, 상기 전체 구조 상부에 폴리실리콘층을 형성하고, 상기 폴리실리콘층과 필드 산화막이 CMP공정으로 식각되어 접합영역의 트랜치에는 폴리실리콘이 남게 되고, 필드 산화막을 평탄화시키는 단계와, 상기 웰 상부에 게이트 전극을 형성하고, 게이트 전극 측벽에 산화막 스페이서를 형성하는 단계와, 상기 전체 구조 상부에 불순물이 주입되어 접합영역이 형성하는 것을 특징으로 한다.In general, when a transistor is formed by a transistor manufacturing method of a conventional semiconductor device, device characteristics are deteriorated due to breakdown voltage phenomenon and hot carrier phenomenon due to a short-channel effect having a channel length of 1 μm or less. The field oxide film for insulating between transistors is very large and has a disadvantage in that the planarization is not performed from an initial process and causes a great problem in subsequent processes. Accordingly, an object of the present invention is to provide a method for fabricating a transistor in a semiconductor device in which a spacer oxide film is formed on both sides of the trench after the trench is formed in the channel region so as to isolate the junction region and the channel region. The present invention for achieving the above object is to form a field oxide film for the isolation of the device after the well is formed on the silicon substrate, a photosensitive film is applied on the entire structure and the photosensitive film is patterned by a photolithography process And forming a trench by etching the well by an etching process using a photoresist as a mask, depositing an oxide layer on the entire structure, and forming an oxide spacer on the trench sidewall of the junction region by etching the oxide layer. Forming a polysilicon layer on the entire structure, and etching the polysilicon layer and the field oxide layer by a CMP process to leave polysilicon in the trench of the junction region, and planarizing the field oxide layer, and Forming a gate electrode on the upper portion and forming an oxide spacer on the sidewall of the gate electrode , Is the injection of impurities in the entire structure above is characterized in that the joining region is formed.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제a도와 관련하여, 실리콘 기판(1)상에 웰(2)이 형성된 후, 소자 분리를 위해 필드산화막(3)이 형성된다. 상기 전체 구조 상부에 감광막(4)이 도포되고 포토리소그라피공정으로 상기 감광막(4)이 패턴닝된다.In relation to FIG. A, after the well 2 is formed on the silicon substrate 1, a field oxide film 3 is formed for device isolation. A photoresist film 4 is applied over the entire structure and the photoresist film 4 is patterned by a photolithography process.
제1c도와 관련하여, 상기 웰(2)에 감광막(4)을 마스크로 이용한 식각공정으로 식각되어 트랜치(5)가 형성된 후, 상기 전체 구조 상부에 제1차 산화막(6A)이 식각공정에 패터닝되어 웰(2)의 트랜치(5)측벽에 산화막 스페이서(6B)가 형성된다. 이때, 산화막 스페이서(6B)는 최상단이 접합층 깊이(A)정도에까지 이르게 식각된다.In connection with FIG. 1C, after the etching process using the photoresist film 4 as a mask in the well 2 to form a trench 5, a first oxide film 6A is patterned on the entire structure. As a result, an oxide film spacer 6B is formed on the side wall of the trench 5 of the well 2. At this time, the oxide film spacer 6B is etched so that its uppermost end reaches the junction layer depth A. FIG.
제1d도와 관련하여, 상기 전체 구조 상부에 제1차폴리실리콘층(7)이 형성된다.Regarding FIG. 1d, a primary polysilicon layer 7 is formed over the entire structure.
제1e도와 관련하여, 상기 제1차폴리실리콘층(7)과 필드 산화막(3)이 CMP공정으로 전면 연마 식각되어 웰(2)의 트랜치(5)영역에 제1차폴리실리콘(7)은 남게 되고, 필드 산화막(3)은 평탄화된다.In relation to FIG. 1E, the primary polysilicon layer 7 and the field oxide layer 3 are subjected to full abrasive etching by a CMP process so that the primary polysilicon 7 is formed in the trench 5 region of the well 2. The field oxide film 3 is planarized.
제1f도와 관련하여, 상기 웰(2) 상부에 게이트 산화막(8) 및 제2차폴리실리콘층(9)이 적층된 게이트 전극(10)이 형성된다. 상기 게이트 전극(10)이 형성된 상부에 제2차 산화막이 증착된 후, 식각공정이 실시되어 게이트 전극(10)측벽에 제2차산화막 스페이서(11)가 형성된다. 상기 전체 구조 상부에 불순물이 주입되어 접합영역(12)이 형성된다. 상기 접합영역(12)과 채널영역(13)은 제2차 산화막 스페이서(11)의해 격리되므로서 단-채널 효과가 억제된다. 또한, 필드 산화막(3)이 평탄화됨으로서 후속 공정 마진에 장점이 있다.In relation to FIG. 1f, a gate electrode 10 in which a gate oxide layer 8 and a second polysilicon layer 9 are stacked is formed on the well 2. After the secondary oxide film is deposited on the gate electrode 10, the etching process is performed to form the secondary oxide spacer 11 on the side wall of the gate electrode 10. Impurities are implanted into the entire structure to form a junction region 12. The junction region 12 and the channel region 13 are isolated by the secondary oxide spacer 11 so that the short-channel effect is suppressed. In addition, since the field oxide film 3 is planarized, there is an advantage in subsequent process margins.
상술한 바와 같이 본 발명에 의하면 접합영역과 채널영역을 산화막 스페이서에 의해 격리시키므로서 단 채널(short-channel)효과 억제 및 소자의 안정성 및 신뢰성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since the junction region and the channel region are separated by the oxide spacer, there is an excellent effect of suppressing short-channel effects and improving the stability and reliability of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048748A KR0172743B1 (en) | 1995-12-12 | 1995-12-12 | Method of manufacturing transistor in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048748A KR0172743B1 (en) | 1995-12-12 | 1995-12-12 | Method of manufacturing transistor in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970054340A KR970054340A (en) | 1997-07-31 |
| KR0172743B1 true KR0172743B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950048748A KR0172743B1 (en) | 1995-12-12 | 1995-12-12 | Method of manufacturing transistor in semiconductor device |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100345522B1 (en) * | 1999-12-31 | 2002-07-24 | 아남반도체 주식회사 | Method for forming gate of transistor |
| KR100345521B1 (en) * | 1999-12-31 | 2002-07-24 | 아남반도체 주식회사 | Method for forming gate of transistor |
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1995
- 1995-12-12 KR KR1019950048748A patent/KR0172743B1/en not_active IP Right Cessation
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| KR970054340A (en) | 1997-07-31 |
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