KR100214534B1 - Method of forming a device isolation structure of semiconductor device - Google Patents
Method of forming a device isolation structure of semiconductor device Download PDFInfo
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- KR100214534B1 KR100214534B1 KR1019960066632A KR19960066632A KR100214534B1 KR 100214534 B1 KR100214534 B1 KR 100214534B1 KR 1019960066632 A KR1019960066632 A KR 1019960066632A KR 19960066632 A KR19960066632 A KR 19960066632A KR 100214534 B1 KR100214534 B1 KR 100214534B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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Abstract
본 발명은 고집적 반도체소자에 적당하도록 한 반도체소자의 소자격리구조(Isolation) 형성방법에 관한 것으로, 실리콘기판 위에 제1절연막과 제2절연막을 형성하는 단계와; 포토리소그레피 및 식각공정으로 상기 제2절연막과 제1절연막을 패터닝하여 식각영역을 정의하는 단계와; 상기 식각영역에 따라 실리콘기판을 식각하여 트렌치를 형성한 후, 그 결과물의 전면에 제31절연막을 증착하는 단계와; 상기 제3절연막 및 제2절연막, 제1절연막을 에치백(Etch-back)하는 단계와; 상기 에치백 단계에 의하여 트렌치의 아래 부분까지 식각된 제3절연막과 그 트렌치의 측면으로 정의되는 모서리에 제4절연막 측벽스페이서를 형성하는 단계로 이루어지는 것을 특징으로 한다. 이에 따른 소자격리구조는 상기 제4절연막 측벽스페이서로 인하여 트렌치의 입구가 부드러운 곡선구조로 형성되는데, 그와 같이 곡선구조로 형성된 소자격리구조는 이후에 형성되는 게이트절연막 및 게이트전극이 절곡되지 않도록 하여 그 영역에서 전계가 집중되지 않도록 하는 효과를 준다.The present invention relates to a method for forming a device isolation structure of a semiconductor device suitable for a highly integrated semiconductor device, comprising: forming a first insulating film and a second insulating film on a silicon substrate; Patterning the second insulating layer and the first insulating layer by photolithography and etching to define an etching region; Etching the silicon substrate according to the etching region to form a trench, and then depositing a thirty-first insulating layer on the entire surface of the resultant; Etching back the third insulating film, the second insulating film, and the first insulating film; And forming a fourth insulating layer sidewall spacer at an edge defined by a side of the trench and the third insulating layer etched to the lower portion of the trench by the etch back step. Accordingly, the device isolation structure has a smooth curved structure due to the fourth insulating layer sidewall spacer, and the device isolation structure formed as such a curved structure prevents the gate insulating film and the gate electrode formed thereafter from being bent. This has the effect of not concentrating the electric field in that area.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 고집적 반도체소자에 적당하도록 한 반도체소자의 소자격리구조(Isolation) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an isolation device for a semiconductor device suitable for a highly integrated semiconductor device.
얕은 트렌치 소자격리구조(Shallow Trench Isolation)는 반도체소자가 고집적화됨에 따라 제안된 것으로, 그러한 소자격리구조의 형성방법에 대해서 첨부한 도면을 참조하여 설명하면 다음과 같다.Shallow Trench Isolation is proposed as a semiconductor device is highly integrated. A method of forming such a device isolation structure will be described below with reference to the accompanying drawings.
도1a-도1e는 종래 기술에 따른 소자격리구조 형성방법을 도시한 공정 단면도로서, 이에 도시된 바와 같이 실리콘기판(110) 위에 제1실리콘산화물(SiO2)(120)과 실리콘질화물(Si3N4)(130)을 순차적으로 증착하는 단계(도1a)와; 포토리소그레피 및 식각공정으로 상기 실리콘질화막(130)과 제`실리콘산화막(120)을 패터닝하여 식각영역을 정의하는 단계(도1b)와; 상기 식각영역에 따라 실리콘기판(110)을 식각하여 트렌치를 형성한 후, 그 결과물의 전면에 제2실리콘산화물(140)을 CVD법으로 증착하는 단계(도1c)와; CMD(chemical michanical polishing) 공정으로 상기 제2실리콘산화막(140) 및 실리콘질화막(130), 제`실리콘산화막(120)을 에치백(Etch-back)하는 단계(도1d)를 통해 트렌치 소자격리구조를 형성하였다. 이때, 도1b에 표시된 미설명 부호(171)는 포토레지스트를 나타낸다.1A to 1E are cross-sectional views illustrating a method of forming a device isolation structure according to the related art. As illustrated therein, a first silicon oxide (SiO 2 ) 120 and a silicon nitride (Si 3 ) are formed on a silicon substrate 110. Sequentially depositing N 4 ) 130 (FIG. 1A); Patterning the silicon nitride layer 130 and the silicon oxide layer 120 by photolithography and etching to define an etching region (FIG. 1B); Forming a trench by etching the silicon substrate 110 according to the etching region, and then depositing a second silicon oxide 140 on the entire surface of the resultant by CVD (FIG. 1C); Trench device isolation structure through etching back the second silicon oxide layer 140, the silicon nitride layer 130, and the silicon oxide layer 120 by a chemical michanical polishing (CMD) process (FIG. 1D). Was formed. In this case, reference numeral 171 shown in FIG. 1B denotes a photoresist.
이후, 상기와 같은 트렌치 소자격리구조(141)가 형성된 실리콘기판(111) 위에 도1e에 도시된 바와 같이 게이트산화막(160)과 게이트(170) 등을 차례대로 형성한다.Thereafter, as shown in FIG. 1E, the gate oxide layer 160, the gate 170, and the like are sequentially formed on the silicon substrate 111 on which the trench device isolation structure 141 is formed.
그러나, 상기와 같이 제2실리콘산화막과 실리콘질화막, 제`실리콘산화막을 CMP 공정으로 에치백하여 트렌치 소자격리구조를 완성하는 종래 기술은, 상기 CMP 공정에서 제2실리콘산화막이 트렌치의 아래 부분까지 식각되게 되는 문제점이 있었다. 즉, 도1e와 같이 트렌치의 입구가 예각의 모서리(A)로 형성됨에 따라, 그 위에 형성되는 게이트산화막 및 게이트전극도 절곡됨으로써, 완성된 소자가 동작할 때 그 영역의 게이트산화막에서 전계 집중이 일어나게 되는 문제점이 있었다.However, the conventional technique of completing the trench isolation structure by etching back the second silicon oxide film, the silicon nitride film, and the first silicon oxide film by the CMP process as described above, the second silicon oxide film is etched to the lower portion of the trench in the CMP process. There was a problem. That is, as the inlet of the trench is formed at an acute corner A as shown in FIG. 1E, the gate oxide film and the gate electrode formed thereon are also bent, so that electric field concentration in the gate oxide film of the region when the completed device operates is performed. There was a problem that occurred.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 창안한 것으로, 트렌치의 입구가 부드러운 곡선형으로 형성되도록 함으로써, 그 영역의 게이트산화막에서 전계가 집중되지 않도록 하는데 적당하도록 한 반도체소자의 소자격리구조 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above problems, and by forming the trench inlet in a smooth curved shape, forming the device isolation structure of the semiconductor device so that the electric field is not concentrated in the gate oxide film of the region In providing a method.
제1a도-제1e도는 종래 기술에 따른 소자격리구조 형성방법을 나타낸 공정 단면도.1A to 1E are cross-sectional views illustrating a method of forming a device isolation structure according to the prior art.
제2a도-제2g도는 본 발명의 일실시예에 따른 소자격리구조 형성방법을 나타낸 공정단면도.2A to 2G are cross-sectional views illustrating a method of forming a device isolation structure according to an embodiment of the present invention.
제3a도와 제3b도는 본 발명의 다른 실시예에 따른 소자격리구조 형성공정의 일부를 나타낸 공정 단면도.3A and 3B are cross-sectional views illustrating part of a process of forming a device isolation structure according to another exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
211 : 실리콘기판 220, 221 : 제1실리콘산화막211: silicon substrate 220, 221: first silicon oxide film
230, 231 : 제1실린콘질화막 240, 241 : 제2실리콘산화막230, 231: first silicon nitride film 240, 241: second silicon oxide film
250, 251 : 제2실리콘질화막 260 : 게이트산화막250 and 251: second silicon nitride film 260: gate oxide film
270 : 게이트전극270 gate electrode
350, 351 : 문턱전압 조절을 위한 이온주입공정에서 사용되는 버퍼산화막.350, 351: Buffer oxide film used in the ion implantation process for controlling the threshold voltage.
상기 목적을 달성하기 위한 본 발명은, 실리콘기판 위에 제1절연막과 제2절연막을 형성하는 단계와; 포토리소그레피 및 식각공정으로 상기 제2절연막과 제1절연막을 패터닝하여 식각영역을 정의하는 단계와; 상기 식각영역에 따라 실리콘기판을 식각하여 트렌치를 형성한 후, 그 결과물의 전면에 제3절연막을 증착하는 단계와; 상기 제3절연막 및 제2절연막, 제1절연막을 에치백(Etch-back)하는 단계와; 상기 에치백 단계에 의하여 트렌치의 아래 부분까지 식각된 제3절연막과 그 트렌치의 측면으로 정의되는 모서리에 제4절연막 측벽스페이서를 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a first insulating film and a second insulating film on a silicon substrate; Patterning the second insulating layer and the first insulating layer by photolithography and etching to define an etching region; Forming a trench by etching the silicon substrate according to the etching region, and then depositing a third insulating layer on the entire surface of the resultant; Etching back the third insulating film, the second insulating film, and the first insulating film; And forming a fourth insulating layer sidewall spacer at an edge defined by a side of the trench and the third insulating layer etched to the lower portion of the trench by the etch back step.
이하, 첨부된 도면을 참조하여 본 발명의 여러 실시예를 설명한다.Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.
도2a-도2g는 본 발명의 일실시예에 따른 소자격리구조 형성방법을 나타낸 공정 단면도로서, 이를 참조하여 상세히 설명하면 다음과 같다.2A to 2G are cross-sectional views illustrating a method of forming a device isolation structure according to an embodiment of the present invention.
우선, 도2a-도2d에 도시된 바와 같이 실리콘기판(210) 위에 제1실리콘산화물(220)과 제1실리콘질화물(230)을 순차적으로 증착한 후(도2a), 포토리소그레피 및 식각공정으로 상기 제1실리콘질화막(230)과 제1실리콘산화막(220)을 패터닝하여 식각영역을 정의하고(도2b), 그 식각영역에 따라 실리콘기판(210)을 식각하여 트렌치를 형성한 후, 그 결과물의 전면에 제2실리콘산화물(240)을 CVD법으로 증착하고(도2c), CMP(chemical michanical polishing) 공정으로 상기 제2실리콘산화막(240) 및 제1실리콘질화막(230), 제1실리콘산화막(220)을 에치백(Etch-back)한다(도2d). 이와 같은 공정은 종래 기술에 따른 소자격리구조 형성방법과 같은 것으로, 식각된 제2실리콘산화막(141)이 트렌치의 아래 부분까지 식각되었음을 보여주고 있다.First, as shown in FIGS. 2A to 2D, the first silicon oxide 220 and the first silicon nitride 230 are sequentially deposited on the silicon substrate 210 (FIG. 2A), followed by photolithography and etching. After the process, the first silicon nitride film 230 and the first silicon oxide film 220 are patterned to define an etching region (FIG. 2B), and the silicon substrate 210 is etched according to the etching region to form a trench. The second silicon oxide 240 is deposited on the entire surface of the resultant by CVD (FIG. 2C), and the second silicon oxide film 240, the first silicon nitride film 230, and the first silicon oxide film are subjected to a chemical michanical polishing (CMP) process. The silicon oxide film 220 is etched back (FIG. 2D). This process is the same as the method of forming a device isolation structure according to the prior art, and shows that the etched second silicon oxide film 141 is etched to the lower portion of the trench.
이후, 도2e와 도2f와 같이 상기 결과물 위에 제2실리콘질화물(250)을 증착한 후, 그 제2실리콘질화막(250)을 에치백(Etch-back)하여 트렌치의 아래 부분까지 식각된 제2실리콘산화막(241)과 그 트렌치의 측면으로 정의되는 모서리에 제2실리콘질화막 측벽스페이서(251)를 형성한다. 이에 따라, 트렌치의 입구가 상기 제2실리콘질화막 측벽스페이서(251)에 의하여 부드러운 곡면으로 형성된 트렌치 소자격리구조(241,251)를 완성한다.2E and 2F, after depositing the second silicon nitride 250 on the resultant, the second silicon nitride layer 250 is etched back to etch the second portion to the lower portion of the trench. A second silicon nitride film sidewall spacer 251 is formed at the edge defined by the silicon oxide film 241 and the side surface of the trench. Accordingly, trench element isolation structures 241 and 251 having a trench formed in a smooth curved surface by the second silicon nitride film sidewall spacer 251 are completed.
이후, 도2e에 도시된 바와 같이 트렌치의 입구가 부드러운 곡면 구조로 형성된 트렌치 소자격리구조(241,251)에 의하여 필드영역과 액티브영역이 구분된 상기 실리콘기판(211) 위에 상기 트렌치의 일부영역과 겹치는 게이트산화막(260)과 게이트전극(270)을 형성한다.Next, as shown in FIG. 2E, a gate overlapping a portion of the trench is formed on the silicon substrate 211 in which the field region and the active region are separated by the trench element isolation structures 241 and 251 having a smooth curved structure. The oxide film 260 and the gate electrode 270 are formed.
그리고, 도3a와 도3b는 본 발명의 다른 실시예에 따른 소자격리구조 형성공정의 일부를 나타낸 공정 단면도로서, 각각 도2e 및 도2f에 대응하는 측벽스페이서 형성공정을 나타낸다. 상세히 설명하면, 도2d와 같이 제2실리콘산화막(240) 및 제1실리콘질화막(230), 제1실리콘산화막(220)을 에치백(Etch-back)하는 공정에서 상기 제2실리콘산화막(240)이 트렌치의 아래 부분까지 식각된 경우, 바로 상기 도2e와 도2f에 도시된 바와 같이 제2실리콘질화막(250)을 증착/에치백하여 제2실리콘질화막 측벽스페이서(251)를 형성하는 공정을 별도로 수행하지 않고, 추후에 문턱전압(Vt)을 조절하거나 웰(WELL)을 형성학이 위해서 수행되는 이온주입공정이 끝나는 대로, 그 이온주입공정에서 사용된 버퍼산화막(350)을 반응성이온에칭(RIE)법으로 식각하여 측벽스페이서(351)를 형성하도록 한 소자격리구조 형성공정을 나타낸다.3A and 3B are cross-sectional views illustrating a part of a device isolation structure forming process according to another embodiment of the present invention, and show sidewall spacer forming processes corresponding to FIGS. 2E and 2F, respectively. In detail, as shown in FIG. 2D, the second silicon oxide film 240 is etched back from the second silicon oxide film 240, the first silicon nitride film 230, and the first silicon oxide film 220. When etching to the lower portion of the trench, the process of depositing / etching the second silicon nitride film 250 to form the second silicon nitride film sidewall spacer 251 as shown in FIGS. 2E and 2F is performed separately. After performing the ion implantation process to adjust the threshold voltage (Vt) or to form the well (WELL) later without performing, the buffer oxide film 350 used in the ion implantation process is reactive ion etching (RIE). A device isolation structure formation process for etching sidewall spacers 351 by etching is shown.
상술한 바와 같이, 일반적인 CMP공정으로 트렌치에 채워진 실리콘산화물을 식각한 후, 그 실리콘산화막이 과식각됨에 따라 트렌치의 입구에 형성되는 예각 모서리에1절연막 측벽스페이서를 형성하는 본 발명에 따른 소자격리구조 형성방법은, 상기1절연막 측벽스페이서로 인하여 트렌치의 입구가 부드러운 곡선구조로 형성되기 때문에, 이후에 형성되는 게이트절연막 및 게이트전극이 절곡되지 않게 됨으로써, 그 영역에서 전개가 집중되지 않게 되는 효과가 있다.As described above, after the silicon oxide filled in the trench is etched by a general CMP process, the isolation layer according to the present invention forms one insulating film sidewall spacer at an acute corner formed at the inlet of the trench as the silicon oxide film is overetched. Since the inlet of the trench is formed in a smooth curved structure due to the first insulating film sidewall spacer, the gate insulating film and the gate electrode formed later are not bent, so that the development is not concentrated in the region. .
Claims (4)
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| KR1019960066632A KR100214534B1 (en) | 1996-12-17 | 1996-12-17 | Method of forming a device isolation structure of semiconductor device |
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| KR1019960066632A KR100214534B1 (en) | 1996-12-17 | 1996-12-17 | Method of forming a device isolation structure of semiconductor device |
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| KR100498591B1 (en) * | 1998-12-24 | 2005-09-30 | 주식회사 하이닉스반도체 | Trench device isolation method for highly integrated semiconductor devices |
| KR100546699B1 (en) * | 2000-12-30 | 2006-01-26 | 주식회사 하이닉스반도체 | Method for fabricating trench isolation film of semiconductor device |
| KR101008224B1 (en) * | 2003-09-29 | 2011-01-17 | 매그나칩 반도체 유한회사 | High voltage cmos device by using silicon on insulator wafer and method for manufacturing the same |
| KR102054185B1 (en) * | 2013-03-15 | 2019-12-10 | 삼성전자주식회사 | Semiconductor Devices and methods of manufacturing the same |
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