KR100236914B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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KR100236914B1
KR100236914B1 KR1019970055148A KR19970055148A KR100236914B1 KR 100236914 B1 KR100236914 B1 KR 100236914B1 KR 1019970055148 A KR1019970055148 A KR 1019970055148A KR 19970055148 A KR19970055148 A KR 19970055148A KR 100236914 B1 KR100236914 B1 KR 100236914B1
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semiconductor substrate
device isolation
isolation insulating
insulating layer
region
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KR1019970055148A
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Korean (ko)
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KR19990033742A (en
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김용찬
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Abstract

본 발명은 반도체장치 및 그의 제조방법에 관한 것으로서 메모리셀영역 및 주변회로영역을 갖는 반도체기판과, 상기 반도체기판의 메모리셀영역에 하부가 상기 반도체기판의 표면 보다 낮으며 상부의 표면이 상기 반도체기판과 평탄되게 형성된 제 1 소자격리절연층과, 상기 반도체기판의 주변회로영역에 상부 표면이 상기 반도체기판의 표면 보다 높게 형성된 제 2 소자격리절연층을 포함한다. 따라서, 메모리셀영역이 주변회로영역 보다 낮으므로 메모리셀영역에 트랜지스터를 형성하면 제 2 소자격리절연층에 의해 주변 회로영역과 단차가 감소되어 이 후의 배선 공정이 용이해지며 디슁 현상을 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, comprising: a semiconductor substrate having a memory cell region and a peripheral circuit region; a lower portion of the semiconductor substrate is lower than a surface of the semiconductor substrate; And a first device isolation insulating layer formed to be flat with the second device isolation insulating layer, the upper surface of which is formed higher than the surface of the semiconductor substrate in the peripheral circuit region of the semiconductor substrate. Therefore, since the memory cell region is lower than the peripheral circuit region, when the transistor is formed in the memory cell region, the step difference between the peripheral circuit region and the peripheral circuit region is reduced by the second device isolation insulating layer, thereby facilitating the subsequent wiring process and preventing the dipping phenomenon. have.

Description

반도체장치 및 그의 제조방법Semiconductor device and manufacturing method thereof

본 발명은 반도체장치 및 그의 제조방법에 관한 것으로서, 특히, 작은 면적의 소자격리절연층과 큰 면적의 소자격리절연층을 갖는 반도체장치 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a small area isolation layer and a large area isolation layer.

도 1a 내지 도 1c는 종래 기술에 따른 소자격리방법을 도시하는 공정도이다.1A to 1C are process diagrams illustrating a device isolation method according to the prior art.

도 1a를 참조하면, 반도체기판(11) 상에 열산화 방법으로 버퍼산화막(13)을 형성하고, 이 버퍼산화막(13) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(15)을 형성한다. 그리고, 포토리쏘그래피(photolithography) 방법으로 반도체기판(11)의 소자격리영역이 노출되도록 마스크층(15) 및 버퍼산화막(13)을 선택적으로 제거하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form a mask layer 15. The device isolation region and the active region are defined by selectively removing the mask layer 15 and the buffer oxide layer 13 so that the device isolation region of the semiconductor substrate 11 is exposed by photolithography.

도 1b를 참조하면, 소자격리영역에 노출된 반도체기판(11)을 건식식각하여 소정 깊이로 식각하여 메모리셀영역(C1)에 작은 영역의 제 1 트렌치(17)와 주변 회로영역(P1)에 넓은 영역의 제 2 트렌치(18)를 형성한다. 그리고, 상술한 구조의 전 표면에 산화막(19)을 CVD 방법으로 제 1 및 제 2 트렌치(16)(17)가 채워지도록 증착한다. 이때, 산화막(19)은 작은 영역의 제 1 트렌치(16)를 채우며 넓은 영역의 제 2 트렌치(17)를 표면에 따라 증착된다. 그러므로, 산화막(19)은 제 2 트렌치(17)의 깊이 만큼 오목하게 형성된다. 그리고, 산화막(19)의 표면에 감광막 또는 SOG(Spin On Glass) 등을 도포하여 평탄화층(21)을 형성한다.Referring to FIG. 1B, the semiconductor substrate 11 exposed to the device isolation region is dry etched and etched to a predetermined depth, so that the first trench 17 and the peripheral circuit region P1 having a small area in the memory cell area C1 are etched. The second trench 18 is formed in a wide area. Then, the oxide film 19 is deposited on the entire surface of the structure described above so that the first and second trenches 16 and 17 are filled by the CVD method. At this time, the oxide film 19 fills the first trench 16 in the small region and deposits the second trench 17 in the large region along the surface. Therefore, the oxide film 19 is formed concave by the depth of the second trench 17. Then, the planarization layer 21 is formed by applying a photosensitive film or spin on glass (SOG) to the surface of the oxide film 19.

도 1c를 참조하면, 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법이나 화학-기계적연마(Chemical Mechanical Polishing : 이하, CMP라 칭함) 방법으로 평탄화층(21)과 산화막(19)의 식각 속도가 같도록 에치 백한다. 이 때, 질화막(15) 및 패드산화막(13)도 제거되어 반도체기판(11)이 노출되도록 에치백하는 데, 제 1 및 제 2 트렌치(16)(17)에 잔류하는 산화막(19)은 제 1 및 제 2 소자격리절연층(23)(24)이 된다.Referring to FIG. 1C, the planarization layer 21 and the oxide film 19 may be formed by a reactive ion etching (hereinafter referred to as RIE) method or a chemical mechanical polishing (hereinafter referred to as CMP) method. Etch back so that the etching speed is the same. At this time, the nitride film 15 and the pad oxide film 13 are also removed and etched back to expose the semiconductor substrate 11. The oxide film 19 remaining in the first and second trenches 16 and 17 is made of First and second element isolation insulating layers 23 and 24 are provided.

그러나, 상술한 종래의 반도체장치의 소자격리방법은 넓은 소자격리영역에서 좁은 소자격리영역 보다 식각량이 커 움푹 파이는 디슁(dishing) 현상이 발생될 뿐만 아니라 메모리셀영역 상에 트랜지스터를 형성한 후 배선을 형성할 때 주변 회로영역와 단차가 커 공정이 어려운 문제점이 있었다.However, the device isolation method of the conventional semiconductor device described above not only causes a dishing phenomenon in which the etching amount is larger than the narrow device isolation region in a wide device isolation region, but also a wiring after forming a transistor in the memory cell region. There was a problem in that the process is difficult when the step is larger than the peripheral circuit area.

따라서, 본 발명의 목적은 메모리셀영역 상에 트랜지스터를 형성한 후 배선을 형성할 때 주변 회로영역와 단차를 감소시키고 디슁 현상을 방지할 수 있는 반도체장치 및 그의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce the step and peripheral circuit area and prevent the desorption phenomenon when forming a transistor after forming a transistor on the memory cell area.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치는 메모리셀영역 및 주변회로영역을 갖는 반도체기판과, 상기 반도체기판의 메모리셀영역에 하부가 상기 반도체기판의 표면 보다 낮으며 상부의 표면이 상기 반도체기판과 평탄되게 형성된 제 1 소자격리절연층과, 상기 반도체기판의 주변회로영역에 상부 표면이 상기 반도체기판의 표면 보다 높게 형성된 제 2 소자격리절연층을 포함한다.A semiconductor device according to the present invention for achieving the above object is a semiconductor substrate having a memory cell region and a peripheral circuit region, the lower portion of the memory cell region of the semiconductor substrate is lower than the surface of the semiconductor substrate, the upper surface of the semiconductor A first device isolation insulating layer formed to be flat with the substrate, and a second device isolation insulating layer having an upper surface higher than that of the semiconductor substrate in the peripheral circuit region of the semiconductor substrate.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 메모리셀영역 및 주변회로영역을 갖는 반도체기판 상의 소정 부분에 마스크층을 형성하여 상기 반도체기판의 상기 메모리셀영역과 상기 주변회로영역의 각각의 소정 부분을 노출시켜 좁은 면적의 제 1 소자격리영역과 넓은 면적의 제 2 소자격리영역을 한정하는 공정과, 상기 반도체기판의 상기 제 1 및 제 2 소자격리영역에 상기 반도체기판의 표면 보다 높은 표면을 갖는 제 1 및 제 2 소자격리절연층을 형성하는 공정과, 상기 마스크층을 제거하고 상기 제 1 소자격리절연층의 상기 반도체기판 보다 높은 부분을 선택적으로 제거하는 공정을 구비한다.A semiconductor device manufacturing method according to the present invention for achieving the above object is formed by forming a mask layer on a predetermined portion on a semiconductor substrate having a memory cell region and a peripheral circuit region of the memory cell region and the peripheral circuit region of the semiconductor substrate. Exposing each predetermined portion to define a narrow area of the first device isolation region and a wide area of the second device isolation region; and to the first and second device isolation regions of the semiconductor substrate than the surface of the semiconductor substrate. Forming a first and a second device isolation insulating layer having a high surface, and removing the mask layer and selectively removing a portion higher than the semiconductor substrate of the first device isolation insulating layer.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조공정도1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체장치의 단면도2 is a cross-sectional view of a semiconductor device according to the present invention.

도 3a 내지 도 3c는 본 발명에 따른 반도체장치의 제조공정도3A to 3C are manufacturing process diagrams of a semiconductor device according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체장치의 단면도이다.2 is a cross-sectional view of a semiconductor device according to the present invention.

본 발명에 따른 반도체장치는 반도체기판(31)의 소정 부분에 소자격리영역과 활성영역을 한정하는 제 1 및 제 2 소자격리절연층(37)(39)이 된다. 상기 제 1 소자격리절연층(37)은 반도체기판(31) 상의 메모리셀영역(C2)에 작은 면적으로 형성되며, 제 2 소자격리절연층(39)은 주변회로영역(P2)에 큰 면적으로 형성된다.The semiconductor device according to the present invention is a first and second device isolation insulating layers 37 and 39 which define a device isolation region and an active region in a predetermined portion of the semiconductor substrate 31. The first device isolation insulating layer 37 is formed in a small area in the memory cell region C2 on the semiconductor substrate 31, and the second device isolation insulating layer 39 has a large area in the peripheral circuit region P2. Is formed.

상기 제 1 및 제 2 소자격리절연층(37)(39)은 통상의 LOCOS(Local Oxidation of Silicon) 방법으로 형성되는 데, 제 1 소자격리절연층(37)은 하부가 반도체기판(31)의 표면 보다 낮으며 상부의 표면이 반도체기판(31)과 평탄되게 형성된다. 즉, 제 1 소자격리절연층(37)은 반도체기판(31)의 표면 보다 높은 부분이 제거되어 표면 보다 낮은 부분에만 형성된다. 그러므로, 제 2 소자격리절연층(39)은 제 1 소자격리절연층(37) 보다 표면이 높게 형성된다.The first and second device isolation insulating layers 37 and 39 are formed by a conventional Local Oxidation of Silicon (LOCOS) method. The first device isolation insulating layer 37 has a lower portion of the semiconductor substrate 31. It is lower than the surface and the upper surface is formed flat with the semiconductor substrate 31. That is, the first element isolation insulating layer 37 is formed only at a portion lower than the surface by removing a portion higher than the surface of the semiconductor substrate 31. Therefore, the surface of the second device isolation insulating layer 39 is higher than that of the first device isolation insulating layer 37.

상기에서 메모리셀영역(C2)에 형성된 제 1 소자격리절연층(37)이 주변회로영역(P2)에 형성된 제 2 소자격리절연층(39) 보다 표면이 낮으므로 이후에 메모리셀영역(C2)에 트랜지스터를 형성한 후 메모리셀영역(C2)과 주변회로영역(P2)에 배선을 동시에 형성할 때 단차를 감소시켜 포토리쏘그래피 공정이 용이하도록 한다.Since the first device isolation insulating layer 37 formed in the memory cell region C2 has a lower surface than the second device isolation insulating layer 39 formed in the peripheral circuit region P2, the memory cell region C2 is later formed. After forming the transistors in the transistors, the wirings are simultaneously formed in the memory cell region C2 and the peripheral circuit region P2, thereby reducing the step difference, thereby facilitating the photolithography process.

도 3a 내지 도 3c는 본 발명에 따른 반도체장치의 제조 공정도이다.3A to 3C are manufacturing process diagrams of a semiconductor device according to the present invention.

도 3a를 참조하면, 반도체기판(31) 상에 열산화 방법으로 버퍼산화막(33)을 형성하고, 이 버퍼산화막(33) 상에 CVD 방법으로 질화실리콘을 증착하여 마스크층(35)을 형성한다. 그리고, 포토리쏘그래피 방법으로 반도체기판(31)의 소자격리영역이 노출되도록 마스크층(35) 및 버퍼산화막(33)을 선택적으로 제거하여 소자격리영역과 활성영역을 한정한다.Referring to FIG. 3A, a buffer oxide film 33 is formed on a semiconductor substrate 31 by a thermal oxidation method, and silicon nitride is deposited on the buffer oxide film 33 by a CVD method to form a mask layer 35. . The device isolation region and the active region are defined by selectively removing the mask layer 35 and the buffer oxide film 33 so that the device isolation region of the semiconductor substrate 31 is exposed by the photolithography method.

도 3b를 참조하면, 소자격리영역에 노출된 반도체기판(31)을 열산화하여 메모리셀영역(C2)에 작은 영역의 제 1 소자격리절연층(37)을, 주변 회로영역(P2)에 넓은 영역의 제 2 소자격리절연층(39)을 형성한다. 이 때, 제 1 및 제 2 소자격리절연층(37)(39)은 부피 팽창하므로 표면이 반도체기판(31)의 표면 보다 높게되어 표면의 굴곡지게 된다. 잔류하는 마스크층(35) 및 버퍼산화막(33)을 습식 식각 방법으로 제거한다.Referring to FIG. 3B, the semiconductor substrate 31 exposed to the device isolation region is thermally oxidized so that the first device isolation insulating layer 37 having a small region in the memory cell region C2 is widened in the peripheral circuit region P2. The second element isolation insulating layer 39 in the region is formed. At this time, since the first and second device isolation insulating layers 37 and 39 expand in volume, the surface of the first and second device isolation insulating layers 37 and 39 is higher than the surface of the semiconductor substrate 31 to bend the surface. The remaining mask layer 35 and the buffer oxide film 33 are removed by a wet etching method.

도 3c를 참조하면, 메모리셀영역(C2)에 형성된 제 1 소자격리절연층(37)의 반도체기판(31) 보다 높은 부분을 선택적으로 습식식각하여 평탄화시킨다. 즉, 메모리셀영역(C2)에 형성된 제 1 소자격리절연층(37)이 노출되도록 주변 회로영역(P2)에 형성된 제 2 소자격리절연층(39)을 포토레지스트(도시되지 않음)로 덮고 제 1 소자격리절연층(37)의 반도체기판(31) 보다 높은 부분을 습식식각하여 평탄화시킨다.Referring to FIG. 3C, a portion higher than the semiconductor substrate 31 of the first device isolation insulating layer 37 formed in the memory cell region C2 is selectively wet etched and planarized. That is, the second device isolation insulating layer 39 formed in the peripheral circuit region P2 is covered with a photoresist (not shown) so that the first device isolation insulating layer 37 formed in the memory cell region C2 is exposed. The portion higher than the semiconductor substrate 31 of the device isolation insulating layer 37 is wet-etched to be flattened.

그러므로, 메모리셀영역(C2)은 제 1 소자격리절연층(37)이 반도체기판(31)과 평탄하며, 주변 회로영역(P2)은 제 2 소자격리절연층(39)이 반도체기판(31) 보다 높게 된다. 따라서, 이 후에, 메모리셀영역(C2)에 트랜지스터를 형성하면 제 2 소자격리절연층(39)에 의해 주변 회로영역(P2)과 단차가 감소된다.Therefore, in the memory cell region C2, the first device isolation insulating layer 37 is flat with the semiconductor substrate 31, and the peripheral circuit region P2 has the second device isolation insulating layer 39 with the semiconductor substrate 31. Higher. Therefore, after the transistor is formed in the memory cell region C2, the step difference with the peripheral circuit region P2 is reduced by the second element isolation insulating layer 39.

상술한 바와 같이 본 발명에 따른 반도체장치는 통상의 LOCOS 방법에 의해 메모리셀영역에 좁은 면적의 제 1 소자격리절연층과 주변 회로영역에 넓은 면적의 제 2 소자격리절연층을 형성한 후 제 2 소자격리절연층을 제외한 제 1 소자격리절연층의 반도체기판 보다 높은 부분을 선택적으로 제거하여 메모리셀영역의 제 1 소자격리절연층을 반도체기판과 평탄하게 하고 주변 회로영역의 제 2 소자격리절연층을 반도체기판 보다 높게 형성한다.As described above, in the semiconductor device according to the present invention, a second device isolation insulating layer having a large area in the memory cell region and a second device isolation insulating layer having a large area in the peripheral circuit region are formed by a conventional LOCOS method. By selectively removing the portion higher than the semiconductor substrate of the first isolation layer except for the isolation layer, the first isolation layer of the memory cell region is made flat with the semiconductor substrate and the second isolation layer of the peripheral circuit region is removed. Is formed higher than that of the semiconductor substrate.

따라서, 본 발명은 메모리셀영역이 주변회로영역 보다 낮으므로 메모리셀영역에 트랜지스터를 형성하면 제 2 소자격리절연층에 의해 주변 회로영역과 단차가 감소되어 이 후의 배선 공정이 용이해지며 디슁 현상을 방지할 수 있는 잇점이 있다.Therefore, in the present invention, since the memory cell region is lower than the peripheral circuit region, when the transistor is formed in the memory cell region, the step difference between the peripheral circuit region and the peripheral circuit region is reduced by the second device isolation insulating layer, thereby facilitating the subsequent wiring process and reducing the dip phenomenon. There is an advantage to avoid.

Claims (5)

메모리셀영역 및 주변회로영역을 갖는 반도체기판과,A semiconductor substrate having a memory cell region and a peripheral circuit region; 상기 반도체기판의 메모리셀영역에 하부가 상기 반도체기판의 표면 보다 낮으며 상부의 표면이 상기 반도체기판과 평탄되게 형성된 제 1 소자격리절연층과,A first device isolation insulating layer in which a lower portion of the memory cell region of the semiconductor substrate is lower than a surface of the semiconductor substrate and an upper surface thereof is flush with the semiconductor substrate; 상기 반도체기판의 주변회로영역에 상부 표면이 상기 반도체기판의 표면 보다 높게 형성된 제 2 소자격리절연층을 포함하는 반도체장치.And a second device isolation insulating layer having an upper surface higher than that of the semiconductor substrate in a peripheral circuit region of the semiconductor substrate. 청구항 1에 있어서 상기 제 1 및 제 2소자격리절연층이 LOCOS(Local Oxidation of Silicon) 방법으로 형성되되 상기 제 1 소자격리절연층의 상기 반도체기판의 표면 보다 높은 부분이 선택적으로 식각되어 형성된 반도체장치.The semiconductor device of claim 1, wherein the first and second device isolation insulating layers are formed by a local oxide of silicon (LOCOS) method, and a portion higher than the surface of the semiconductor substrate of the first device isolation insulating layer is selectively etched. . 메모리셀영역 및 주변회로영역을 갖는 반도체기판 상의 소정 부분에 마스크층을 형성하여 상기 반도체기판의 상기 메모리셀영역과 상기 주변회로영역의 각각의 소정 부분을 노출시켜 좁은 면적의 제 1 소자격리영역과 넓은 면적의 제 2 소자격리영역을 한정하는 공정과,A mask layer is formed on a predetermined portion of the semiconductor substrate having a memory cell region and a peripheral circuit region to expose each of the predetermined portion of the memory cell region and the peripheral circuit region of the semiconductor substrate; Defining a second device isolation region having a large area; 상기 반도체기판의 상기 제 1 및 제 2 소자격리영역에 상기 반도체기판의 표면 보다 높은 표면을 갖는 제 1 및 제 2 소자격리절연층을 형성하는 공정과,Forming first and second device isolation insulating layers having a surface higher than that of the semiconductor substrate in the first and second device isolation regions of the semiconductor substrate; 상기 마스크층을 제거하고 상기 제 1 소자격리절연층의 상기 반도체기판 보다 높은 부분을 선택적으로 제거하는 공정을 구비하는 반도체장치의 제조방법.Removing the mask layer and selectively removing a portion higher than the semiconductor substrate of the first device isolation insulating layer. 청구항 3에 있어서 상기 제 1 및 제 2소자격리절연층을 LOCOS(Local Oxidation of Silicon) 방법으로 형성하는 반도체장치의 제조방법.4. The method of claim 3, wherein the first and second device isolation insulating layers are formed by a local oxide of silicon (LOCOS) method. 청구항 4에 있어서 상기 제 1 소자격리절연층을 선택적으로 제거하는 공정은,The process of selectively removing the first device isolation insulating layer according to claim 4, 상기 주변 회로영역에 형성된 제 2 소자격리절연층을 덮는 포토레지스트를 형성하는 단계와,Forming a photoresist covering the second device isolation insulating layer formed in the peripheral circuit region; 상기 포토레지스트를 마스크로 사용하여 상기 제 1 소자격리절연층의 상기 반도체기판 보다 높은 부분을 습식식각하는 단계와,Wet etching a portion of the first device isolation insulating layer higher than the semiconductor substrate by using the photoresist as a mask; 상기 포토레지스트를 제거하는 단계를 구비하는 반도체장치의 제조방법.Removing the photoresist.
KR1019970055148A 1997-10-27 1997-10-27 Semiconductor device and method for manufacturing the same KR100236914B1 (en)

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