JPH10261794A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a transistor having a gate length smaller than the dimension of a photoengraving transfer, and a method for its manufacture. SOLUTION: The dimensions of a gate electrode comprising an insulating film 6, a gate insulating film 2 and polysilicon 1 are determined by photoengraving. The size of gate length is determined by the thickness of the insulating film 6. Therefore, the size of gate length can be adjusted by adjusting the thickness of the insulating film 6. Hence the size of gate length can be reduced and the gate length can be made shorter than the minimum dimension of transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a transistor having a gate length shorter than a minimum dimension (transfer limit) of photolithography transfer and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view showing the structure of a conventional semiconductor device. First, the configuration of the semiconductor device of FIG. 10 will be described. A gate insulating film 92, which is an oxide film, is formed on the surface of the semiconductor substrate 97. Polysilicon 91 is formed on the surface of gate insulating film 92. Source / drain regions 95 having a structure in which the concentration of impurities varies stepwise, ie, an LDD structure, are formed below the surface of the semiconductor substrate 97 on both sides of the gate insulating film 92. Sidewalls 96 are formed on the side walls of the polysilicon 91 and the gate insulating film 92. The gate electrode includes a sidewall 96, a gate insulating film 92, and polysilicon 91. The transistor includes the gate electrode and the source / drain region 95.

Next, a method of manufacturing the semiconductor device shown in FIG.
This will be described with reference to FIGS. First, referring to FIG. 11, a gate insulating film 92 having a thickness of 50 to 100 Å is formed on the surface of semiconductor substrate 97 by using thermal oxidation. Next, polysilicon 91 having a thickness of 2000 to 3000 angstroms is formed on the surface of the gate insulating film 92 by deposition using a CVD method. Next, a photoresist 96 patterned by photolithography is formed on the surface of the polysilicon 91.

Next, referring to FIG. 12, polysilicon 91 and gate insulating film 92 are etched using photoresist 96 as a mask. Next, source / drain regions 95 are formed by implanting impurities.

Next, an oxide film having a thickness of 1000 to 2000 angstroms is formed on the semiconductor substrate 97 by deposition using a CVD method. Next, by selectively removing a part of the oxide film formed by the deposition by anisotropic dry etching, the sidewall 96 having a thickness of 0.1 to 0.15 μm is formed in a self-aligned manner. Form. The dimensions of the sidewall 96 are determined by the thickness of the oxide film formed by deposition. Next, by implanting impurities,
The structure of the source / drain region 95 is an LDD structure. Thus, the semiconductor device shown in FIG. 10 is completed.

[0006]

Conventionally, since the polysilicon 91 and the gate insulating film 92 are etched using the photoresist 96 as a mask to form a gate electrode, the dimension (gate length) of the gate insulating film 92 is The minimum dimension of the photolithographic transfer of the manufacturing equipment is the limit. The minimum size of the transfer varies depending on the manufacturing equipment, but the manufacturing equipment is i
In the case of a line stepper, it is about 0.3 to 0.4 μm. The conventional method of manufacturing a semiconductor device has a problem that a gate length shorter than a minimum dimension of transfer cannot be formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a semiconductor device having a transistor having a gate length shorter than the dimension of the transfer of photolithography and a method of manufacturing the same. With the goal.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor device including a transistor, wherein the control electrode of the transistor is a control electrode on which the control electrode of the transistor is formed. A first insulating film formed on a semiconductor substrate as an inwardly projecting side wall at a side portion of a formation region, and a gate insulating film formed on the semiconductor substrate surface sandwiched between the first insulating films And a conductive film formed on the gate insulating film sandwiched between the first insulating films.

[0009] The means for solving the problem according to claim 2 of the present invention is:
The semiconductor device further includes an impurity region formed below the surface of the semiconductor substrate below the gate insulating film.

[0010] The problem solving means according to claim 3 of the present invention is:
The semiconductor device further includes a pattern formed adjacent to the outside of the first insulating film, and a source / drain region of the transistor formed from the pattern to the inside of the semiconductor substrate.

In the means for solving problems according to claim 4 of the present invention, the pattern is formed by photolithography.

[0012] In the means for solving problems according to claim 5 of the present invention, the size of the control electrode forming region is the minimum size of the transfer of the photolithography.

[0013] In the means for solving problems according to claim 6 of the present invention, the pattern has conductivity, and further includes a wiring connected to the pattern.

The problem solving means according to claim 7 of the present invention is:
A second insulating film formed on the semiconductor substrate surface as an outwardly projecting side wall adjacent to the first insulating film, and in the semiconductor substrate surface sandwiching the control electrode formation region; And a source / drain region of the transistor formed, wherein the concentration of the source / drain region of the transistor changes stepwise.

[0015] The problem solving means according to claim 8 of the present invention is:
A method for manufacturing a semiconductor device including a transistor,
Forming a pattern on a semiconductor substrate sandwiching a control electrode formation region where a control electrode of the transistor is formed;
Forming a first insulating film on a side surface of the pattern facing the control electrode formation region on the semiconductor substrate surface; and forming a gate insulating film on the semiconductor substrate surface exposed in the control electrode formation region. Forming a film;
Forming a conductive film sandwiched between the insulating films on the gate insulating film to form a control electrode of the transistor.

According to a ninth aspect of the present invention, in the step of forming a pattern, the step of forming a pattern includes the step of forming a film on the semiconductor substrate and the step of forming a part of the film by photolithography in the control electrode formation region Removing step.

In a tenth aspect of the present invention, the size of the control electrode formation region is a minimum size of the transfer of the photolithography.

[0018] The means for solving problems according to claim 11 of the present invention further comprises a step of implanting an impurity under the gate insulating film and below the surface of the semiconductor substrate.

The means for solving the problems according to claim 12 of the present invention further comprises a step of implanting an impurity for forming a source / drain region of the transistor from the surface of the pattern.

[0020] In the means for solving problems according to claim 13 of the present invention, the pattern has conductivity, and the method further comprises a step of forming a wiring connected to the pattern.

According to a fourteenth aspect of the present invention, there is provided a method of forming a second insulating film as an outwardly convex side wall on the surface of the semiconductor substrate and adjacent to the first insulating film. And a step of implanting an impurity for forming a source / drain region of the transistor before and after the step of forming the second insulating film.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 First, Embodiment 1 of the present invention will be described. FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to the present embodiment. First, the configuration of the semiconductor device of FIG. 1 will be described. The gate electrode (control electrode) includes the insulating film 6, the gate insulating film 2, and the polysilicon 1. The transistor includes the gate electrode and the source / drain region 5. The insulating film 6 (first insulating film) is formed as an inwardly projecting side wall on the side of the region where the gate electrode is formed (control electrode forming region). Gate insulating film 2 is formed on the surface of semiconductor substrate 7 sandwiched between insulating films 6. Polysilicon 1 is formed on the surface of gate insulating film 2 sandwiched between insulating films 6. Gate insulating film 2
The source / drain region 5 is formed below the surface of the semiconductor substrate 7 on both sides of the semiconductor substrate 7.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIGS. First, referring to FIG.
The film thickness of 200 is formed on the surface of the semiconductor substrate 7 by using the CVD method.
A nitride film 3 of 0 to 3000 angstroms is deposited and formed. Next, a photoresist 4 patterned by photolithography is formed on the surface of the nitride film 3. The photoresist 4 has a space 4a corresponding to the control electrode formation region where the gate electrode of FIG. 1 is formed.

Next, referring to FIG.
The nitride film 3 is etched using the mask as a mask, and a part of the nitride film 3 is removed as the control electrode formation region 3a, so that the nitride film 3 has a pattern sandwiching the control electrode formation region 3a.

Next, referring to FIG. 4, an oxide film having a predetermined thickness (2000 to 3000 angstroms) is formed on semiconductor substrate 7 by CVD. Next, by selectively removing a part of the deposited oxide film by anisotropic etching, an insulating film (sidewall) 6 is formed on the side wall of nitride film 3 facing control electrode formation region 3a. To form The dimension L2, which is the thickness of the insulating film 6, is:
It is 0.1 to 0.15 μm. Next, a gate insulating film 2 having a thickness of 50 to 100 Å is formed on the surface of the semiconductor substrate 7 exposed in the control electrode formation region 3a by using thermal oxidation. Next, after depositing and forming polysilicon over the entire surface by using the CVD method, this is etched back by using the dry etching or the CMP method.
Polysilicon 1 (conductive film) sandwiched between insulating films 6 is formed on the surface of gate insulating film 2. The thickness of the polysilicon deposited on the entire surface is preferably 3000 to 4000 angstroms when dry etching is applied as an etch back method, and larger when CMP is applied.

Next, the nitride film 3 is removed. Next, a source / drain region 5 having an LDD structure is formed by implanting impurities. In order to form the source / drain region 5 having the LDD structure, the impurity may be implanted while changing the incident angle of the impurity with respect to the semiconductor substrate in a stepwise manner. When this source / drain region 5 is formed, the semiconductor device of FIG. 1 is completed.

The effects of the present embodiment are as follows. (1) Dimension L2 of a portion in contact with insulating film 6 and semiconductor substrate 7
Is determined by a predetermined thickness of the oxide film formed for forming the insulating film 6. Therefore, the dimension L2 can be adjusted by adjusting the above-mentioned predetermined film thickness. Therefore, the gate length (that is, L1−L2 × 2) can be reduced. Depending on the dimension L2, it is possible to make the gate length shorter than the minimum dimension of the transfer. (2) The dimension L1 of the control electrode formation region 3a in FIG. 3 is set to the minimum dimension for transfer (for example, 0.4 μm in the case of an i-line stepper).
Then, it is possible to make the gate length shorter than the minimum dimension of the transfer without adjusting the predetermined film thickness.

Embodiment 2 Next, a second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view illustrating the configuration of the semiconductor device according to the present embodiment. First, the configuration of the semiconductor device of FIG. 5 will be described. An impurity region 9 is provided below the surface of the semiconductor substrate 7 below the gate insulating film 2 to reduce the junction capacitance between the source and drain of the transistor. Other configurations are the same as those in FIG.

Next, a method of manufacturing the semiconductor device of FIG. 5 will be described. The method for manufacturing a semiconductor device according to the present embodiment adds the following processing to the method for manufacturing a semiconductor device according to the first embodiment. That is, referring to FIG. 4, after the insulating film 6 is formed and before the gate insulating film 2 is formed, channel doping is performed on the exposed lower surface of the semiconductor substrate 7.

The effects of the present embodiment are as follows in addition to (1) and (2). (3) In the structure of FIG. 1, the presence of the insulating film 6 increases the distance between the source and the drain and increases the junction capacitance between the source and the drain. Therefore, as in the structure shown in FIG. 5, by performing channel doping and forming impurities in a self-aligned manner only under the gate insulating film 2, the junction capacitance between the source and the drain can be reduced.

Embodiment 3 Next, a third embodiment of the present invention will be described. FIG. 6 is a cross-sectional view illustrating a configuration of the semiconductor device according to the present embodiment. First, the configuration of the semiconductor device of FIG. 6 will be described. The reference numerals in FIG. 6 correspond to those in FIG. The main part shown in FIG. 1 is formed in the field oxide film 8 of FIG. Conductive polysilicon 3 ′ is formed adjacent to the outside of the insulating film 6 so as to be in contact with the surface of the field oxide film 8, the surface of the semiconductor substrate 7, and the insulating film 6. An insulating film 6 'is formed so as to be in contact with the surface of field oxide film 8 and polysilicon 3'. The source / drain region 5 ′ is formed from the polysilicon 3 ′ as a pattern to the inside of the semiconductor substrate 7.

Next, a method of manufacturing the semiconductor device of FIG. 6 will be described with reference to FIG. First, referring to FIG. 7, on the surface of semiconductor substrate 7 is formed a polysilicon film having a thickness of about 1000 .ANG. Or less by using a CVD method, and a nitride film having a film thickness of 2000 to 3000 .ANG. The films are formed by deposition. The polysilicon and the nitride film correspond to the nitride film 3 in FIG. Next, similarly to FIGS. 2 and 3, a polysilicon 3 ′ and a nitride film 3 ″ are formed.

Next, insulating films 6, 6 ', gate oxide film 2, and polysilicon are formed in the same manner as described with reference to FIG. That is, the insulating film 6 serving as a sidewall is formed. The insulating film 6 'is a sidewall formed simultaneously with the insulating film 6. Next, the gate insulating film 2 is formed on the surface of the semiconductor substrate 7 exposed in the control electrode formation region. Next, polysilicon is formed by depositing polysilicon on the entire surface and then etched back to form polysilicon 1 on the surface of the gate insulating film 2 and in a portion surrounded by the insulating film 6.

Next, by removing only the nitride film 3 ″,
The polysilicon 3 'is left. Next, when the source / drain region 5 'is formed by injecting impurities from the surface of the polysilicon 3', the semiconductor device of FIG. 6 is completed.

The effects of the present embodiment are as follows in addition to (1) and (2). (4) Since the impurity is implanted from the surface of the polysilicon 3 ', the dimension L3 from the surface of the semiconductor substrate 7 to the bottom of the source / drain region 5' can be reduced. In order to obtain the effect (4), 3 ′ may be another film having no conductivity.

Embodiment 4 FIG. Next, a fourth embodiment of the present invention will be described. FIG. 8 is a cross-sectional view showing a configuration of the semiconductor device according to the present embodiment. A method for manufacturing the semiconductor device of FIG. 8 will be described. First, the semiconductor device of FIG. 6 described in the third embodiment is prepared. In the present embodiment,
3 'has conductivity like polysilicon. Next, a film thickness of about 1 is formed on the surface of the semiconductor device of FIG.
An interlayer insulating film 12 of 0000 angstroms is deposited and formed. Next, a contact hole is formed by etching the interlayer insulating film 12 so that the polysilicon 3 is exposed. Next, a contact 13 which is a wiring electrically connected to the polysilicon 3 is formed in the contact hole. Next, an aluminum wiring 13 'electrically connected to the contact 13 is formed. Aluminum wiring 13 'is electrically connected to source / drain region 5'.

The effects of the present embodiment are as follows in addition to (1) and (2). (5) In order to electrically connect the aluminum wiring 13 'to the source / drain region 5', a contact hole may be formed such that a relatively large area of the polysilicon 3 'is exposed. Assuming that the polysilicon 3 'is not formed, the aluminum wiring 13' is connected to the source / drain region 5 '.
In order to electrically connect with the contact hole, it is necessary to form a contact hole such that a relatively narrow source / drain region 5 'is exposed. Thus, the presence of the polysilicon 3 ′ increases the margin of the position where the contact hole is formed.

(6) The contact 13 is made of polysilicon 3 '
, The occurrence of a leak current flowing from the contact 13 to the semiconductor substrate 7 can be prevented. Assuming that the polysilicon 3 'is not formed, the contact 13 may be connected to the boundary between the field oxide film 8 and the semiconductor substrate 7, and a leak current (junction leak) may occur. As described above, the presence of the polysilicon 3 ′ can prevent generation of a leak current.

Embodiment 5 Next, a fifth embodiment of the present invention will be described. FIG. 9 is a cross-sectional view showing a configuration of the semiconductor device according to the present embodiment. A method for manufacturing the semiconductor device of FIG. 9 will be described. First, the semiconductor device of FIG. 1 described in the first embodiment is prepared. Next, a TEOS oxide film having a thickness of 1000 to 2000 angstroms is deposited and formed using a CVD method. Next, by selectively removing a part of the TEOS oxide film by anisotropic etching, an insulating film (a 0.1-0.15 μm-thick side wall) is formed on the side wall of the insulating film 6. 2 ''). The insulating film 6 '' is formed as an outwardly convex side wall adjacent to the insulating film 6. Next, impurities are implanted into the source / drain regions 5.

The effects of the present embodiment are as follows in addition to (1) and (2). (7) The structure of the source / drain region 5 can be a structure in which the concentration of impurities is different stepwise, that is, an LDD structure. In addition, in order to form the LDD structure in FIG. 1, it is necessary to implant the impurity while changing the incident angle of the impurity to the semiconductor substrate in a stepwise manner. On the other hand, in FIG. 9, the source / drain region can have an LDD structure in a self-aligned manner without changing the incident angle of the impurity with respect to the semiconductor substrate in a stepwise manner.

Modification Example The second embodiment may be applied to the third embodiment and the fifth embodiment used in the third embodiment and the fourth embodiment.

[0042]

According to the first aspect of the present invention, the size of the gate insulating film formed in the control electrode formation region, that is, the gate length is determined by the thickness of the first insulating film. Therefore, the size of the gate length has an effect that the gate length can be reduced by adjusting the thickness of the first insulating film.

According to the second aspect of the present invention, there is an effect that the junction capacitance between the source and the drain is small.

According to the third aspect of the present invention, there is an effect that the dimension from the surface of the semiconductor substrate to the bottom of the source / drain region is short.

According to the fourth aspect of the present invention, there is an effect that the gate length can be made shorter than the dimension of transfer of photolithography.

According to the fifth aspect of the present invention, there is an effect that the gate length can be made shorter than the minimum dimension of the transfer of photolithography.

According to the sixth aspect of the present invention, there is an effect that the margin at the position where the wiring is formed is large.

According to the seventh aspect of the present invention, the provision of the second insulating film has an effect that the structure of the source / drain region can be made to have a structure in which the impurity concentration is varied stepwise in a self-aligned manner. .

According to the eighth aspect of the present invention, the size of the gate insulating film formed in the control electrode forming region, that is, the size of the gate length is determined by the thickness of the first insulating film. Therefore, by forming the first insulating film by adjusting the thickness, a semiconductor device including a transistor having a control electrode with a short gate length can be obtained.

According to the ninth aspect of the present invention, it is possible to obtain a semiconductor device having a transistor having a control electrode whose gate length is shorter than the dimension of transfer of photolithography.

According to the tenth aspect of the present invention, it is possible to obtain a semiconductor device having a transistor having a control electrode whose gate length is shorter than the minimum dimension of photolithography transfer.

According to the eleventh aspect of the present invention, it is possible to obtain a semiconductor device having a transistor having a small junction capacitance between the source and the drain.

According to the twelfth aspect of the present invention, it is possible to obtain a semiconductor device having a short dimension from the surface of the semiconductor substrate to the bottom of the source / drain region.

According to the thirteenth aspect of the present invention, it is possible to obtain a semiconductor device having a large margin at a position where a wiring is formed.

According to the fourteenth aspect of the present invention, it is possible to obtain a source / drain region which is formed in a self-aligned manner and has a structure in which the impurity concentration is varied stepwise.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor device in the first embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment of the present invention.

FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a conventional semiconductor device.

FIG. 11 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

1 polysilicon, 2 gate insulating films, 3 nitride films,
3 ′ polysilicon, 3 ″ nitride film, 4 photoresist, 5 source / drain region, 6, 6 ′ insulating film, 7
Semiconductor substrate, 8 field oxide films, 9 impurity regions.

Claims (14)

[Claims] 1. A semiconductor device provided with a transistor, wherein a control electrode of the transistor is formed on a semiconductor substrate as an inwardly projecting side wall at a side of a control electrode forming region where a control electrode of the transistor is formed. A first insulating film formed on the semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate interposed between the first insulating films, and a gate insulating film interposed between the first insulating films And a conductive film formed on the semiconductor device. 2. The semiconductor device according to claim 1, further comprising an impurity region formed below the surface of the semiconductor substrate below the gate insulating film. 3. The semiconductor device according to claim 1, further comprising: a pattern formed outside and adjacent to the first insulating film; and a source / drain region of the transistor formed from the pattern to the inside of the semiconductor substrate. Item 3. The semiconductor device according to item 1 or 2. 4. The semiconductor device according to claim 3, wherein said pattern is formed by photolithography. 5. The semiconductor device according to claim 4, wherein the size of the control electrode formation region is the minimum size of the photolithography transfer. 6. The pattern has conductivity, and further comprises a wiring connected to the pattern.
6. The semiconductor device according to any one of items 1 to 5, 7. The method according to claim 1, wherein the first substrate is located on a surface of the semiconductor substrate.
A second insulating film formed as an outwardly convex side wall adjacent to the insulating film, and a source / drain region of the transistor formed in the semiconductor substrate surface sandwiching the control electrode formation region; 3. The semiconductor device according to claim 1, further comprising: a source / drain region of the transistor, the concentration of which is changed stepwise. 8. A method for manufacturing a semiconductor device having a transistor, comprising: a step of forming a pattern on a semiconductor substrate sandwiching a control electrode formation region where a control electrode of the transistor is formed; Forming a first insulating film on a side wall of the pattern facing the control electrode forming region; and forming a gate insulating film on the semiconductor substrate surface exposed in the control electrode forming region. Forming a conductive film sandwiched between the first insulating films on the gate insulating film, thereby forming a control electrode of the transistor. 9. The step of forming the pattern includes the steps of: forming a film on the semiconductor substrate; and removing a part of the film as the control electrode formation region by photolithography. 9. The method for manufacturing a semiconductor device according to item 8. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the size of the control electrode formation region is the minimum size of the photolithography transfer. 11. The method according to claim 8, further comprising a step of implanting an impurity under the surface of the semiconductor substrate under the gate insulating film.
11. The method for manufacturing a semiconductor device according to any one of items 10 to 10. 12. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of implanting an impurity for forming a source / drain region of said transistor from a surface of said pattern. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the pattern has conductivity, and further comprising a step of forming a wiring connected to the pattern. 14. A step of forming a second insulating film as an outwardly convex side wall on the surface of the semiconductor substrate and adjacent to the first insulating film; and forming the second insulating film. Before and after the step, further comprising a step of implanting an impurity for forming a source / drain region of the transistor.
The method for manufacturing a semiconductor device according to any one of the above.