KR100477786B1 - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
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- KR100477786B1 KR100477786B1 KR10-2000-0080778A KR20000080778A KR100477786B1 KR 100477786 B1 KR100477786 B1 KR 100477786B1 KR 20000080778 A KR20000080778 A KR 20000080778A KR 100477786 B1 KR100477786 B1 KR 100477786B1
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- interlayer insulating
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 콘택홀의 크기를 최소화하면서 콘택홀에 금속막을 완전 매립시키도록 한 반도체소자의 콘택 형성 방법에 관한 것으로, 소정 공정이 완료된 반도체기판 상에 제1층간절연막을 형성하는 단계, 상기 제1층간절연막 상에 제1콘택마스크를 형성하는 단계, 상기 제1콘택마스크를 이용하여 상기 제1층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 전면에 금속막을 형성하는 단계, 상기 금속막 상에 상기 제1콘택마스크보다 상대적으로 폭이 넓은 제2콘택마스크를 형성하는 단계, 상기 제2콘택마스크를 이용하여 상기 금속막을 식각하는 단계, 상기 식각된 금속막을 포함한 전면에 제2층간절연막을 형성하는 단계, 및 상기 제2층간절연막을 화학적기계적연마하여 상기 금속막 표면을 노출시키는 단계를 포함하여 이루어진다.The present invention relates to a method of forming a contact of a semiconductor device in which a metal film is completely embedded in a contact hole while minimizing the size of the contact hole, the method comprising: forming a first interlayer insulating film on a semiconductor substrate on which a predetermined process is completed; Forming a first contact mask on the insulating film, forming a contact hole by selectively etching the first interlayer insulating film using the first contact mask, forming a metal film on the entire surface including the contact hole; Forming a second contact mask that is relatively wider than the first contact mask on the metal film, etching the metal film by using the second contact mask, and a second surface on the entire surface including the etched metal film Forming an interlayer insulating film; and exposing the surface of the metal film by chemical mechanical polishing of the second interlayer insulating film. Eojinda.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 반도체기판의 손상을 방지하면서 콘택홀의 접촉 면적을 감소시키도록 한 반도체소자의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device to reduce a contact area of a contact hole while preventing damage to the semiconductor substrate.
일반적으로 반도체소자의 콘택홀 제조 방법은 PMD(Polysilicon to Metal Dieelectric)를 형성한 후 PMD층을 선택적으로 식각하여 금속배선용 콘택홀을 형성한다.In general, a method of manufacturing a contact hole in a semiconductor device forms a PMD (Polysilicon to Metal Dieelectric) and then selectively etches the PMD layer to form a contact hole for metal wiring.
도 1은 종래기술에 따른 콘택 형성 방법을 간략히 도시한 도면이다.1 is a view schematically showing a contact forming method according to the prior art.
도 1에 도시된 바와 같이, 반도체기판(11)의 소정 부분에 소자간 격리를 위한 필드산화막(12)을 형성하고, 반도체기판(11)상에 게이트산화막(13), 게이트전극 (14)을 형성한다. 게이트전극(14)을 마스크로 이용하거나, 또는 추가로 이온주입 마스크를 이용한 불순물 이온주입으로 반도체기판(11)에 LDD(Lightly Doped Drain) 영역을 형성하고, 전면에 측벽용 절연막을 증착 및 전면식각하여 게이트전극(14)의 양측벽에 접하는 스페이서(15)를 형성한다. 계속해서, 고농도 불순물 이온주입으로 LDD 구조의 소스/드레인(16)을 형성한다.As shown in FIG. 1, a field oxide film 12 for inter-element isolation is formed on a predetermined portion of the semiconductor substrate 11, and the gate oxide film 13 and the gate electrode 14 are formed on the semiconductor substrate 11. Form. The LDD (Lightly Doped Drain) region is formed on the semiconductor substrate 11 by using the gate electrode 14 as a mask or by additionally implanting impurity ions using an ion implantation mask. Thus, spacers 15 in contact with both side walls of the gate electrode 14 are formed. Subsequently, the source / drain 16 of the LDD structure is formed by the implantation of high concentration impurity ions.
계속해서, 게이트전극(14)을 포함한 전면에 PMD(17)을 형성한 후, PMD(17)상에 콘택마스크를 형성하고, 콘택마스크를 이용하여 PMD(17)을 선택적으로 식각하여 소스/드레인(16)의 소정 부분이 노출되는 콘택홀을 형성한다.Subsequently, after the PMD 17 is formed on the entire surface including the gate electrode 14, a contact mask is formed on the PMD 17, and the PMD 17 is selectively etched using the contact mask to selectively source / drain. A contact hole through which a predetermined portion of 16 is exposed is formed.
콘택홀에 매립되어 소스/드레인(16)에 접속되는 금속배선(18)을 형성한다.A metal wiring 18 is formed in the contact hole and connected to the source / drain 16.
그러나, 상술한 종래기술은 PMD층의 두께가 두꺼워서 콘택홀 형성시 콘택홀 상부와 바닥의 면적이 다를뿐 아니라, 금속배선막으로서 알루미늄실리콘(AlSi 1%)을 증착할 경우, 증착하는데 어려움이 있다.However, the above-described prior art has a thick PMD layer, which is difficult to deposit when not only the top and bottom areas of the contact hole are different when forming the contact hole, but also when aluminum silicon (AlSi 1%) is deposited as the metal wiring layer. .
상기한 금속배선막 증착의 어려움을 해결하기 위해 텅스텐(W)을 이용하여 콘택홀을 매립하였으나, 텅스텐을 이용하면 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 적용해야만 하기 때문에 공정에 소요되는 비용이 증가하는 문제점이 있다.In order to solve the above-mentioned difficulty in depositing the metal wiring film, the contact hole was buried using tungsten (W). There is an increasing problem.
다른 종래기술로서, 콘택홀의 크기를 줄이기 위하여 콘택홀의 측벽에 스페이서(Spacer)를 사용하여 공정을 단순화시켰지만, 레이아웃(Layout)상으로는 콘택홀 의 크기를 줄이는데 한계가 있다.As another prior art, the process is simplified by using a spacer on the sidewall of the contact hole in order to reduce the size of the contact hole, but there is a limit in reducing the size of the contact hole on the layout.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 콘택홀의 접촉 면적을 감소시키고 콘택홀내 금속배선막의 매립 불량을 방지하여 콘택저항을 감소시키는데 적합한 반도체소자의 콘택 형성 방법을 제공하는데 그 목적이 있다. The present invention has been made to solve the problems of the prior art, and provides a method for forming a contact of a semiconductor device suitable for reducing the contact resistance by reducing the contact area of the contact hole and preventing the filling of the metal wiring film in the contact hole. There is this.
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 콘택 형성 방법은 소정 공정이 완료된 반도체기판 상에 제1층간절연막을 형성하는 단계, 상기 제1층간절연막 상에 제1콘택마스크를 형성하는 단계, 상기 제1콘택마스크를 이용하여 상기 제1층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 전면에 금속막을 형성하는 단계, 상기 금속막 상에 상기 제1콘택마스크보다 상대적으로 폭이 넓은 제2콘택마스크를 형성하는 단계, 상기 제2콘택마스크를 이용하여 상기 금속막을 식각하는 단계, 상기 식각된 금속막을 포함한 전면에 제2층간절연막을 형성하는 단계, 및 상기 제2층간절연막을 화학적기계적연마하여 상기 금속막 표면을 노출시키는 단계를 포함하는 것을 특징으로 한다.The method of forming a contact of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a first interlayer insulating film on a semiconductor substrate, a predetermined process is completed, forming a first contact mask on the first interlayer insulating film, Selectively etching the first interlayer dielectric layer using the first contact mask to form a contact hole, forming a metal layer on the entire surface including the contact hole, and forming a contact layer on the metal layer relative to the first contact mask. Forming a wide second contact mask, etching the metal film using the second contact mask, forming a second interlayer insulating film on the entire surface including the etched metal film, and the second interlayer And chemically polishing the insulating film to expose the surface of the metal film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 콘택홀 형성 방법을 도시한 도면이다. 2A to 2D illustrate a method of forming a contact hole according to an exemplary embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(21)의 전면에 웰이온을 주입한 후, 반도체기판(21)의 소정 부분에 소자간 격리를 위한 필드산화막(22)을 형성하고, 반도체기판(21)상에 게이트산화막(23)을 형성한 후 문턱전압 조절을 위한 문턱전압이온을 주입한다. 이 때, 문턱전압 조절 이온 주입 공정은 게이트산화막(23) 형성전에 실시할 수 있다.As shown in FIG. 2A, after implanting well ions into the entire surface of the semiconductor substrate 21, a field oxide film 22 for isolation between devices is formed in a predetermined portion of the semiconductor substrate 21, and the semiconductor substrate 21 is formed. After the gate oxide layer 23 is formed on the gate oxide layer 23, threshold voltage ions are injected to control the threshold voltage. At this time, the threshold voltage adjusting ion implantation step can be performed before the gate oxide film 23 is formed.
계속해서, 게이트산화막(23)상에 게이트전극용 폴리실리콘을 증착한 다음, 도핑 및 패터닝하여 게이트전극(24)을 형성하고, 게이트전극(24)을 마스크로 이용하거나 추가의 이온주입 마스크를 이용하여 저농도 불순물 이온주입을 실시한다. 이러한 저농도 불순물 이온주입으로 반도체기판(21)에 LDD(Lightly Doped Drain) 영역이 형성된다.Subsequently, polysilicon for the gate electrode is deposited on the gate oxide film 23, and then doped and patterned to form the gate electrode 24, using the gate electrode 24 as a mask or using an additional ion implantation mask. Low concentration impurity ion implantation is performed. Lightly doped drain (LDD) regions are formed in the semiconductor substrate 21 by the low concentration impurity ion implantation.
게이트전극(24)의 양측벽에 접하는 스페이서(25)를 형성한 후, 스페이서(25) 및 게이트전극(24)을 마스크로 이용하거나, 추가의 이온주입마스크를 이용하여 고농도 불순물을 이온주입하여 LDD 구조의 소스/드레인 영역(26)을 형성한다.After forming the spacers 25 in contact with both side walls of the gate electrode 24, the LDD is ion-implanted with a high concentration of impurities using the spacer 25 and the gate electrode 24 as a mask or an additional ion implantation mask. Source / drain regions 26 of the structure are formed.
전면에 제 1 PMD(27)을 1000Å∼2000Å의 두께로 형성하고, 첫 번째 콘택마스크를 이용하여 제 1 PMD(27)을 선택적으로 식각하여 소스/드레인 영역(26)의 소정 부분을 노출시키는 콘택홀을 형성한 다음, 첫 번째 콘택마스크를 제거한다. 이 때, 제 1 PMD(27) 형성시, 후속 두 번째 콘택 식각시의 금속막과의 선택비가 매우 양호한 막을 사용한다.The first PMD 27 is formed on the entire surface with a thickness of 1000 GPa to 2000 GPa, and the first PMD 27 is selectively etched using the first contact mask to expose a predetermined portion of the source / drain region 26. After the hole is formed, the first contact mask is removed. At this time, when forming the first PMD 27, a film having a very good selectivity with respect to the metal film during subsequent second contact etching is used.
한편, 제 1 PMD(27) 식각후, 콘택홀을 줄이는데 한계가 있어 통상적으로 소스/드레인 영역(26)의 접합 누설을 방지하기 위하여 제 1 콘택홀 형성후 플러그 공정을 실시하는데, 이 공정은 선택적으로 실시한다. 즉, 공정 마진이 충분하다면 금속 증착전에 플러그 공정을 진행하지 않아도 되지만, 더욱 더 칩 크기를 줄이기 위해서는 플러그 공정을 금속 증착전에 진행하므로서 칩 밀도 확보에 유리하다.On the other hand, after etching the first PMD 27, there is a limit to reducing the contact hole, so that a plug process is performed after the first contact hole is formed in order to prevent junction leakage of the source / drain region 26. To be carried out. In other words, if the process margin is sufficient, the plug process does not need to be performed before metal deposition, but in order to further reduce the chip size, it is advantageous to secure the chip density by performing the plug process before the metal deposition.
도 2b에 도시된 바와 같이, 콘택홀을 포함한 전면에 제 1 금속막(28)을 증착하는데, 이러한 제 1 금속막(28)은 콘택홀 접속을 위함이다. As shown in FIG. 2B, the first metal film 28 is deposited on the entire surface including the contact hole, and the first metal film 28 is for contact hole connection.
두 번째 콘택마스크를 이용하여 제 1 금속막(28)을 선택적으로 식각하는데, 이 때 두 번째 콘택마스크는 첫 번째 콘택마스크를 반전시킨 마스크를 이용하며, 제 1 금속막(28)이 제 1 PMD(27)상에 남아 있음으로 인해 후속 공정 진행시 안정적으로 견딜 수 있다. 여기서, 두 번째 콘택마스크는 네가티브 감광막을 사용할 수 있는데, 재차 콘택 식각 진행시 바이어스를 이용하여 실제 콘택홀보다 크게 정의하면 실제 반도체기판과 접합하는 콘택홀은 작고 제 1 PMD(27)상의 제 1 금속막(28)은 이보다 두꺼워져 저항을 최소화할 수 있다.The first metal layer 28 is selectively etched using a second contact mask, wherein the second contact mask uses a mask in which the first contact mask is inverted, and the first metal layer 28 uses the first PMD. Remaining on (27) allows it to withstand subsequent processing. In this case, the second contact mask may use a negative photoresist film. When the contact etching process is performed, the second contact mask is larger than the actual contact hole by using a bias, and the contact hole to be bonded to the actual semiconductor substrate is small and the first metal on the first PMD 27 is used. Membrane 28 may be thicker than this to minimize resistance.
도 2c에 도시된 바와 같이, 제 2 PMD(29), 제 3 PMD(30)를 형성하되, 제 2 PMD(29)는 SOG(Spin On Glass)와 산화막의 적층막을 이용한다.As shown in FIG. 2C, the second PMD 29 and the third PMD 30 are formed, and the second PMD 29 uses a stacked film of spin on glass (SOG) and an oxide film.
도 2d에 도시된 바와 같이, 화학적기계적연마를 실시하여 제 3 PMD(30)를 평탄화하므로써 제 1 금속막(28)의 표면을 노출시킨다. 여기서, 도면부호 30a는 평탄화된 제 3 PMD이다.As shown in FIG. 2D, the surface of the first metal film 28 is exposed by chemical mechanical polishing to planarize the third PMD 30. Here, reference numeral 30a denotes a planarized third PMD.
도면에 도시되지 않았지만, 후속 공정으로 노출된 제 1 금속막상에 금속배선간 접속을 위한 제 2 금속막을 증착한 후 선택적으로 식각한다.Although not shown in the drawings, a second metal film for connection between metal lines is deposited on the first metal film exposed in a subsequent process, and then selectively etched.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체소자의 콘택 형성 방법은 설정된 콘택홀 형성전에 얇은 PMD를 형성 및 식각한 후 금속막을 매립시키므로써 콘택홀의 완전한 금속막 매립을 구현할 수 있어 콘택저항을 최소화시킬 뿐만 아니라 콘택홀 면적을 줄일 수 있는 효과가 있다. The method of forming a contact of the semiconductor device of the present invention as described above can implement a complete metal film filling of the contact hole by forming and etching a thin PMD before forming the set contact hole, thereby minimizing the contact resistance. It is effective to reduce the hole area.
또한, 플러그 공정에서 사용하는 텅스텐을 사용하지 않고도 안정된 콘택홀을 형성할 수 있는 효과가 있다.In addition, there is an effect that can form a stable contact hole without using tungsten used in the plug process.
도 1은 종래기술에 따른 반도체 소자의 콘택 형성 방법을 간략히 도시한 도면,1 is a view briefly illustrating a method for forming a contact of a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 도시한 도면.2A to 2D illustrate a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 게이트산화막 24 : 게이트전극23: gate oxide film 24: gate electrode
25 : 스페이서 26 : LDD구조의 소스/드레인25: spacer 26: source / drain of LDD structure
27 : 제 1 PMD 28 : 제 1 금속막27: first PMD 28: first metal film
29 : 제 2 PMD 30 : 제 3 PMD29: 2nd PMD 30: 3rd PMD
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07115093A (en) * | 1993-10-20 | 1995-05-02 | Nkk Corp | Multilayer wiring structure and manufacture thereof |
| KR0154804B1 (en) * | 1994-09-29 | 1998-12-01 | 김광호 | Fabrication method of semiconductor device |
| KR19990055129A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method for forming contact hole in semiconductor device |
| US5950081A (en) * | 1997-11-08 | 1999-09-07 | Winbond Electronics Corporation | Method of fabricating semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07115093A (en) * | 1993-10-20 | 1995-05-02 | Nkk Corp | Multilayer wiring structure and manufacture thereof |
| KR0154804B1 (en) * | 1994-09-29 | 1998-12-01 | 김광호 | Fabrication method of semiconductor device |
| US5950081A (en) * | 1997-11-08 | 1999-09-07 | Winbond Electronics Corporation | Method of fabricating semiconductor |
| KR19990055129A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Method for forming contact hole in semiconductor device |
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