KR100273685B1 - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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KR100273685B1
KR100273685B1 KR1019970077884A KR19970077884A KR100273685B1 KR 100273685 B1 KR100273685 B1 KR 100273685B1 KR 1019970077884 A KR1019970077884 A KR 1019970077884A KR 19970077884 A KR19970077884 A KR 19970077884A KR 100273685 B1 KR100273685 B1 KR 100273685B1
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forming
film
layer
insulating film
conductive
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KR1019970077884A
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Korean (ko)
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KR19990057805A (en
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박재범
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A fabrication method of semiconductor devices is provided to prevent a short of contact holes and easily achieve a processing margin by using a self-aligned contact formation processes. CONSTITUTION: A gate electrode(23) surrounded by a first insulating layer(24) is formed on a silicon substrate(20) having source and drain regions(26,26'). By forming and selectively etching a second insulating layer(27), the surface of the silicon substrate of a contact region is exposed. After forming a first conductive layer(28) on the resultant structure, a sacrificial oxide(29) is formed on the first conductive layer(28). A contact hole is formed by selectively etching the sacrificial oxide(29) using the first conductive layer(28) as an etch stopper. A contact layer(30) is formed by filling a second conductive layer into the contact hole. After removing the sacrificial layer(29), the exposed first conductive layer is removed.

Description

반도체 장치 제조 방법{Method for forming semiconductor device}Method for manufacturing semiconductor device

본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 반도체 장치의 자기정렬 콘택 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method of forming self-aligned contacts in a semiconductor device.

반도체 장치가 고집적화에 되어 감에 따라 패턴의 선폭 및 패턴간의 거리가 좁아지고 있어 콘택홀 형성시 마진이 줄어들고 있다.As semiconductor devices become more integrated, the line width of the patterns and the distance between the patterns are narrowing, and thus margins are reduced when forming contact holes.

이하, 첨부된 도면 도1a 내지 도1c를 참조하여 종래기술의 문제점을 살펴본다.Hereinafter, with reference to the accompanying drawings Figures 1a to 1c looks at the problems of the prior art.

먼저, 도1a에 도시된 바와 같이 실리콘기판(10) 상에 소자분리막(11), 게이트 산화막(12) 및 게이트 전극(13)을 형성하고, 이온 주입을 실시하여 저농도 소오스/드레인 영역(16)을 형성한다. 이어서, 게이트 전극(13) 측벽에 스페이서를 형성하기 위하여 화학기상증착 방법으로 산화막을 증착하고, 산화막을 전면성 건식 식각하여 게이트 전극(13) 측벽에 산화막 스페이서(15)를 형성한 다음, 이온 주입을 실시하여 고농도 소오스/드레인 영역(16')을 형성함으로써 LDD(Lightly Doped Drain) 구조의 전계효과 트랜지스터를 형성한다. 미설명 도면 부호 '14'는 절연막을 나타낸다.First, as shown in FIG. 1A, an isolation layer 11, a gate oxide layer 12, and a gate electrode 13 are formed on a silicon substrate 10, and ion implantation is performed to form a low concentration source / drain region 16. To form. Subsequently, an oxide layer is deposited by chemical vapor deposition to form a spacer on the sidewall of the gate electrode 13, and the oxide layer is entirely dry-etched to form the oxide spacer 15 on the sidewall of the gate electrode 13, followed by ion implantation. By forming a high concentration source / drain region 16 ′, a field effect transistor having an LDD (Lightly Doped Drain) structure is formed. Unexplained reference numeral 14 denotes an insulating film.

다음으로, 도1b에 도시된 바와 같이 전체 구조 상부에 층간절연막(17)을 형성하고 콘택홀 형성을 위한 마스크(도시되지 않음)를 사용하여 층간절연막(17)을 선택적으로 식각함으로써 게이트 전극(13)과 일정거리를 유지하는 콘택홀(h)을 형성한다.Next, as shown in FIG. 1B, the interlayer insulating layer 17 is formed over the entire structure, and the gate electrode 13 is selectively etched by selectively etching the interlayer insulating layer 17 using a mask (not shown) for forming a contact hole. ) And a contact hole h is maintained.

다음으로, 도1c에 도시한 바와 같이 전체 구조 상부에 전도막(18)을 증착하고 에치백(etch back)하여 콘택홀 내부에만 전도막(18)이 남도록 한다.Next, as illustrated in FIG. 1C, the conductive film 18 is deposited and etched back on the entire structure so that the conductive film 18 remains only inside the contact hole.

전술한 바와 같이 이루어지는 종래 기술은 게이트 전극(13)과 콘택홀(h)이 일정 간격을 유지해야하기 때문에 반도체 장치의 크기를 감소시키는데 걸림돌이 되고 있으며, 게이트 전극과 콘택홀 내부를 채우는 전도막과의 단락 가능성이 항상 존재하여 충분한 공정 마진을 확보하기 어려운 문제점을 가지고 있다.The prior art made as described above is an obstacle to reducing the size of the semiconductor device because the gate electrode 13 and the contact hole h must be kept at a predetermined distance, and the conductive film filling the gate electrode and the contact hole inside and The possibility of a short circuit always exists, which makes it difficult to secure sufficient process margin.

상기와 같은 문제점을 해결하기 위한 본 발명은 전도막 패턴과 그에 이웃하여 형성되는 콘택홀의 단락을 방지함과 동시에 공정 마진을 확보할 수 있는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a short circuit between a conductive film pattern and a contact hole formed adjacent thereto and at the same time securing a process margin.

도1a 내지 도1c는 종래 기술에 따른 반도체 장치 제조 공정 단면도1A to 1C are cross-sectional views of a semiconductor device manufacturing process according to the prior art.

도2a 내지 도2f는 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도2A through 2F are cross-sectional views of a semiconductor device manufacturing process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings

20: 실리콘 기판 21: 소자분리막20: silicon substrate 21: device isolation film

22: 게이트 산화막 23: 게이트 전극22: gate oxide film 23: gate electrode

24: 제1 절연막 25: 스페이서24: first insulating film 25: spacer

26, 26': 소오스/드레인 영역 27: 제2 절연막26, 26 ': source / drain region 27: second insulating film

28: 식각정지 전도막 29: 희생산화막28: etch stop conductive film 29: sacrificial oxide film

30: 콘택층 31: 제3 절연막30: contact layer 31: third insulating film

상기와 같은 목적을 달성하기 위한 본 발명은, 그 상부 및 측벽이 제1 절연막으로 둘러싸인 게이트 전극을 반도체 기판 상에 형성하고, 상기 반도체 기판 표면으로부터 소정의 깊이를 갖는 소오스 및 드레인 영역을 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 제2 절연막을 형성하고, 상기 제2 절연막을 선택적으로 식각하여 콘택 영역의 상기 반도체 기판 표면을 노출시키는 제2 단계; 상기 제2 단계가 완료된 전체 구조 상에 제1 전도막을 형성하는 제3 단계; 상기 제3 단계가 완료된 전체 구조 상에 상기 제1 전도막과 식각 특성이 다른 희생막을 형성하고, 상기 제1 전도막을 식각 정지층으로 이용하여 상기 희생막을 선택적으로 식각해서 상기 콘택 영역의 상기 제1 전도막을 노출시키는 개구부를 형성하는 제4 단계; 상기 개구부 내에 제2 전도막을 매립하여 콘택층을 형성하는 제5 단계; 상기 희생막을 제거하여 상기 콘택층으로 덮이지 않은 상기 제1 전도막을 노출시키는 제6 단계; 상기 제6 단계에 의해 노출된 상기 제1 전도막을 제거하는 제7 단계; 및 제7 단계가 완료된 전체 구조 상에 제3 절연막을 형성하는 제8 단계를 포함하는 반도체 장치 제조 방법을 제공한다.The present invention for achieving the above object is formed by forming a gate electrode on the semiconductor substrate, the top and sidewalls of which are surrounded by the first insulating film, and the source and drain regions having a predetermined depth from the surface of the semiconductor substrate; Stage 1; Forming a second insulating film on the entire structure in which the first step is completed, and selectively etching the second insulating film to expose a surface of the semiconductor substrate in the contact region; A third step of forming a first conductive film on the entire structure in which the second step is completed; Forming a sacrificial layer having different etching characteristics from the first conductive layer on the entire structure of which the third step is completed, and selectively etching the sacrificial layer using the first conductive layer as an etch stop layer to form the sacrificial layer in the first region of the contact region. Forming a opening exposing the conductive film; A fifth step of forming a contact layer by filling a second conductive film in the opening; Removing the sacrificial layer to expose the first conductive layer not covered with the contact layer; A seventh step of removing the first conductive film exposed by the sixth step; And an eighth step of forming a third insulating film on the entire structure where the seventh step is completed.

이하, 본 발명의 일실시예에 따른 반도체 장치 제조 공정 단면도인 도2a 내지 도2f를 참조하여 본 발명을 설명한다.Hereinafter, the present invention will be described with reference to FIGS. 2A to 2F, which are cross-sectional views of a semiconductor device manufacturing process according to an exemplary embodiment.

먼저, 도2a에 도시한 바와 같이 실리콘 기판(20)에 소자분리막(21)을 형성한 다음, 게이트 산화막(22) 및 게이트 전극(23)용 전도막을 증착하고, 상기 게이트 전극(23)용 전도막 상에 제1 절연막(24)을 형성한 후, 게이트 전극 형성을 위한 마스크를 사용하여 제1 절연막(24) 및 게이트 전극(23)용 전도막을 차례로 식각하여 게이트 전극(23)을 형성한다.First, as shown in FIG. 2A, the device isolation film 21 is formed on the silicon substrate 20, and then a conductive film for the gate oxide film 22 and the gate electrode 23 is deposited, and the conductive film for the gate electrode 23 is formed. After the first insulating film 24 is formed on the film, the first insulating film 24 and the conductive film for the gate electrode 23 are sequentially etched using a mask for forming the gate electrode to form the gate electrode 23.

이어서, 이온 주입 공정을 실시하여 저도핑 드레인(lightly doped drain, LDD) 구조의 저농도 소오스/드레인 영역(26)을 형성하고, 전체 구조 상에 절연막을 증착하고 전면 건식 식각하여 게이트 전극(23) 측벽에 스페이서(25)를 형성한 후, 이온 주입을 실시하여 고농도 소오스/드레인 영역(26')을 형성하고 열처리하여 LDD 구조를 완성한다.Subsequently, an ion implantation process is performed to form a low concentration source / drain region 26 having a lightly doped drain (LDD) structure, an insulating film is deposited on the entire structure, and the surface is dry-etched to form a sidewall of the gate electrode 23. After the spacer 25 is formed in the ion source, ion implantation is performed to form a high concentration source / drain region 26 'and heat treatment to complete the LDD structure.

다음으로, 도2b에 도시한 바와 같이 이후에 형성될 식각완충용 전도막과 소스/드레인 영역(26, 26')과의 접촉 방지하기 위하여 전체 구조 상에 얇은 제2 절연막(27)을 형성하고, 게이트 산화막(22) 및 제2 절연막(27)을 선택적으로 식각하여 콘택영역의 실리콘 기판(20) 표면(소오스 또는 드레인)을 노출시킨다. 이때, 콘택과 게이트 전극(23)이 종래 기술처럼 일정 간격을 유지하지 않아도 된다. 즉, 이후에 형성될 콘택과 게이트 전극이 중첩되어도 무방하다. 한편, 상기 제2 절연막(27) 및 게이트 산화막(22)이 충분히 얇기 때문에 제2 절연막(27) 및 게이트 산화막(22) 식각 과정에서 제1 절연막(24) 및 스페이서(25)가 손상되는 정도는 크지 않다.Next, as shown in FIG. 2B, a thin second insulating layer 27 is formed on the entire structure to prevent contact between the etch buffer conductive layer to be formed later and the source / drain regions 26 and 26 ′. The gate oxide film 22 and the second insulating film 27 are selectively etched to expose the surface (source or drain) of the silicon substrate 20 in the contact region. At this time, the contact and the gate electrode 23 do not have to maintain a constant interval as in the prior art. That is, the contact to be formed later and the gate electrode may overlap. Meanwhile, since the second insulating film 27 and the gate oxide film 22 are sufficiently thin, the degree of damage of the first insulating film 24 and the spacer 25 during the etching process of the second insulating film 27 and the gate oxide film 22 may be reduced. not big.

다음으로, 도2c에 도시한 바와 같이 전체 구조 상에 식각정지 전도막(28)을 증착하고, 식각정지 전도막(28) 상에 상기 식각정지 전도막(28)과 식각 특성이 다른 희생산화막(29)을 형성한다. 이어서, 희생산화막(29)을 선택적으로 식각하여 콘택 영역의 식각정지 전도막(28)을 노출시키는 개구부를 형성한다.Next, as illustrated in FIG. 2C, an etch stop conductive film 28 is deposited on the entire structure, and on the etch stop conductive film 28, the sacrificial oxide film having different etching characteristics from the etch stop conductive film 28 is formed. 29). Subsequently, the sacrificial oxide film 29 is selectively etched to form an opening for exposing the etch stop conductive film 28 in the contact region.

다음으로, 도2d에 도시한 바와 같이 전체 구조 상에 전도막(30)을 증착하고 전면 식각 또는 화학기계적 연마 공정을 실시하여 상기 희생산화막(29) 내에 형성된 개구부 내에 전도막을 매립하여 콘택층(30)을 형성한다. 상기 게이트 전극(23) 및 상기 콘택층(31)의 가장자리가 중첩될 수도 있다.Next, as illustrated in FIG. 2D, the conductive film 30 is deposited on the entire structure, and the entire surface is etched or chemical mechanical polishing is performed to bury the conductive film in the opening formed in the sacrificial oxide film 29. ). Edges of the gate electrode 23 and the contact layer 31 may overlap.

다음으로, 도2e에 도시한 바와 같이 희생산화막(29)을 습식식각하여 제거한 후 식각정지 전도막(29)을 등방성 건식식각으로 제거한다.Next, as shown in FIG. 2E, the sacrificial oxide film 29 is removed by wet etching, and then the etch stop conductive film 29 is removed by isotropic dry etching.

다음으로, 도2f에 도시한 바와 같이 전체 구조 상에 제3 절연막(31)을 증착하여 콘택층(31)이 제3 절연막(31)으로 덮이도록 한다.Next, as shown in FIG. 2F, a third insulating film 31 is deposited on the entire structure so that the contact layer 31 is covered with the third insulating film 31.

전술한 본 발명의 일실시예에서 상기 제1 절연막(24)과 스페이서(25)를 산화막 또는 질화막 중 적어도 어느 하나로 형성할 수 있으며, 상기 제2 절연막(27)과 제3 절연막(29)은 산화막으로 형성할 수 있다. 또한, 상기 식각정지 전도막(28)을 폴리실리콘으로 형성하여 희생산화막의 건식 식각 또는 습식 식각시 높은 식각 선택비를 얻을 수 있고, 식각정지 전도막(28)을 Ti/TiN, WN 등과 같은 장벽금속막으로 형성할 수도 있다. 또한, 상기 콘택층(30)은 폴리실리콘 또는 텅스텐(W)과 같은 물질로 형성된다.In the above-described exemplary embodiment, the first insulating film 24 and the spacer 25 may be formed of at least one of an oxide film and a nitride film, and the second insulating film 27 and the third insulating film 29 may be oxide films. It can be formed as. In addition, the etch stop conductive layer 28 may be formed of polysilicon to obtain a high etching selectivity during dry or wet etching of the sacrificial oxide layer, and the etch stop conductive layer 28 may be formed of a barrier such as Ti / TiN, WN, or the like. It can also be formed from a metal film. In addition, the contact layer 30 is formed of a material such as polysilicon or tungsten (W).

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the spirit of the present invention. It will be evident to those who have knowledge of.

상기와 같이 이루어지는 본 발명은 자기정렬 방식으로 콘택을 형성하고 절연막을 형성하여 콘택층을 매립함으로써 공정 마진을 확보하는 것이 가능하여 비교적 용이하게 고집적 반도체 장치를 제조 할 수 있다.According to the present invention as described above, a process margin can be secured by forming a contact in a self-aligning manner, forming an insulating film, and filling a contact layer, thereby manufacturing a highly integrated semiconductor device relatively easily.

Claims (11)

그 상부 및 측벽이 제1 절연막으로 둘러싸인 게이트 전극을 반도체 기판 상에 형성하고, 상기 반도체 기판 표면으로부터 소정의 깊이를 갖는 소오스 및 드레인 영역을 형성하는 제1 단계;Forming a gate electrode on the semiconductor substrate, the upper and sidewalls of which are surrounded by the first insulating film, and forming source and drain regions having a predetermined depth from the surface of the semiconductor substrate; 상기 제1 단계가 완료된 전체 구조 상에 제2 절연막을 형성하고, 상기 제2 절연막을 선택적으로 식각하여 콘택 영역의 상기 반도체 기판 표면을 노출시키는 제2 단계;Forming a second insulating film on the entire structure in which the first step is completed, and selectively etching the second insulating film to expose a surface of the semiconductor substrate in the contact region; 상기 제2 단계가 완료된 전체 구조 상에 제1 전도막을 형성하는 제3 단계;A third step of forming a first conductive film on the entire structure in which the second step is completed; 상기 제3 단계가 완료된 전체 구조 상에 상기 제1 전도막과 식각 특성이 다른 희생막을 형성하고, 상기 제1 전도막을 식각 정지층으로 이용하여 상기 희생막을 선택적으로 식각해서 상기 콘택 영역의 상기 제1 전도막을 노출시키는 개구부를 형성하는 제4 단계;Forming a sacrificial layer having different etching characteristics from the first conductive layer on the entire structure of which the third step is completed, and selectively etching the sacrificial layer using the first conductive layer as an etch stop layer to form the sacrificial layer in the first region of the contact region. Forming a opening exposing the conductive film; 상기 개구부 내에 제2 전도막을 매립하여 콘택층을 형성하는 제5 단계;A fifth step of forming a contact layer by filling a second conductive film in the opening; 상기 희생막을 제거하여 상기 콘택층으로 덮이지 않은 상기 제1 전도막을 노출시키는 제6 단계;Removing the sacrificial layer to expose the first conductive layer not covered with the contact layer; 상기 제6 단계에 의해 노출된 상기 제1 전도막을 제거하는 제7 단계; 및A seventh step of removing the first conductive film exposed by the sixth step; And 제7 단계가 완료된 전체 구조 상에 제3 절연막을 형성하는 제8 단계Eighth step of forming a third insulating film on the entire structure of the seventh step is completed 를 포함하는 반도체 장치 제조 방법.A semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 게이트 전극 및 상기 콘택층의 가장자리가 중첩되는 것을 특징으로 하는 반도체 장치 제조 방법.And edges of the gate electrode and the contact layer overlap. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제1 단계는,The first step, 반도체 기판 상에 게이트 전극을 형성하기 위한 제3 전도막을 형성하는 단계;Forming a third conductive film for forming a gate electrode on the semiconductor substrate; 상기 제3 전도막 상에 제3 절연막을 형성하는 단계;Forming a third insulating film on the third conductive film; 상기 제3 전도막 및 제3 절연막을 선택적으로 식각하여 게이트 전극 패턴을 형성하는 단계;Selectively etching the third conductive layer and the third insulating layer to form a gate electrode pattern; 상기 반도체 기판 상에 이온 주입을 실시하여 저농도 소오스 및 드레인 영역을 형성하는 단계;Performing ion implantation on the semiconductor substrate to form a low concentration source and drain region; 상기 게이트 전극 측벽에 절연막 스페이서를 형성하는 단계; 및Forming an insulating film spacer on sidewalls of the gate electrode; And 상기 반도체 기판 상에 이온 주입을 실시하여 고농도 소오스 및 드레인 영역을 형성하는 단계로 이루어지는 반도체 장치 제조 방법.And implanting ions on the semiconductor substrate to form a high concentration source and drain region. 제 1 항에 있어서,The method of claim 1, 상기 제1 절연막을 산화막으로 형성하는 반도체 장치 제조 방법.A method of manufacturing a semiconductor device, wherein the first insulating film is formed of an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제1 전도막을 폴리실리콘, Ti, TiN 또는 WN 중 적어도 어느 하나로 형성하는 반도체 장치 제조 방법.A method for manufacturing a semiconductor device, wherein the first conductive film is formed of at least one of polysilicon, Ti, TiN, or WN. 제 5 항에 있어서,The method of claim 5, 상기 희생막을 산화막으로 형성하는 반도체 장치 제조 방법.A method of manufacturing a semiconductor device, wherein the sacrificial film is formed of an oxide film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 전도막을 폴리실리콘 또는 텅스텐으로 형성하는 반도체 장치 제조 방법.A method of manufacturing a semiconductor device, wherein the second conductive film is formed of polysilicon or tungsten. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제2 절연막을 산화막으로 형성하는 반도체 장치 제조 방법.A method of manufacturing a semiconductor device, wherein the second insulating film is formed of an oxide film. 제 2 항에 있어서,The method of claim 2, 상기 제3 절연막을 산화막 또는 질화막 중 적어도 어느 하나로 형성하는 반도체 장치 제조 방법.And forming the third insulating film into at least one of an oxide film and a nitride film. 제 2 항에 있어서,The method of claim 2, 상기 절연막 스페이서를 산화막 또는 질화막 중 적어도 어느 하나로 형성하는 반도체 장치 제조 방법.And forming the insulating film spacer into at least one of an oxide film and a nitride film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제5 단계는,The fifth step, 상기 제4 단계가 완료된 전체 구조 상에 상기 제2 전도막을 증착하는 단계; 및Depositing the second conductive film on the entire structure in which the fourth step is completed; And 상기 제2 전도막을 전면 식각하거나 또는 화학 기계적 연마방법으로 연마하여 상기 희생막 사이에 노출된 영역에 제2 전도막을 매립하여 상기 콘택층을 형성하는 단계로 이루어지는 반도체 장치 제조 방법.And etching the second conductive film by full etching or chemical mechanical polishing to fill the second conductive film in an exposed area between the sacrificial films to form the contact layer.
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