KR100273320B1 - Silicide Formation Method of Semiconductor Device_ - Google Patents
Silicide Formation Method of Semiconductor Device_ Download PDFInfo
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- KR100273320B1 KR100273320B1 KR1019980047517A KR19980047517A KR100273320B1 KR 100273320 B1 KR100273320 B1 KR 100273320B1 KR 1019980047517 A KR1019980047517 A KR 1019980047517A KR 19980047517 A KR19980047517 A KR 19980047517A KR 100273320 B1 KR100273320 B1 KR 100273320B1
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- impurity ions
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 37
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 실리사이드 형성방법에 관한 것으로, 종래에는 트렌치영역 가장자리에 산화막이 손실되어 반도체기판이 노출되고, 그 노출된 영역에 실리사이드층이 형성되어 소자특성이 열화되고, 소스/드레인 영역이 협소해짐에 따라 실리사이드층이 제대로 형성되지 않는 문제점이 있었다. 따라서, 본 발명은 반도체기판상에 순차적으로 웰, 트렌치영역 및 게이트를 형성하는 공정과; 상기 게이트와 트렌치영역을 마스크로 하여 상기 웰 상에 저농도 불순물이온을 주입한 후, 반도체기판의 상부전면에 절연막을 증착하고 저농도 불순물이온이 주입된 영역까지 과도식각하여 상기 게이트에 측벽을 형성하는 공정과; 상기 반도체기판의 상부전면에 폴리실리콘을 증착하고 에치백하여 상기 저농도 불순물이온이 주입된 영역의 양측 가장자리에 폴리실리콘측벽을 형성하는 공정과; 상기 게이트, 트렌치영역 및 측벽을 마스크로 하여 상기 웰 상에 고농도 불순물이온을 주입하여 소스/드레인을 형성하는 공정과; 자기정렬된 실리사이드 공정을 통해 상기 폴리실리콘측벽과 소스/드레인 상에 실리사이드층을 형성하는 공정으로 이루어지는 반도체소자의 실리사이드 형성방법을 통해 트렌치영역 가장자리에 산화막 손실에 따른 반도체기판상에 실리사이드층이 형성되는 것을 차단하여 소자특성의 열화를 방지하고, 고집적소자에서 실리사이드층이 형성될 수 있는 면적을 확보할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a silicide of a semiconductor device. In the related art, an oxide film is lost at an edge of a trench region to expose a semiconductor substrate, and a silicide layer is formed on the exposed region to degrade device characteristics, As narrowed, there was a problem that the silicide layer was not properly formed. Accordingly, the present invention comprises the steps of sequentially forming wells, trench regions and gates on a semiconductor substrate; Implanting low concentration impurity ions into the wells using the gate and trench regions as masks, depositing an insulating film on the upper surface of the semiconductor substrate, and over-etching the region into which the low concentration impurity ions have been implanted to form sidewalls in the gate and; Depositing and etching back polysilicon on the upper surface of the semiconductor substrate to form polysilicon sidewalls at both edges of the region into which the low concentration impurity ions are implanted; Forming a source / drain by implanting high concentration impurity ions into the well using the gate, trench region and sidewalls as a mask; Through the self-aligned silicide process, a silicide layer is formed on the semiconductor substrate due to oxide loss at the edge of the trench region through the silicide formation method of the semiconductor device, which comprises forming a silicide layer on the polysilicon sidewall and the source / drain. To prevent deterioration of device characteristics, and to secure an area in which a silicide layer can be formed in a highly integrated device.
Description
본 발명은 반도체소자의 실리사이드(silicide) 형성방법에 관한 것으로, 특히 트렌치(trench)에 매립되는 산화막의 손실(loss)에 의한 반도체소자의 특성열화를 방지하기에 적당하도록 한 반도체소자의 실리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming silicide of a semiconductor device, and more particularly, to a method of forming a silicide of a semiconductor device suitable for preventing the deterioration of characteristics of the semiconductor device due to the loss of an oxide film embedded in a trench. It is about.
종래 반도체소자의 실리사이드 형성방법을 도1a 내지 도1c의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A silicide formation method of a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1C.
먼저, 도1a에 도시한 바와같이 웰(2)이 형성된 반도체기판(1) 상에 소자들의 전기적 절연을 위한 트렌치영역(3)을 형성한 후, 그 트렌치영역(3)과 소정거리 이격되는 반도체기판(1)의 상부에 게이트(4)를 형성한다. 이때, 게이트(4)는 트렌치영역(3)이 형성된 반도체기판(1)의 상부전면에 산화막, 폴리실리콘, 금속층 및 절연막을 증착하고 패터닝하여 적층구조로 형성한다.First, as shown in FIG. 1A, a trench region 3 for electrical insulation of elements is formed on a semiconductor substrate 1 on which a well 2 is formed, and then a semiconductor spaced apart from the trench region 3 by a predetermined distance. The gate 4 is formed on the substrate 1. In this case, the gate 4 is formed in a stacked structure by depositing and patterning an oxide film, a polysilicon, a metal layer, and an insulating film on the upper surface of the semiconductor substrate 1 on which the trench region 3 is formed.
그리고, 도1b에 도시한 바와같이 상기 게이트(4)와 트렌치영역(3)의 이격영역 상에 저농도 불순물이온을 주입하여 저농도 소스/드레인 영역(5)을 형성한 후, 반도체기판(1)의 상부전면에 화학기상증착법을 통해 절연막을 증착하고, 에치백(etch-back)하여 상기 게이트(4)의 측면에 측벽(6)을 형성한다. 이때, 측벽(6) 하부에 형성된 저농도 소스/드레인 영역(5)은 반도체소자가 고집적화되어 채널길이가 짧아짐에 따라 발생되는 문제점을 완충하기 위한 엘디디(lightly doped drain : LDD)영역이다.As shown in FIG. 1B, a low concentration source / drain region 5 is formed by implanting low concentration impurity ions into a space between the gate 4 and the trench region 3 to form a low concentration source / drain region 5. An insulating film is deposited on the upper surface by chemical vapor deposition and etched back to form sidewalls 6 on the side of the gate 4. In this case, the low concentration source / drain region 5 formed under the sidewall 6 is an LDD region for buffering problems caused by the high integration of semiconductor devices and shortening of channel lengths.
그리고, 도1c에 도시한 바와같이 상기 게이트(4)의 측벽(6)과 트렌치영역(3)의 이격영역 상에 고농도 불순물이온을 주입하여 고농도 소스/드레인 영역(7)을 형성한 후, 그 소스/드레인 영역(7) 상에 실리사이드층(8)을 형성한다. 이때, 실리사이드층(8)은 반도체기판(1)의 상부전면에 금속층을 증착한 후, 열처리하게 되면 실리콘이 금속과 반응하여 형성되고, 트렌치영역(3), 게이트(4) 상부 및 측벽(6)에서는 금속과의 반응이 일어나지 않으므로 금속층으로 잔류하게 되며, 이와같이 잔류하는 금속층을 제거하면 소스/드레인 영역(7) 상에만 형성된다.As shown in FIG. 1C, a high concentration source / drain region 7 is formed by implanting high concentration impurity ions on the sidewall 6 of the gate 4 and the separation region of the trench region 3. The silicide layer 8 is formed on the source / drain region 7. In this case, the silicide layer 8 is formed by depositing a metal layer on the upper surface of the semiconductor substrate 1 and then heat-treating the silicon to react with the metal, and form the trench region 3, the upper portion of the gate 4, and the sidewalls 6. In (), the reaction with the metal does not occur, so it remains as a metal layer. If the remaining metal layer is removed, it is formed only on the source / drain region 7.
상기한 바와같은 실리사이드층(8)의 형성을 자기정렬된 실리사이드(self-aligned silicide : SALICIDE)공정이라 하며, 이 실리사이드층(8)은 소스/드레인 영역(7)의 저항값을 낮추는데 기여한다.The formation of the silicide layer 8 as described above is called a self-aligned silicide (SALICIDE) process, and this silicide layer 8 contributes to lowering the resistance value of the source / drain region 7.
그러나, 상기한 바와같은 종래 반도체소자의 실리사이드 형성방법은 게이트, 측벽등의 형성시에 과도식각이나 HF 전세등으로 인해 트렌치영역 가장자리에 산화막의 손실(loss)이 생기게 되고, 이에 따라 반도체기판이 노출된 영역까지 실리사이드층이 형성되어 접합누설(junction leakage) 및 절연(isolation) 특성이 열화되는 문제점과; 반도체소자가 고집적화되어 소스/드레인 영역이 협소해짐에 따라 실리사이드층이 제대로 형성되지 않는 문제점이 있었다.However, in the method of forming a silicide of a conventional semiconductor device as described above, an oxide film is lost at the edge of the trench region due to excessive etching or HF charting during the formation of gates, sidewalls, and the like, thereby exposing the semiconductor substrate. A silicide layer is formed up to a defined region, whereby junction leakage and isolation characteristics deteriorate; As the semiconductor device is highly integrated and the source / drain regions are narrowed, there is a problem that the silicide layer is not properly formed.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 트렌치영역 가장자리의 산화막 손실을 방지함과 아울러 실리사이드층이 형성될 수 있는 면적을 확보할 수 있는 반도체소자의 실리사이드 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of preventing oxide loss at the edge of the trench region and securing an area in which a silicide layer can be formed. It is to provide a silicide forming method.
도1은 종래 반도체소자의 실리사이드 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a method of forming a silicide of a conventional semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:웰11: semiconductor substrate 12: well
13:트렌치영역 14:게이트13: trench region 14: gate
15:저농도 소스/드레인 영역 16:측벽15: Low concentration source / drain area 16: Side wall
17:폴리실리콘측벽 18:소스/드레인 영역17: polysilicon sidewall 18: source / drain area
19:실리사이드층19: silicide layer
상기한 바와같은 본 발명의 목적을 달성하기 위한 실리사이드 형성방법의 바람직한 일 실시예는 반도체기판상에 순차적으로 웰, 트렌치영역 및 게이트를 형성하는 공정과; 상기 게이트와 트렌치영역을 마스크로 하여 상기 웰 상에 저농도 불순물이온을 주입한 후, 반도체기판의 상부전면에 절연막을 증착하고 저농도 불순물이온이 주입된 영역까지 과도식각(over-etch)하여 상기 게이트에 측벽을 형성하는 공정과; 상기 반도체기판의 상부전면에 폴리실리콘을 증착하고 에치백하여 상기 저농도 불순물이온이 주입된 영역의 양측 가장자리에 폴리실리콘측벽을 형성하는 공정과; 상기 게이트, 트렌치영역 및 측벽을 마스크로 하여 상기 웰 상에 고농도 불순물이온을 주입하여 소스/드레인을 형성하는 공정과; 자기정렬된 실리사이드 공정을 통해 상기 폴리실리콘측벽과 소스/드레인 상에 실리사이드층을 형성하는 공정을 구비하여 이루어짐을 특징으로 한다.One preferred embodiment of the silicide forming method for achieving the object of the present invention as described above comprises the steps of sequentially forming wells, trench regions and gates on a semiconductor substrate; After implanting low concentration impurity ions into the well using the gate and trench regions as masks, an insulating film is deposited on the upper surface of the semiconductor substrate and over-etched to a region where low concentration impurity ions are implanted into the gate. Forming sidewalls; Depositing and etching back polysilicon on the upper surface of the semiconductor substrate to form polysilicon sidewalls at both edges of the region into which the low concentration impurity ions are implanted; Forming a source / drain by implanting high concentration impurity ions into the well using the gate, trench region and sidewalls as a mask; And forming a silicide layer on the polysilicon sidewall and the source / drain through a self-aligned silicide process.
상기한 바와같은 본 발명에 의한 실리사이드 형성방법의 바람직한 일 실시예를 도2a 내지 도2e를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the silicide formation method according to the present invention as described above will be described in detail with reference to FIGS. 2A to 2E.
먼저, 도2a에 도시한 바와같이 웰(12)이 형성된 반도체기판(11) 상에 소자들의 전기적 절연을 위한 트렌치영역(13)을 형성한 후, 그 트렌치영역(13)과 소정거리 이격되는 반도체기판(11)의 상부에 게이트(14)를 형성한다. 이때, 게이트(14)는 트렌치영역(13)이 형성된 반도체기판(11)의 상부전면에 산화막, 폴리실리콘, 금속층 및 절연막을 증착하고 패터닝하여 적층구조로 형성한다.First, as shown in FIG. 2A, a trench region 13 is formed on the semiconductor substrate 11 on which the well 12 is formed, and the semiconductor region is spaced apart from the trench region 13 by a predetermined distance. The gate 14 is formed on the substrate 11. In this case, the gate 14 is formed in a stacked structure by depositing and patterning an oxide film, a polysilicon, a metal layer, and an insulating film on the upper surface of the semiconductor substrate 11 on which the trench region 13 is formed.
그리고, 도2b에 도시한 바와같이 상기 게이트(14)와 트렌치영역(13)의 이격영역 상에 저농도 불순물이온을 주입하여 저농도 소스/드레인 영역(15)을 형성한 후, 반도체기판(11)의 상부전면에 화학기상증착법을 통해 절연막을 증착하고 상기 저농도 소스/드레인 영역(15)까지 과도식각하여 상기 게이트(14)의 측면에 측벽(16)을 형성한다. 이때, 절연막은 저농도 불순물이온이 주입된 깊이에 따라 과도식각량이 결정되며, 최소 100Å이상 수행한다.As shown in FIG. 2B, a low concentration source / drain region 15 is formed by implanting low concentration impurity ions into a space between the gate 14 and the trench region 13 to form a low concentration source / drain region 15. An insulating film is deposited on the upper surface by chemical vapor deposition and overetched to the low concentration source / drain region 15 to form sidewalls 16 on the side of the gate 14. At this time, the insulating film is determined according to the depth implanted with a low concentration of impurity ions, the over-etching amount is performed at least 100Å.
그리고, 도2c에 도시한 바와같이 상기 반도체기판(11)의 상부전면에 폴리실리콘을 증착하고 에치백하여 상기 저농도 소스/드레인 영역(15)의 양측 가장자리에 폴리실리콘측벽(17)을 형성한다. 이때, 폴리실리콘은 도핑되지 않은 폴리실리콘을 100Å 이상의 두께로 형성한다.As shown in FIG. 2C, polysilicon is deposited on the upper surface of the semiconductor substrate 11 and etched back to form polysilicon sidewalls 17 at both edges of the low concentration source / drain region 15. As shown in FIG. At this time, the polysilicon forms the undoped polysilicon to a thickness of 100 kPa or more.
그리고, 도2d에 도시한 바와같이 상기 게이트(14)의 측벽(16)과 트렌치영역(13)의 이격영역 상에 고농도 불순물이온을 주입하여 고농도 소스/드레인 영역(18)을 형성한다.As shown in FIG. 2D, a high concentration of impurity ions are implanted on the sidewalls 16 of the gate 14 and the separation region of the trench region 13 to form a high concentration source / drain region 18.
그리고, 도2e에 도시한 바와같이 자기정렬된 실리사이드 공정을 통해 상기 폴리실리콘측벽(17)과 소스/드레인 영역(18) 상에 실리사이드층(19)을 형성한다. 이때, 실리사이드층(19)은 반도체기판(11)의 상부전면에 금속층을 증착한 후, 열처리하게 되면 실리콘이 금속과 반응하여 형성되고, 트렌치영역(13), 게이트(14) 상부 및 측벽(16)에서는 금속과의 반응이 일어나지 않으므로 금속층으로 잔류하게 되며, 이와같이 잔류하는 금속층을 제거하면 폴리실리콘측벽(17)과 소스/드레인 영역(18)의 상부에만 형성된다.As shown in FIG. 2E, a silicide layer 19 is formed on the polysilicon sidewall 17 and the source / drain region 18 through a self-aligned silicide process. In this case, the silicide layer 19 is formed by depositing a metal layer on the upper surface of the semiconductor substrate 11 and then heat-treating the silicon to react with the metal, and form the trench region 13, the gate 14, and the sidewall 16. In this case, the reaction with the metal does not occur and thus remains as a metal layer. When the remaining metal layer is removed, the metal layer is formed only on the polysilicon sidewall 17 and the source / drain region 18.
상기한 바와같은 본 발명에 의한 반도체소자의 실리사이드 형성방법은 폴리실리콘측벽을 형성하고, 그 폴리실리콘측벽 상에 실리사이드층을 형성함으로써, 트렌치영역 가장자리에 산화막의 손실에 따라 반도체기판의 노출된 영역까지 실리사이드층이 형성되는 것을 차단하여 접합누설 및 절연 특성의 열화를 방지함과 아울러 고집적소자에서 실리사이드층이 형성될 수 있는 면적을 확보할 수 있는 효과가 있다.The silicide formation method of the semiconductor device according to the present invention as described above forms a polysilicon sidewall and a silicide layer on the polysilicon sidewall, to the exposed region of the semiconductor substrate according to the loss of the oxide film at the edge of the trench region. By preventing the silicide layer from being formed, it is possible to prevent junction leakage and deterioration of insulation characteristics, and to secure an area in which the silicide layer can be formed in the highly integrated device.
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