KR101133523B1 - Method of manufacturing a transistor in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, wherein openings (or trenches) are formed in the insulating film with a minimum width that can be defined by exposure equipment, and insulating film spacers are formed on the sidewalls of the openings. The gate is formed by filling the opening with a conductive material, and the transistor is provided by a structure of a Schottky Barrier Metal Oxide Silicon Field Effect Transistor (SBMOSFET), which does not require a high temperature thermal process and an ion implantation process to form a source / drain. In addition, it is possible to stably form a pattern having a width narrower than the minimum width that can be defined by the exposure equipment, and to omit a thermal process or an ion implantation process for forming a source / drain, thereby increasing the integration of the device while ensuring the reproducibility of the process. .

SBMOSFETs, gates, damascene structures, pattern widths, exposure limits

Description

Method of manufacturing a transistor in a semiconductor device             

1A to 1L are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 device isolation film

103: first ion implantation mask 104: first insulating film

105: second insulating film 105a: opening part

106: sacrificial insulating film spacer 107: gate insulating film

108: gate 109: oxide film

110 insulating film spacer 111 silicide layer

112: interlayer insulating film 112a: contact hole

113: contact plug

The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly to a method for manufacturing a transistor of a semiconductor device capable of increasing the degree of integration.

Generally, after performing an ion implantation process to form the source / drain of a transistor, a thermal process is performed at high temperature (for example, about 1000 degreeC). As a result, the implanted impurities are activated. At this time, the impurities are diffused, which makes it difficult to diffuse the impurities at a shallow depth.

In addition, the degree of integration of the device is almost absolutely dependent on the performance of the exposure equipment. Expensive exposure equipment is needed to increase the integration of the device, and when a finer pattern is formed than the exposure device can define the pattern, it is difficult to secure the reproducibility of the process and the yield is lowered, thereby increasing the integration of the device. .

In contrast, in the method of manufacturing a transistor of a semiconductor device according to the present invention, an opening (or trench) is formed in an insulating film with a minimum width that can be defined by exposure equipment, and an insulating film spacer is formed on the sidewall of the opening. The gate is formed by filling the narrow opening with a conductive material, and the transistor is formed by a structure of a Schottky Barrier Metal Oxide Silicon Field Effect Transistor (SBMOSFET) that does not require a high-temperature thermal process and an ion implantation process to form a source / drain. By increasing the density, the thermal pattern or ion implantation process for stably forming a pattern narrower than the minimum width that can be defined by the exposure equipment and the source / drain can be omitted, thereby increasing the integration of the device while ensuring the reproducibility of the process. Can be.

In the method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention, the steps of sequentially forming an insulating film on a semiconductor substrate on which the device isolation film is formed, forming an opening in the insulating film to a minimum width, and a sacrificial insulating film spacer on the sidewall of the opening Forming a gate insulating film on the semiconductor substrate exposed through the opening; forming a gate in the opening; and sequentially removing the insulating film and the sacrificial insulating film spacer; Forming an insulating film spacer on the sidewall of the gate by oxidizing the surface, and forming a silicide layer on the upper surface of the gate and on the semiconductor substrate at the gate edge.

In the above, an etch stop insulating layer may be further formed between the semiconductor substrate and the insulating layer in order to prevent the etching damage from occurring in the process of forming the opening. In this case, the etch stop insulating film may be formed of a SiON film.

The width of the opening is controlled by the sacrificial insulating spacer.

The surface of the gate may be oxidized by about 100 kV to about 300 kV by the oxidation process, and after forming the insulating film spacer, the surface of the semiconductor substrate may be etched to relatively increase the height of the semiconductor substrate under the gate.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

1A to 1L are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, an isolation layer 102 is formed in an isolation region of the semiconductor substrate 101. In this case, the device isolation layer 102 may be formed in a trench structure by applying a shallow trench isolation (STI) method. Subsequently, after forming the first ion implantation mask 103, a well (not shown) is formed in the active region by an ion implantation process. Here, the first ion implantation mask 103 may prevent pentavalent ions into the p-well region when the n-well is formed or trivalent ions into the n-well region when the p-well is formed. Is formed.

Referring to FIG. 1B, after removing the first ion implantation mask 103 (FIG. 1A), the first insulating layer 104 is formed on the entire structure of the semiconductor substrate 101 on which the device isolation layer 102 and the wells (not shown) are formed. ) And the second insulating film 105 are sequentially formed. Here, the first insulating film 104 is preferably formed of a SiON film. This is to protect the semiconductor substrate 101 from the etching process during the etching process for defining the region where the gate is to be formed in a subsequent process. The second insulating layer 105 may serve as a sacrificial insulating layer for defining a gate or a region in which a predetermined pattern is to be formed, and may be formed of a silicon oxide layer. In addition, the thickness of the second insulating layer 105 is preferably determined in consideration of the height of the pattern to be formed in a subsequent step, and may be formed to a thickness of 1800 kPa to 2500 kPa.

Referring to FIG. 1C, a portion of the second insulating layer 105 is removed by an etching process to define a region in which a gate or a predetermined pattern is to be formed in the form of an opening 105a. As a result, the opening 105a is formed in the region where the gate is to be formed, and the first insulating film 104 is exposed through the opening 105a. At this time, the opening 105a is formed in the minimum width that the exposure equipment can stably define.

Referring to FIG. 1D, the sacrificial insulating layer spacer 106 is formed on the sidewall of the opening 105a. In this case, the sacrificial insulating film spacer 106 may be formed of a silicon nitride film, and after the insulating film is formed on the entire structure including the opening 105a, the insulating film is left only on the sidewall of the opening 105a by a front etching process. Can be formed.

Here, the sacrificial insulating layer spacer 106 is formed to narrow the width of the opening 105a in which the gate or the predetermined film is to be formed, thereby narrowing the gate or the predetermined film to a width smaller than the minimum width that the exposure equipment can stably define. Can be formed. Specifically, for example, when the minimum width of the pattern that the exposure equipment can define is 20 μm and the target width of the gate is set to 0.14 μm, the amount of the opening 105a is 0.3 μm in the thickness. When formed on the sidewalls, the width may be reduced by 0.6 μm to form a gate having a width of 0.14 μm in the opening 105 a.

Therefore, when the insulating film is formed over the entire structure to form the sacrificial insulating film spacer 106, it is preferable to set the thickness of the insulating film in consideration of how much the width of the opening 104a is to be reduced.

Referring to FIG. 1E, the first insulating layer 104 exposed through the opening 105a is removed. As a result, the surface of the semiconductor substrate 101 is exposed through the opening. Next, a gate insulating film 107 is formed on the surface of the semiconductor substrate 101.

Referring to FIG. 1F, a gate 108 is formed in the opening 105a. The gate 108 forms a conductive material layer on the entire structure such that the opening 105a is completely filled, and then selectively removes only the conductive material layer on the second insulating layer 105 and removes the conductive material layer only in the opening 105a. It can form by the method of making it remain. In this case, the conductive material layer may be formed of polysilicon, and the conductive material layer on the second insulating layer 105 may be removed by a chemical mechanical polishing process. On the other hand, the chemical mechanical polishing process proceeds in such a way that the polishing is stopped when the component of the second insulating film 105 is detected, through which the height of the gate 108 can be accurately controlled.

Referring to FIG. 1G, the second insulating film 105 (FIG. 1F) and the first insulating film (104 of FIG. 1F) are sequentially removed. In this case, the insulating layers may be removed with diluted hydrofluoric acid (HF) solution or BOE solution. Meanwhile, the first insulating film may be completely removed, and the first insulating film 104 may be left only under the sacrificial insulating film spacer 106. If there is no low energy ion implantation device, it is preferable to leave the first insulating film 104 under the sacrificial insulating film spacer 106.

Referring to FIG. 1H, the sacrificial insulation spacer (106 of FIG. 1G) remaining on the sidewall of the gate 108 and the first insulating layer 104 (FIG. 1G) below it are removed. As a result, the surface of the gate 108 is completely exposed.

Referring to FIG. 1I, the entire surface of the gate 108 is oxidized in an oxidation process. At this time, the surface of the semiconductor substrate 101 is also oxidized, and an oxide film 109 is formed on the surface of the gate 108 and the surface of the semiconductor substrate 101. The oxidation process is performed such that the oxide film 109 is formed on the surface of the gate 108 to a thickness of 100 kPa to 300 kPa.

On the other hand, the oxide film 109 formed on the surface of the semiconductor substrate 101 is formed while penetrating to a predetermined depth of the semiconductor substrate 101.

Referring to FIG. 1J, the entire surface etching process may be performed by a dry etching method to remove the oxide layer 109 of FIG. 1I and the oxide layer 109 of FIG. 1I on the semiconductor substrate 101, and to remove the gate 108. The oxide film (109 in Fig. 1I) is left only on the sidewall of the &quot; Since the oxide film 109 of FIG. 1I is formed while the sidewall of the gate 108 is recessed, the oxide film 109 of FIG. 1I that remains on the sidewall of the gate 108 is left without etching during the entire surface etching process. As a result, an insulating film spacer 110 made of the remaining oxide film (109 in FIG. 1I) is formed on the sidewall of the gate 108.

On the other hand, while the oxide film (109 in FIG. 1I) formed on the surface of the semiconductor substrate 101 is removed, the surface height of the semiconductor substrate 101 is lowered. Accordingly, the height of the semiconductor substrate 101 under the gate 108 corresponding to the channel region is increased.

In addition, the height of the semiconductor substrate 101 under the gate 108 may be relatively higher by etching the semiconductor substrate 101. At this time, the surface of the semiconductor substrate 101 may be etched 50 ~ 200 ~. This is to allow the silicide layer to grow laterally under the gate oxide layer during the silicide layer forming process in a subsequent process. In this case, the distance between the source and the drain may be reduced to further improve the operation characteristics of the SBMOSFET.

After the surface of the semiconductor substrate 101 is etched, a curing and cleaning process is performed. The ATC treatment may be performed instead of the cleaning process.

Referring to FIG. 1K, conventionally, ion implantation was performed to form a source / drain. However, in the present invention, a self-aligned silicide process is immediately performed without performing an ion implantation process, and thus the upper portion of the gate 108 is formed. And a silicide layer 111 is formed on the active region of the semiconductor substrate 101.

In this case, Ir, Pt2, Er, or the like may be used as the metal material for forming the silicide layer 111, and is determined according to the type of SBMOSFET. In other words, since the work function of each silicide becomes a characteristic of the N / P type silicon, it is possible to form a desired type of device.

In this way, an SBMOSFET is manufactured.

Referring to FIG. 1L, an interlayer insulating layer 112 is formed on an entire structure, a contact hole 112a is formed, and a contact plug 113 is formed inside the contact hole 112a.

As described above, the present invention forms the openings (or trenches) in the insulating film to the minimum width that can be defined by the exposure equipment, and the insulating film spacers are formed on the sidewalls of the openings. It is defined as an exposure equipment by forming a gate in a buried manner and enhancing the transistor with a structure of a Schottky Barrier Metal Oxide Silicon Field Effect Transistor (SBMOSFET) that does not require a high temperature thermal process and an ion implantation process to form a source / drain. It is possible to stably form a pattern narrower than the minimum width possible and to omit a thermal process or an ion implantation process for forming a source / drain, thereby increasing the integration of the device while ensuring the reproducibility of the process.

Claims (7)

Sequentially forming an insulating film on the semiconductor substrate on which the device isolation film is formed; Forming openings in the insulating film; Forming a sacrificial insulation spacer on sidewalls of the opening; Forming a gate insulating film on the semiconductor substrate exposed through the opening; Forming a gate in the opening; Sequentially removing the insulating film and the sacrificial insulating film spacer; Oxidizing the surface of the gate by an oxidation process and then performing an entire surface etching process to form an insulating film spacer on the sidewall of the gate; After forming the insulating film spacer on the gate sidewall, etching a surface of the semiconductor substrate on which the silicide layer is to be formed to relatively increase the height of the semiconductor substrate under the gate; And Forming a silicide layer on the gate and on the semiconductor substrate at the gate edge; Transistor manufacturing method of a semiconductor device comprising a. The method of claim 1, And an etch stop insulating film is further formed between the semiconductor substrate and the insulating film to prevent etch damage from occurring in the semiconductor substrate during the opening. The method of claim 2, The method of manufacturing a transistor of a semiconductor device, wherein the etch stop insulating film is a SiON film. The method of claim 1, And a width of the opening portion is controlled by the sacrificial insulating layer spacer. The method of claim 1, And a surface of the gate is oxidized about 100 kV to about 300 kV by the oxidation process. delete The method of claim 1, The etching of the surface of the semiconductor substrate, the semiconductor substrate transistor manufacturing method, characterized in that for etching the surface of the semiconductor substrate 50 ~ 200Å.

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