JP2010067683A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inhibit the generation of dislocation to a semiconductor substrate when forming a source/drain region when the element separation of an STI structure is performed. <P>SOLUTION: A semiconductor device is formed so that, in a contact region between an active region 2 and an element isolation insulating film 3, the element isolation insulating film is located in a height which is deeper than that of a surface of a silicon substrate 1 and shallower than a formation depth d4 (or a PN junction part) of a high concentration impurity diffusion region 1b whose concentration is the peak concentration of a source/drain region 1b. The element isolation insulating film is located in the depth d2 which is deeper than the depth d4 as the element isolation insulating film moves away from this region to an outward region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a structure in which an element isolation region is provided around an active region and a method for manufacturing the same.

  In a typical flash memory as a semiconductor device, element isolation having an STI (Shallow Trench Isolation) structure is employed in order to form a fine element isolation structure. The STI structure is configured by forming an element isolation groove along a predetermined direction on the surface of a semiconductor substrate, and embedding an element isolation insulating film in the element isolation groove, thereby isolating the active region. (For example, refer to Patent Document 1). According to the technical idea described in Patent Document 1, a polysilazane film is embedded as a coating type insulating film in an element isolation trench, and silicon is formed on the polysilazane film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method. An oxide film is formed, thereby constituting an element isolation insulating film.

  The polysilazane film described above is converted into an oxide film by applying a heat treatment after applying a polysilazane coating solution. However, since the polysilazane itself contracts during this heat treatment, the stress acts on the semiconductor substrate side. . In particular, since the stress generated in the portion where the coating amount is large also increases, the strain stress applied to the semiconductor substrate in the portion in contact with the polysilazane also increases.

  For example, since the STI is formed so as to surround the active region of the semiconductor substrate in the region where the transistor of the peripheral circuit portion is formed, the active region is likely to cause crystal defects and dislocations due to a large stress at the portion where the active region is in contact with the polysilazane film. . In particular, when an LDD (lightly doped drain) structure is adopted as the impurity diffusion region of the transistor, there is a problem that dislocation is likely to occur when the high concentration impurity region is formed.

  That is, when forming a high-concentration impurity region of an LDD structure, a crystal formed by ion implantation at a depth at which a pn junction is formed inside the semiconductor substrate, that is, at a depth where the impurity concentration is at a peak level during ion implantation. Many defects have occurred. Heat treatment is performed in order to reduce the crystal defects and activate the impurities. At this time, since the semiconductor substrate receives stress from polysilazane at the STI portion in contact with the active region, dislocations that are linear defects are likely to occur inside the semiconductor substrate with the crystal defects as nuclei. Since such dislocations cause an increase in the leakage current of the pn junction, it is desirable to suppress them. Therefore, it is preferable to drop the oxide film by wet etching such as hydrofluoric acid. Then, the oxide film at the corner of the semiconductor substrate under the gate electrode can also be etched.

In order to protect the side wall of the gate electrode, it is preferable to form an insulating film on the side wall of the gate electrode in advance. However, the side wall insulating film is thinned because the side wall insulating film is also exposed to the process by the wet etching process of the element isolation insulating film. For example, if all the processing is performed, the exposed gate insulating film may be exposed to processing, which may adversely affect transistor characteristics and reliability. Therefore, the wet etching processing amount is limited by the thickness of the insulating film on the side wall, and the element isolation insulating film cannot be dropped sufficiently as a countermeasure against crystal defects.
JP 2006-156471 A JP 2004-228557 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of dislocation with respect to a semiconductor substrate at the time of forming a source / drain region when element isolation of an STI structure is performed.

  According to one embodiment of the present invention, a semiconductor substrate having an active region partitioned by forming a trench having a first depth from the substrate surface around the gate, and gate insulation over a part of the active region A gate electrode formed through a film and in the active region on both sides of the gate electrode, a depth from the surface of the semiconductor substrate is formed at a second depth shallower than a first depth; A source / drain region having an exposed surface exposed on a sidewall of the trench; and an element isolation insulating film embedded in the trench including a coating type insulating film, wherein the gate electrode is separated from the active region by the element isolation. The element isolation insulating film extending in the insulating film in a region where the gate electrode is not located above is deeper than the height of the surface of the semiconductor substrate in the vicinity of the contact region with the active region. Located at a height shallower than the depth It is characterized in that it is located deep than the second depth in the outer region than near the contact area.

  In one embodiment of the present invention, a groove is formed around the active region of the first conductivity type semiconductor substrate, and an element isolation insulating film including a coating type insulating film is embedded in the groove to form an element isolation region. A step of forming a gate electrode on the active region through a gate insulating film, and introducing an impurity into the active region using the gate electrode as a mask to have a conductivity type opposite to the first conductivity type. A step of forming a second conductivity type low-concentration impurity introduction region, a step of forming a spacer film for forming an LDD (Lightly Doped Drain) structure along the sidewall of the gate electrode, and the gate electrode and the spacer film. Forming a second conductivity type high-concentration impurity introduction region in the active region as a mask, and forming a mask pattern so as to cover the contact end portion of the element isolation insulating film between the active region and the element isolation region; A step of removing a predetermined thickness of the upper portion of the element isolation insulating film in the groove in a region excluding the contact end of the element isolation insulating film using the mask pattern as a mask, and a step of peeling the mask pattern; A step of wet-etching the upper portion of the element isolation insulating film in the groove including the contact end portion of the element isolation insulating film and the spacer film, a step of performing a heat treatment to activate the impurities, and the element isolation insulating film And a step of forming a non-coating insulating film thereon.

  According to the present invention, it is possible to suppress the occurrence of dislocation with respect to the semiconductor substrate at the time of forming the source / drain regions.

  Hereinafter, an embodiment in which the present invention is applied to a transistor having an LDD structure formed in a peripheral circuit portion of a NAND flash memory device and the peripheral structure thereof will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  First, the configuration of the low voltage transistor of this embodiment will be described with reference to FIGS. 1 and 2. 1A is a longitudinal sectional view of a low voltage transistor in a peripheral circuit of the NAND flash memory device, and FIG. 1B is a longitudinal sectional view of a memory cell transistor configured in a memory cell region. 2 (a) is a plan view of the low-voltage transistor and its periphery, FIG. 2 (b) schematically shows a plan view of the memory cell transistor and its periphery, and FIG. 1 (a) is shown in FIG. 2 (a). The middle 1A-1A line and FIG. 1B schematically show the cross section of the portion indicated by the 1B-1B line in FIG. 2B.

  As shown in FIGS. 1A and 1B, a P-type silicon substrate 1 as a semiconductor substrate has an N well in the surface layer of the low voltage transistor formation region R in the memory cell region M and the peripheral circuit region. (Not shown) is formed, and a P well 1a is formed on the surface layer thereof, and an active region 2 is formed in the P well 1a. An element isolation region having an STI (Shallow Trench Isolation) structure is formed so as to surround the active region 2. An element isolation insulating film 3 is formed in the element isolation region.

  The element isolation insulating film 3 includes an HTO (High Temperature Oxide) film 5 formed along the inner surface of a trench (corresponding to a groove) 4 formed in the silicon substrate 1 and a coating type formed inside the HTO film 5. The insulating film is composed of an SOG (Spin On Glass) film 6 which is a coating type oxide film.

  The trench 4 is formed such that its bottom surface is located at a depth d1 from the surface of the silicon substrate 1. The SOG film 6 is buried in the trench 4 such that the upper surface is located at a predetermined height from the bottom surface of the trench 4 and the depth from the surface of the silicon substrate 1 is located at a depth d2 that is shallower than the depth d1. It is included.

  The SOG film 6 is a silicon oxide film that has been converted into an oxide film by, for example, applying a chemical solution of polysilazane (PSZ) and heat-treating it. Further, a TEOS (Tetra Ethyl Ortho Silicate) oxide film 7 and a silicon nitride film 8 having a predetermined film thickness are laminated on the upper surface of the SOG film 6, and a BPSG film 9 is embedded so as to fill the trench 4 and its upper part. Is formed.

A gate electrode PG is formed on the active region 2 so as to cross a predetermined direction in the surface of the silicon substrate 1 via a gate insulating film 10, and source / drain regions 1 d are formed on both sides of the gate electrode PG. Thus, a low voltage transistor Trp is configured. The gate electrode PG is configured by laminating a polycrystalline silicon layer 11, an inter-gate insulating film 12, a polycrystalline silicon layer 13, and cobalt silicide (CoSi ₂ ) 14 from the lower layer.

  The gate electrode PG is formed in the same process as the process for forming the gate electrode MG of the memory cell transistor Trm. Note that there is an opening in the inter-gate insulating film 12 between the polycrystalline silicon layer 11 corresponding to the floating gate electrode FG of the gate electrode MG and the polycrystalline silicon layer 13 constituting the control gate electrode CG of the memory cell transistor Trm. 12a is formed, and the polycrystalline silicon layers 11 and 13 are structurally contacted and electrically short-circuited.

  As shown in FIG. 1A and FIG. 2A, on the surface layer of the active region 2, the source / drain regions 1 d of the LDD structure on both sides of the gate electrode PG are active except for the lower central region of the gate electrode PG. It is formed over the entire region 2. The source / drain region 1d of this LDD structure is an N-type impurity diffusion region having a conductivity type opposite to the conductivity type of the P well 1a. The first-concentration low-concentration impurity diffusion region 1c and the first concentration Also, the high-concentration impurity diffusion region 1b having a high second concentration is formed.

  The low-concentration impurity diffusion region 1c has one end extending below the gate electrode PG so as to overlap the side portion of the gate electrode PG by a predetermined length. One end of the high concentration impurity diffusion region 1b is separated from the side wall of the gate electrode PG by a predetermined distance. Further, the formation depth of the high concentration impurity diffusion region 1b from the surface of the silicon substrate 1 (the depth at which the impurity distribution is at the peak level or the depth of the PN junction) d4 is the formation depth of the low concentration impurity diffusion region 1c. (The depth at which the low-concentration impurity distribution is at the peak level or the depth of the PN junction) is formed deeper than d3.

  The high concentration impurity region 1b is formed from the side of the gate electrode PG to the end of the active region 2 while maintaining the depth d4. Similarly, the low-concentration impurity region 1c is also formed from the side of the gate electrode PG to the end of the active region 2 while maintaining the depth d3.

  Therefore, the PN junction of the source / drain region 1d is exposed on the side wall of the active region 2 which is the boundary surface between the active region 2 and the element isolation insulating film 3. The formation depth d4 of the high concentration impurity region 1b is formed to be shallower than the depth d2 of the upper surface of the SOG film 6 at a predetermined position spaced outward from the active region 2.

  A TEOS oxide film 7 is formed on the side wall surface of the gate electrode PG and the upper surface of the active region 2, and a silicon nitride film 8 is formed along the outer surface of the TEOS oxide film 7. On the silicon nitride film 8, a BPSG film 9 is buried and formed as an uncoated insulating film up to the height of the upper surface of the gate electrode PG.

  On the upper surface of the gate electrode PG and the upper surface of the BPSG film 9, a silicon nitride film 15 as an etching stopper and a barrier film is formed. An interlayer insulating film 16 is formed on the upper surface of the silicon nitride film 15. The interlayer insulating film 16 is composed of a TEOS oxide film. A contact hole 17a is formed so as to penetrate the interlayer insulating film 16, the silicon nitride film 15, the BPSG film 9, the silicon nitride film 8 and the TEOS oxide film 7, and a contact plug 17 is formed in the contact hole 17a. Yes. A wiring layer 18 is formed on the contact plug 17. The lower end of the contact plug 17 is in contact with the high concentration impurity region 1b constituting the source / drain region 1d.

  In the memory cell region M, as shown in FIG. 2B, the active region 2 is formed along the X direction, and the active region 2 has a predetermined interval in the Y direction orthogonal to the X direction. Therefore, it is installed side by side. Further, word lines WL are formed along the Y direction, and are arranged in parallel in the X direction with a predetermined interval. A gate electrode MG of the memory cell transistor Trm is disposed in an intersection region between the active region 2 and the word line WL.

  As shown in FIG. 1B, the gate electrode MG is formed on the P well 1a of the silicon substrate 1 through the gate insulating film 10 through the polycrystalline silicon layer 11, the intergate insulating film 12, the polycrystalline silicon layer 13, and the cobalt. It is formed by a laminated structure of the silicide layer 14, and no opening is provided in the intergate insulating film 12. Polycrystalline silicon layer 11 functions as floating gate electrode FG, and polycrystalline silicon layer 13 and cobalt silicide layer 14 function as control gate electrode CG. The memory cell transistor Trm includes a gate electrode MG and a source / drain region 1e composed of a low concentration impurity diffusion region 1c on both sides in the Y direction of the gate electrode MG. In this way, the gate electrode MG has a structure substantially similar to that of the gate electrode PG. Although not shown, a silicon nitride film 15 is also formed in the memory cell region M as a barrier film.

  In the above configuration, the SOG film 6 formed around the low voltage transistor Trp has an upper end 6a deeper than the height of the upper surface (surface) of the silicon substrate 1 in the vicinity of the contact region with the active region 2, and the high concentration impurity region 1b. The upper surface of the SOG film 6 is located at a depth d2 deeper than the depth d4 in the outer region than in the vicinity of the contact region. For this reason, the influence of the stress which the high concentration impurity region 1b receives from the SOG film 6 is relieved. As a result, the occurrence of dislocations in the silicon substrate 1 due to the stress of the crystal defects can be suppressed, the leakage current can be reduced, and the occurrence of device defects due to the occurrence of dislocations can be suppressed.

  Next, a manufacturing process of the low voltage transistor having the above configuration will be described. A description of the manufacturing method of the memory cell transistor Trm and other regions is omitted. In the following description, a general process may be added, or each process may be replaced and applied as necessary.

First, as shown in FIG. 3, after cleaning the P-type silicon substrate 1, a sacrificial oxide film 18 is formed for the purpose of preventing substrate contamination and resist collapse during lithography. Next, for the purpose of forming the well / channel region, a resist (not shown) is applied by lithography to open the region including the region where the transistor Trp is formed, and impurity ions such as B and BF2 are implanted, and the P well 1a Then, impurity ions for adjusting the threshold voltage of the transistor Trp are implanted again to form an N channel. However, when it is desired to keep the threshold voltage of the transistor Trp close to 0, impurity ion implantation is not necessary. Conversely, when the threshold voltage is negative and a depletion type transistor is desired, phosphorus (P) or arsenic (As) is used. N-type impurities such as are ion-implanted. Since the resist used as a mask at the time of impurity ion implantation is unnecessary, the resist is peeled off by O ₂ dry asher and chemical treatment. Thereafter, the impurity ions are activated by annealing.

Next, as shown in FIG. 4, after sacrificing the sacrificial oxide film 18 with hydrofluoric acid or the like, the gate insulating film 10 having a necessary thickness is formed by heating in a water vapor atmosphere, and the polycrystalline for the floating gate electrode FG is formed. A silicon layer 11, a processing silicon nitride film 19 and a silicon oxide film 20 are sequentially deposited by a CVD method. Thereafter, a resist (not shown) is applied and patterned by a normal lithography method, and the silicon oxide film 20 for processing is processed by an RIE (Reactive Ion Etching) method, followed by O ₂ dry asher processing and chemical processing. The resist is removed, and the polycrystalline silicon layer 11, the gate insulating film 10 and the upper portion of the silicon substrate 1 are etched by the RIE method using the processing silicon oxide film 20 as a mask to form a trench 4 in the silicon substrate 1 with a depth d1. To do. At this time, the region where the trench 4 is not processed and the stacked structure of the gate insulating film 10 and the polycrystalline silicon layer 11 remains becomes the active region 2.

  Next, as shown in FIG. 5, an HTO film 5 is formed along the inner surface of the trench 4 by LP-CVD, and then polysilazane for forming the SOG film 6 is applied, and the inside of the trench 4 is polysilazane. Fill with coating solution. Next, heat treatment is performed in an oxidizing atmosphere at 400 to 500 ° C. to convert the polysilazane coating solution into a silicon oxide film, thereby forming the SOG film 6.

  Next, as shown in FIG. 6, the SOG film 6 and the HTO film 5 are polished by the CMP (Chemical Mechanical Polishing) method using the silicon nitride film 19 as a stopper to perform a planarization process. 6 is embedded.

Next, as shown in FIG. 7, the SOG film 6 is etched back by the thickness of the silicon nitride film 19, and the silicon nitride film 19 is peeled off. Next, the inter-gate insulating film 12 for the memory cell transistor Trm is formed of a high dielectric film containing, for example, an ONO film, a NONON film, or alumina (Al ₂ O ₃ ).

  Next, as shown in FIG. 8, a polycrystalline silicon film 13 is deposited on the intergate insulating film 12. After forming the intergate insulating film 12 and before depositing the polycrystalline silicon film 13 thickly, the polycrystalline silicon film is deposited thinly to form an opening 12a in the intergate insulating film 12 for the low voltage transistor Trp. Thereafter, a polycrystalline silicon film 13 is deposited thickly. Thereby, the polycrystalline silicon film 13 and the polycrystalline silicon layer 11 are structurally contacted through the opening 12a.

  Next, as shown in FIG. 9, a silicon nitride film 21 is deposited by a CVD method as a mask material used when processing the gate electrode PG. Next, as shown in FIG. 10, patterning of the gate electrode PG is performed using photolithography and anisotropic etching (RIE). At this time, a resist is patterned on the silicon nitride film 21, the silicon nitride film 21 is etched to form a hard mask, and the polycrystalline silicon layer 13, the intergate insulating film 12, The crystalline silicon layer 11 is etched. At this time, the SOG film 6 is also etched back to the extent that its upper surface is located near the surface of the silicon substrate 1.

  Next, as shown in FIG. 11, ion implantation of N-type impurities is performed using the SOG film 6 constituting the gate electrode PG and the element isolation insulating film 3 as a mask, and on the surface layer of the silicon substrate 1 beside the gate electrode PG. An N-type low-concentration impurity region 1c in which the peak level of the impurity distribution is located at a depth d3 from the surface of the silicon substrate 1 is formed in a certain active region 2 as a whole. The low concentration impurity region 1c is provided for forming a source / drain having an LDD (Lightly Doped Drain) structure. The boundary line between the low-concentration impurity region 1c shown in FIG. 11 and the P-type region of the silicon substrate 1 covering the periphery of the lower portion indicates the peak level of the impurity distribution.

  Next, as shown in FIG. 12, a resist 22 is applied and patterned. As shown in the plan view of FIG. 13, the patterning remaining region of the resist 22 is a region that covers the active region 2 in a plan view and projects over a part of the element isolation insulating film 3 with a predetermined margin added. .

  Next, as shown in FIG. 14, the SOG film 6 is etched by the RIE method using the patterned resist 22 as a mask. This etching processing depth is a predetermined desired depth, for example, a depth deeper than the depth of the low-concentration impurity region 1c.

  Although a high voltage transistor (not shown) is separately formed in the flash memory device 1, the gate insulating film of the high voltage transistor is formed thicker than the gate insulating film 10 of the low voltage transistor Trp. In order to introduce a shallow impurity into the source / drain region of the high voltage transistor, it is necessary to remove the thick gate insulating film of the high voltage transistor. The etching process performed by the RIE method at this time is the same process as that process. You can go there. Thereby, the number of processes can be reduced.

  Next, as shown in FIG. 15, the resist 22 is removed by ashing or the like, a silicon oxide film 23 is deposited on the entire surface by the CVD method, and the silicon oxide film 23 is anisotropically etched by the RIE method. Spacer processing is performed so that the silicon oxide film 23 remains along the side walls of the crystalline silicon layer 11, the intergate insulating film 12, the polycrystalline silicon layer 13, and the silicon nitride film 21. Next, N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the surface layer of the silicon substrate 1 at a high concentration by an ion implantation technique. The concentration peak position of ion implantation at this time is adjusted to a position deeper than the deepest etching processing portion of the SOG film 6 by the RIE method described above, for example. In this ion implantation, the silicon is amorphized in the ion implantation region due to ion damage. The impurity peak distribution depths d3 and d4 depend on the ion species to be implanted and the acceleration voltage and implantation amount which are implantation conditions. A silicon oxide film 23 is formed as a spacer on the side wall of the gate electrode PG during the processing. The end of the high concentration impurity region 1 b is formed at a position along the outside of the silicon oxide film 23.

FIG. 16 schematically shows the three-dimensional structure at this time. As shown in FIG. 16, the active region 2 of the silicon substrate 1 is provided in a state surrounded by the element isolation insulating film 3.
Next, as shown in FIG. 17, wet etching with a hydrofluoric acid chemical solution is performed according to the thickness of the sidewall of the silicon oxide film 23 so that the silicon oxide film 23 remaining as the sidewall insulating film and spacer film can be removed. Process. By this wet etching process, the upper portion of the SOG film 6 is removed to be thicker than the film thickness of the silicon oxide film 23 formed on the side wall of the gate electrode PG.

  The element isolation insulating film 3 is deeper than the surface height of the silicon substrate 1 and shallower than the formation depth d2 of the high-concentration impurity diffusion region 1b, particularly in the contact region between the upper end 6a of the SOG film 6 and the active region 2. It is located at a height and is formed so as to be located deeper than the formation depth d2 as the distance from the region increases to the outer region.

  FIG. 18 schematically shows the three-dimensional structure at this time. As shown in FIG. 18, the SOG film 6 is isotropically removed by wet etching, and the gate electrode PG extends in the gate length direction to the upper surface of the element isolation insulating film 3. In the extended region of PG, element isolation insulation is provided on the side of the support portion in the gate width direction and below the side portion of the gate electrode PG with the support portion below the center in the gate width direction of the gate electrode PG remaining in the extended region. The film 3 (SOG film 6) is removed by etching.

  Since the minimum wet etching process is isotropically performed after the upper part of the SOG film 6 is etched by the RIE method, adverse effects on the gate insulating film 10 are suppressed. Although the amount of wet etching is limited by the film thickness of the silicon oxide film 23 formed on the side of the gate electrode PG, the upper portion of the SOG film 6 is removed in advance by the RIE method. Even if the thickness of the oxide film 23 is small, the removal process can be performed on the upper portion of the element isolation insulating film 3 by a necessary thickness.

  Next, activation of impurities introduced into the low concentration impurity region 1c and the high concentration impurity region 1b by ion implantation processing is performed by RTA (Rapid Thermal Annealing) to recover crystallinity. Thereby, the source / drain region 1d having the LDD structure can be formed in the active region 2. Since the heat treatment is performed after dropping the SOG film 6 in this manner, the heat treatment can be performed in a state in which the influence of high tensile stress by the SOG film 6 is reduced, and the occurrence of dislocation due to the RTA treatment can be suppressed. Can do. By performing this annealing process, a PN junction is formed between each of the N-type impurity regions 1b and 2c and the P-type silicon substrate 1, and the position of the PN junction is compared with the depth of the impurity peak distribution. And become a little deeper. The upper surface position of the element isolation insulating film 3 in the contact region may be adjusted to the active region 2 in accordance with the depth of the PN junction.

  Next, as shown in FIG. 19, a TEOS oxide film 7 is formed by LP-CVD so as to cover the upper surface and side surfaces of the gate electrode PG, the upper surface of the active region 2 and the upper exposed surface of the element isolation insulating film 3. Subsequently, a silicon nitride film 8 is formed by LP-CVD.

  Next, as shown in FIG. 20, a BPSG film 9 is buried beside the gate electrode PG by a CVD method as a non-coating type oxide film, and thereafter a melt treatment is performed to suppress the generation of voids. Thus, planarization is performed by polishing using the silicon nitride film 8 as a stopper.

  Next, as shown in FIG. 21, the silicon nitride film 8, the TEOS oxide film 7, and the silicon nitride film 21 are removed, the BPSG film 9 is etched back, and the polycrystalline silicon layer 13 constituting the gate electrode PG is formed. The upper surface is exposed. In FIG. 19, the upper surface of the BPSG film 9 and the upper surface of the polycrystalline silicon layer 13 are made to coincide with each other, but the polycrystalline silicon layer 13 may protrude from the upper surface of the BPSG film 9.

  Next, as shown in FIG. 22, the upper part of the polycrystalline silicon layer 13 is formed as cobalt silicide layer 14 from cobalt (Co), and a silicon nitride film 15 is formed as a barrier film on the entire surface. In the formation of the cobalt silicide layer 14, the exposed surface of the polycrystalline silicon layer 13 is washed from the state shown in FIG. 13 by a wet etching process or the like, and then a cobalt film is formed. The upper part of the silicon layer 13 is partially reacted to be silicided to form the cobalt silicide layer 14. After silicidation, unreacted metal is peeled off, and a silicon nitride film 15 is formed as a barrier insulating film for preventing contamination by the cobalt silicide layer 14. Note that after the unreacted metal is peeled off, the silicon nitride film 15 may be formed after heat treatment is performed again.

  Next, as shown in FIG. 23, a TEOS oxide film having a predetermined thickness is formed as the interlayer insulating film 16 by plasma CVD. Next, contact holes 17a and wiring grooves 18a are formed by photolithography and RIE, and a conductor is embedded in the contact holes 17a and wiring grooves 18a to form contact plugs 17 and wiring layers 18 as shown in FIG. To do. The buried conductor forms a laminated structure of titanium (Ti) / titanium nitride (TiN) as a barrier metal, and then tungsten (W) is filled by a CVD method. Thereby, the structure shown in FIG. 1 can be obtained. Although the subsequent steps are not shown in the figure, they are further followed by an upper-layer multilayer wiring process.

  According to the present embodiment, the SOG film 6 constituting the element isolation insulating film 3 is embedded in the trench 4, and the element isolation insulating film 3 is formed on the surface of the silicon substrate 1 in the contact region with the active region 2. It is located at a depth deeper than that and shallower than the formation depth d4 (or PN junction) of the high-concentration impurity diffusion region 1b, which is the peak concentration of the source / drain region 1d, and as it moves away from that region, Can be formed deeper than the depth d4, the tensile stress exerted on the active region 2 by the SOG film 6 can be relieved, and RTA can be performed after ion implantation of high-concentration impurities to form an LDD structure. The generation of dislocations due to crystal defects that are likely to occur in the treatment can be suppressed.

  For example, in the case of a high-voltage transistor, the gate insulating film formed on the semiconductor substrate 2 is thicker than the gate insulating film 10 of the low-voltage transistor Trp in order to increase the breakdown voltage. Therefore, when a process for processing the gate insulating film of the high voltage transistor is necessary, the height adjustment of the element isolation insulating film 3 around the high voltage transistor is relatively easy.

  In the case of the low voltage transistor Trp, since the gate insulating film 10 is relatively thin, it is not necessary to process the gate insulating film of the high voltage transistor and simultaneously drop the element isolation insulating film. For this reason, the element isolation insulating film 3 does not drop significantly before the wet etching process. Therefore, particularly in the peripheral region of the low-voltage transistor Trp, the dropping process of the element isolation insulating film 3 by the RIE method in a state where the active region 2 is covered with a mask before dropping by wet etching has a great effect on suppressing crystal defects. Play.

  Since the upper portion of the element isolation insulating film 3 is processed by the RIE method in a state where the resist mask 22 is formed so as to cover the entire region of the active region 2, the silicon substrate 1 can be prevented from gouging and the short channel effect of the transistor can be prevented. it can.

  Since the wet etching process is performed after the upper portion of the SOG film 6 constituting the element isolation insulating film 3 is removed in advance by the RIE method, the wet etching removal amount can be reduced, and the gate insulating film 10 is adversely affected. And the characteristic deterioration of the low voltage transistor Trp can be suppressed.

  Since this wet etching process is isotropic, an area that cannot be removed in advance by the RIE method can also be etched. Since the resist 22 is covered up to the region beyond the boundary between the active region 2 and the element isolation insulating film 3, the surface of the silicon substrate 1 in the active region 2 is processed at the same time as the etching process by the prior RIE method. Therefore, the device characteristics can be kept good.

  In the wet etching process of the element isolation insulating film 3, the side wall insulating film 23 as the spacer of the LDD structure is also removed at the same time, so that the number of processes can be reduced. In addition, when the sidewall insulating film 23 is treated so as to remain on the sidewall of the contact portion with the gate insulating film 10 when wet etching is performed, the reliability of the gate insulating film 10 can be kept high.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.

  Although the semiconductor substrate is applied to the P-type silicon substrate 1, a substrate in which a P-well is formed on the surface layer of the N-type silicon substrate may be applied, and the type of the semiconductor substrate is not limited. Although applied to a low-voltage n-channel MOSFET, it may be applied to a p-channel MOSFET if the impurity species doped in each region is changed.

  Although the embodiment in which the cobalt silicide layer 14 is formed on the gate electrode PG is shown, the present invention may be applied to a metal gate structure in which tungsten (W), tantalum (Ta), or the like is applied as the gate electrode PG.

  Further, although the description is made on the basis of the impurity peak distribution depth d2 of the high concentration impurity region 1b, more strictly, the impurity depth becomes slightly deeper after the RTA process after the ion implantation. Originally, the distribution obtained from the profile in the depth direction after ion implantation does not match the distribution after impurities are diffused by activation annealing. However, the activation annealing temperature after ion implantation has increased with the miniaturization of semiconductor element formation technology. Since the temperature is lowered, the distribution peak position after ion implantation and the depth of the peak distribution (PN junction) after annealing are slightly different, but can be regarded as almost coincident.

The longitudinal cross-sectional view of the principal part which shows one Embodiment of this invention Plan view schematically Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 1) Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 2) Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 3) Vertical sectional view schematically showing one stage of the manufacturing process (No. 4) Vertical sectional view schematically showing one stage of the manufacturing process (No. 5) Vertical sectional view schematically showing one stage of the manufacturing process (No. 6) Vertical sectional view schematically showing one stage of the manufacturing process (No. 7) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 8) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 9) 10 is a longitudinal sectional view schematically showing one stage of the manufacturing process. Plan view schematically showing one stage of the manufacturing process (part 1) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 11) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 12) Schematic diagram showing three stages of the manufacturing process (Part 1) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 13) Schematic diagram that shows one stage of the manufacturing process in three dimensions (Part 2) Vertical sectional view schematically showing one stage of the manufacturing process (No. 14) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 15) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 16) Vertical sectional view schematically showing one stage of the manufacturing process (No. 17) 18 is a longitudinal sectional view schematically showing one stage of the manufacturing process.

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 1d is a source / drain region, 2 is an active region, 3 is an element isolation insulating film, 4 is a trench (groove), 6 is an SOG film (coating insulating film), 9 Indicates a BPSG film (non-coated insulating film), and PG indicates a gate electrode.

Claims (5)

A semiconductor substrate having an active region partitioned by forming a groove having a first depth from the substrate surface around the surface;
A gate electrode formed on a part of the active region via a gate insulating film;
A source having an exposed surface that is formed in the active region on both sides of the gate electrode at a second depth that is shallower than the first depth from the surface of the semiconductor substrate and exposed on the sidewall of the trench. / Drain region;
An element isolation insulating film embedded in the groove including a coating type insulating film;
The gate electrode extends from the active region onto the element isolation insulating film,
The element isolation insulating film in the region where the gate electrode is not located above is located at a height deeper than the surface height of the semiconductor substrate and shallower than the second depth in the vicinity of the contact region with the active region. The semiconductor device is located deeper than the second depth in the outer region than in the vicinity of the contact region.   2. The semiconductor device according to claim 1, wherein the gate electrode is a gate electrode of a low voltage transistor. Forming a groove around the active region of the first conductivity type semiconductor substrate;
Embedding an element isolation insulating film including a coating type insulating film in the groove to form an element isolation region;
Forming a gate electrode on the active region through a gate insulating film;
Introducing an impurity into the active region using the gate electrode as a mask to form a low-concentration impurity introduction region of a second conductivity type opposite to the first conductivity type;
Forming a spacer film for forming an LDD (Lightly Doped Drain) structure along the sidewall of the gate electrode;
Forming a second conductivity type high concentration impurity introduction region in the active region using the gate electrode and the spacer film as a mask;
Forming a mask pattern so as to cover a contact end portion of the element isolation insulating film between the active region and the element isolation region;
Removing a predetermined thickness of the upper part of the element isolation insulating film in the groove in a region excluding the contact end of the element isolation insulating film using the mask pattern as a mask;
Peeling the mask pattern;
Wet etching the upper portion of the element isolation insulating film in the groove including the contact end portion of the element isolation insulating film and the spacer film;
Heat treatment to activate the impurities;
Forming a non-coating insulating film on the element isolation insulating film. A method for manufacturing a semiconductor device.   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the mask pattern, the mask pattern is formed so as to cover the entire region of the active region.   5. The method of manufacturing a semiconductor device according to claim 3, wherein in the wet etching process, the spacer film is also removed at the same time.

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