KR101044385B1

KR101044385B1 - Method for manufacturing semiconductor device

Info

Publication number: KR101044385B1
Application number: KR20040049354A
Authority: KR
Inventors: 박정구
Original assignee: 매그나칩 반도체 유한회사
Priority date: 2004-06-29
Filing date: 2004-06-29
Publication date: 2011-06-29
Also published as: KR20060000483A

Abstract

The present invention discloses a method of manufacturing a semiconductor device capable of preventing the occurrence of sub-defects and reducing the sheet resistance of the source / drain regions. The disclosed method comprises the steps of providing a silicon substrate having active and field regions defined therein; Sequentially forming a pad oxide film and a pad nitride film exposing the field region on the silicon substrate; Etching a field region of the exposed substrate to form a trench; Filling the trench by sequentially forming first and second oxide films having opposite stresses on the entire surface of the resultant substrate; Performing a rapid heat treatment process on the resultant; Forming a device isolation layer by CMPing the second and first oxide layers until the pad nitride layer is exposed; Removing the pad nitride film; Simultaneously removing the pad oxide layer and partially removing the device isolation layer to expose the upper sidewall of the trench; Forming a gate electrode on the active region of the substrate; Forming a source / drain region by implanting high concentration ions into the active side of the substrate and the exposed sidewalls of the trench using the gate electrode as a mask; And selectively forming a silicide layer on surfaces of the gate electrode and the source / drain regions.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the related art.

2A through 2E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

40: silicon substrate 41: pad oxide film

42: pad nitride film 41a: patterned pad oxide film

42a: patterned pad nitride film 43: trench

44: first oxide film 45: second oxide film

44a: remaining first oxide film 45a: remaining second oxide film

46 device isolation film 47 gate oxide film

48 polysilicon film 49 gate electrode

50: LDD region 51: spacer

52 source / drain region 53 silicide layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a class of 0.13 μm or less. The present invention relates to a method of manufacturing a semiconductor device for improving the characteristics of the device by reducing the sheet resistance of the source / drain regions by increasing the surface area of the silicide layer selectively formed on the surface of the source / drain regions.

As is well known, recent semiconductor devices use an STI process to form device isolation films for electrical separation between devices. This has the disadvantage of reducing the device formation area in connection with the conventional LOCOS device isolation film having a bird's-beak of the beak shape at the edge thereof, while the device by the STI process This is because the separator can be formed in a small width.

As the semiconductor device is highly integrated, the junction depth of the source / drain regions may be reduced in order to prevent short channel effects due to a decrease in the gate length of the transistor and to secure a margin for punch through. It is necessary to form a shallow junction depth while at the same time reducing the parasitic resistance of the source / drain regions, such as sheet resistance.

For this purpose, a salicide process for selectively forming a metal silicide layer on the surfaces of the gate and the source / drain regions becomes essential, and the silicide layer includes titanium-silicide, cobalt-silicide and tantalum-silicide. Etc. are available.

Hereinafter, a method of manufacturing a 0.13 μm or less semiconductor device using a conventional STI process and a salicide process will be described.

1A to 1E are cross-sectional views illustrating processes for manufacturing a semiconductor device according to the related art.

In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1A, a pad oxide film 11 and a pad are formed on a silicon substrate 10 in which an active region (not shown) and a field region (not shown) are defined. The nitride film 12 is formed in order. In this case, the pad oxide film 11 is formed to a thickness of 100 ~ 150Å, the pad nitride film 12 is formed to a thickness of 1500 ~ 2000Å.

Subsequently, as illustrated in FIG. 1B, the pad nitride film and the pad oxide film are patterned to expose the field region of the substrate 10. Next, the trench 13 is formed by etching the field region of the exposed substrate 10. In this case, reference numeral 11a, which is not described in FIG. 1A, shows a patterned pad oxide film, and 12a shows a patterned pad nitride film.

Subsequently, as shown in FIG. 1C, a high density plasma (HDP) oxide film 14 is formed to bury the trench 13 in the entire surface of the resulting substrate. At this time, the HDP oxide film 14 is formed to a thickness of 6000 Å.

Then, as shown in FIG. 1D, the HDP oxide film is chemically mechanically polished (CMP) until the pad nitride film is exposed to form an isolation layer 14a. Then, the pad nitride film and the pad oxide film are removed.

Subsequently, the gate electrode 17 is formed on the active region of the substrate 10. In this case, the gate electrode 17 has a structure in which the gate oxide film 15 and the polysilicon film 16 are sequentially stacked. Thereafter, low concentration ion implantation is performed on the substrate 10 using the gate electrode 17 as a mask to form a lightly doped drain (LDD) region 18.

Next, as shown in FIG. 1E, spacers 19 are formed on both sidewalls of the gate electrode 17. Thereafter, a high concentration of ion implantation is performed on the semiconductor substrate 10 using the gate electrode 17 including the spacer 19 as a mask to form a source / drain region 20.

Thereafter, a salicide process is performed to reduce the sheet resistance of the gate electrode 17 and the source / drain region 20, thereby selectively selecting the surface of the gate electrode 17 and the source / drain region 20. The silicide layer 21 is formed.

However, according to the conventional method of forming a device isolation layer using the STI process, the edge of the active region has a sharp shape after the trench formation. In such a structure, the etching stress and the trench generated during the trench etching are formed. The mechanical stress and the like in the deposition of HDP oxides for embedding are concentrated in the trench bottom corners, so that sub-defects such as dislocations occur at these sites. Sub-defects lead to deterioration of device characteristics, such as leakage current characteristics, as well as lower yields.

In addition, according to the related art, a silicide layer is selectively formed on the surface of the gate and the source / drain regions in order to reduce the resistance of the gate and the source / drain regions. There is a limit to the increase, which causes a problem of difficulty in reducing the resistance.

Accordingly, the present invention has been made to solve the above problems, by preventing the occurrence of sub-defects, it is possible to prevent the leakage current generation to improve the characteristics and yield of the device, the silicide of the surface of the source / drain region It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving the characteristics of the device by reducing the sheet resistance of the source / drain regions by increasing the surface area of the layer.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: providing a silicon substrate in which an active region and a field region are defined; Sequentially forming a pad oxide film and a pad nitride film exposing the field region on the silicon substrate; Etching a field region of the exposed substrate to form a trench; Filling the trench by sequentially forming first and second oxide films having opposite stresses on the entire surface of the resultant substrate; Performing a rapid heat treatment process on the resultant; Forming an isolation layer by CMPing the second and first oxide layers until the pad nitride layer is exposed; Removing the pad nitride film; Simultaneously removing the pad oxide layer and partially removing the device isolation layer to expose the upper sidewall of the trench; Forming a gate electrode on the active region of the substrate; Forming a source / drain region by implanting high concentration ions into the active side of the substrate and the exposed sidewalls of the trench using the gate electrode as a mask; And selectively forming a silicide layer on surfaces of the gate electrode and the source / drain regions.

Here, an HDP oxide film having a compressive stress is used as the first oxide film, and an HLD oxide film having a tensile stress is used as the second oxide film. The first oxide film is formed to a thickness of 3000 kPa, and the second oxide film is formed to a thickness of 3000 kPa. In addition, the rapid heat treatment process is carried out for 30 seconds using N2 at a temperature of 1000 ℃.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, a pad oxide film 41 is formed on a silicon substrate 40 in which an active region (not shown) and a field region (not shown) are defined. And the pad nitride film 42 are formed in this order. In this case, the pad oxide film 41 is formed to a thickness of 100 ~ 150Å, the pad nitride film 42 is formed to a thickness of 1500 ~ 2000Å.

Subsequently, as shown in FIG. 2B, the pad nitride film and the pad oxide film are patterned to expose the field region of the substrate 40. Thereafter, the field region of the exposed substrate 40 is etched to form the trench 43 having a predetermined depth. In this case, reference numeral 41a, which is not described in FIG. 2B, denotes a patterned pad oxide film and 42a, respectively, shows a patterned pad nitride film.

Subsequently, as shown in FIG. 2C, the trench 43 is buried by sequentially forming the first oxide film 44 and the second oxide film 45 having opposite stresses on the entire surface of the resultant substrate. Here, the second oxide film is used as the first oxide film 44 using an oxide film having a compressive stress (hereinafter referred to as an HDP oxide film having a compressive stress) formed by performing a high density plasma (HDP) process. As the reference numeral 45, an oxide film having a tensile stress (hereinafter referred to as an HLD oxide film having a tensile stress) formed by performing a high temperature low pressure deposition (HLD) process is used. In addition, the first oxide film 44 is formed to a thickness of 3000 kPa, and the second oxide film 45 is formed to a thickness of 3000 kPa.

On the other hand, when the trench 43 is double-filled by using the HDP oxide film and the HLD oxide film having opposite stresses as described above, it is possible to prevent the mechanical stress from being concentrated on the bottom corner of the trench 43. Accordingly, it is possible to prevent the occurrence of sub-defects such as dislocations in the bottom corner portion of the trench 43.

The resultant is then subjected to a rapid thermal process (RTP) process. At this time, the rapid heat treatment process is carried out for 30 seconds using N2 at a temperature of 1000 ℃. In this case, the rapid heat treatment process is performed to densify the first oxide film 44 and the second oxide film 45.

Then, as shown in FIG. 2D, the device isolation layer 46 is formed by CMPing the second oxide layer and the first oxide layer until the pad nitride layer is exposed. Here, the device isolation layer 46 has a double structure of the remaining first oxide film 44a and the remaining second oxide film 45a.

Then, the pad nitride film is removed using a phosphoric acid solution. Subsequently, the pad oxide layer is removed using an HF solution, and the upper corner of the isolation layer 46 is partially removed to expose the upper sidewall of the trench 43.

Subsequently, a gate electrode 49 is formed on the active region of the substrate 40. In this case, the gate electrode 49 has a structure in which the gate oxide film 47 and the polysilicon film 48 are sequentially stacked. Thereafter, low concentration ion implantation is performed on the substrate 40 using the gate electrode 49 as a mask to form the LDD region 50.

Next, as shown in FIG. 2E, spacers 51 are formed on both side walls of the gate electrode 49. Then, using the gate electrode 49 including the spacer 51 as a mask, a high concentration of ion implantation is performed on the active side of the substrate 40 and the exposed sidewall of the trench 43 to perform source / drain regions. Form 52.

Subsequently, a silicide process is performed to reduce the sheet resistance of the gate electrode 49 and the source / drain regions 52 to selectively form a silicide layer on the surfaces of the gate electrode 49 and the source / drain regions 52. 53 is formed. In this case, since the source / drain regions 52 are formed on the exposed sidewalls of the trench 43, the surface area of the silicide layer 53 on the surface of the source / drain regions 52 is increased. Accordingly, the sheet resistance of the source / drain region 52 is reduced, thereby improving the characteristics of the device.

As described above, the present invention double fills the trenches using the HDP oxide film having the compressive stress and the HLD oxide film having the tensile stress, thereby preventing the mechanical stress from being concentrated at the bottom corner of the trench, thereby reducing the sub- Defects can be prevented from occurring. Therefore, the present invention can improve the leakage current characteristic by the sub-defect to improve the characteristics and the yield of the device.

In addition, the present invention can partially increase the surface area of the silicide layer on the surface of the source / drain regions by removing part of the isolation layer so that the upper sidewall of the trench is exposed. Accordingly, the present invention can improve the characteristics of the device by reducing the sheet resistance of the source / drain region.

Claims

Providing a silicon substrate in which an active region and a field region are defined;

Sequentially forming a pad oxide film and a pad nitride film exposing the field region on the silicon substrate;

Etching a field region of the exposed substrate to form a trench;

Filling the trench by sequentially forming first and second oxide films having opposite stresses on the entire surface of the resultant substrate;

Performing a rapid heat treatment process on the resultant;

Forming a device isolation layer by CMPing the second and first oxide layers until the pad nitride layer is exposed;

Removing the pad nitride film;

Simultaneously removing the pad oxide layer and partially removing the device isolation layer to expose the upper sidewall of the trench;

Forming a gate electrode on the active region of the substrate;

Forming a source / drain region by implanting high concentration ions into the active side of the substrate and the exposed sidewalls of the trench using the gate electrode as a mask; And

And forming a silicide layer on surfaces of the gate electrode and the source / drain regions.

The method of claim 1, wherein an oxide film having a compressive stress formed by a high density plasma (HDP) process is used as the first oxide film, and a high temperature low pressure deposition (HLD) process is performed as the second oxide film. And an oxide film having a tensile stress formed by using the same.

The method of claim 1, wherein the first oxide film is formed to a thickness of 3000 kPa.

The method of claim 1, wherein the second oxide film is formed to a thickness of 3000 kPa.

The method of claim 1, wherein the rapid heat treatment process is performed for 30 seconds using N 2 at a temperature of 1000 ° C. 3.