KR100370154B1 - Method for manufacturing of semiconductor device - Google Patents
Method for manufacturing of semiconductor device Download PDFInfo
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- KR100370154B1 KR100370154B1 KR10-2000-0022856A KR20000022856A KR100370154B1 KR 100370154 B1 KR100370154 B1 KR 100370154B1 KR 20000022856 A KR20000022856 A KR 20000022856A KR 100370154 B1 KR100370154 B1 KR 100370154B1
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- trench
- semiconductor substrate
- oxide film
- forming
- manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Abstract
본 발명은 소자의 크기를 줄이기 위한 반도체 소자의 제조 방법으로서, 활성영역 및 필드영역이 정의된 반도체 기판의 활성영역에 소정깊이를 갖는 트랜치를 형성하는 단계; 상기 트랜치 양측의 반도체 기판 표면내에 트랜치보다 깊게 절연막을 형성하는 단계; 상기 트랜치를 포함한 전면에 게이트 산화막, 전도막을 차례로 형성하는 단계; 상기 전도막 및 게이트산화막을 선택적으로 제거하여 상기 트랜치 및 반도체 기판상에 게이트 라인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device for reducing the size of a device, comprising: forming a trench having a predetermined depth in an active region of a semiconductor substrate in which an active region and a field region are defined; Forming an insulating layer deeper than a trench in a surface of the semiconductor substrate on both sides of the trench; Sequentially forming a gate oxide film and a conductive film on the entire surface including the trench; And selectively removing the conductive layer and the gate oxide layer to form a gate line on the trench and the semiconductor substrate.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 낸드(NAND) 롬 제조시 트랜치 기법과 베리드(buried) 절연 방법을 이용함으로서 소자의 크기를 줄일 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device which can reduce the size of a device by using a trench technique and a buried insulation method in manufacturing a NAND ROM.
반도체 소자가 집적화되면서 가장 중요한 기술로 대두되고 있는 것이 인접소자간의 격리문제이다.As semiconductor devices are integrated, the most important technology has emerged as a problem of isolation between adjacent devices.
이것은 기본적으로 소자간의 펀치스루(Punch through)를 최소화하면서 전체회로의 크기를 최소화하기 위해서이다.This is basically to minimize the size of the entire circuit while minimizing punch through between devices.
예를 들어, 낸드 롬 제조시 반도체 기판을 활성영역과 필드영역으로 구분하여 활성영역상에 게이트 라인을 형성하는데 활성영역간의 격리를 위해 필드 영역상에 필드산화막을 형성한다.For example, in NAND fabrication, a semiconductor substrate is divided into an active region and a field region to form a gate line on the active region. A field oxide film is formed on the field region for isolation between the active regions.
요즘은 1970년대 개발된 LOCOS(Local Oxidation of Silicon)공정이 일반화되어 상기 필드산화막을 형성하는데 사용되고 있다.Nowadays, a LOCOS (Local Oxidation of Silicon) process developed in the 1970s has been generalized and used to form the field oxide film.
LOCOS 공정이란 산화막이 반도체 기판의 필드영역에 선택적으로 형성되게 하는 것으로 먼저, 반도체 기판에 패드산화막과 산화를 억제하는 질화막을 차례로 형성하고, 사진공정 및 식각공정을 통해 활성영역상의 패드산화막과 질화막을 남겨놓은 채 필드영역의 상기 패드산화막과 질화막을 제거하여 질화막 패턴을 형성한다.In the LOCOS process, an oxide film is selectively formed in a field region of a semiconductor substrate. First, a pad oxide film and a nitride film for inhibiting oxidation are sequentially formed on the semiconductor substrate, and the pad oxide film and the nitride film in the active region are formed through a photo process and an etching process. While leaving the pad oxide film and the nitride film in the field region, the nitride film pattern is formed.
여기서 절연특성을 향상시키기 위해 채널 스톱 도펀트(Channel stop dopant)를 필드영역에 선택적으로 주입하면 셀프 얼라인 필드 산화막을 형성할 수 있다.In this case, if a channel stop dopant is selectively injected into the field region to improve the insulating property, a self-aligned field oxide film may be formed.
이어, 선택적 산화를 진행하면 질화막 패턴이 있는 부분은 산화되지 않고 선택적으로 반도체 기판을 잠식하면서 LOCOS 구조를 이루게 된다.Subsequently, when the selective oxidation is performed, the portion having the nitride film pattern is not oxidized, and selectively encroaches the semiconductor substrate, thereby forming a LOCOS structure.
이 때, 반도체 기판이 일정량 잠식되고, 또한 질화막 패턴의 양측 하부에도 새부리(Bird's beak)모양의 산화막이 성장된다.At this time, the semiconductor substrate is eroded by a certain amount, and an oxide film in the shape of a bird's beak is also grown on both lower portions of the nitride film pattern.
그리고, 선택적 산화의 보호막으로 사용된 상기 질화막 패턴은 제거한 후 낸드 롬 셀 형성 공정을 진행한다.In addition, the nitride film pattern used as the protective film for the selective oxidation is removed and then the NAND cell formation process is performed.
그러나 상기와 같은 종래의 반도체 소자의 제조 방법에 있어서 필드산화막 형성 때 새부리(Bird's beak) 모양의 산화막이 생기기 때문에 최소 필드 영역에 대한 디자인 룰(Design Rule)이 존재하게 된다.However, in the conventional method of manufacturing a semiconductor device as described above, when a field oxide film is formed, a bird's beak-shaped oxide film is formed, and thus a design rule for a minimum field region exists.
즉, 소자간의 격리 및 절연 역할을 하는 필드 산화막의 전체 크기가 게이트 라인의 크기보다 커지므로 소자의 크기 또한 커지는 문제점이 있다.That is, since the overall size of the field oxide film serving as isolation and isolation between devices becomes larger than the size of the gate line, there is a problem that the size of the device also increases.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 소자의 크기를 줄이기 위한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for manufacturing a semiconductor device for reducing the size of the device to solve the above problems.
도 1은 본 발명에 의한 반도체 소자의 제조 방법.1 is a method of manufacturing a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
10 : 반도체 기판 11 : 필드산화막10 semiconductor substrate 11 field oxide film
12 : 버퍼산화막 12a : 버퍼산화막패턴12: buffer oxide film 12a: buffer oxide film pattern
13 : 포토레지스트 14 : 트랜치13: photoresist 14: trench
15 : 절연막 16 : 게이트산화막15 insulating film 16 gate oxide film
17a, 17b : 게이트라인17a, 17b: gate line
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은 활성영역 및 필드영역이 정의된 반도체 기판의 활성영역에 소정깊이를 갖는 트랜치를 형성하는 단계와, 상기 트랜치 양측의 반도체 기판 표면내에 트랜치보다 깊게 절연막을 형성하는 단계와, 상기 트랜치를 포함한 전면에 게이트 산화막, 전도막을 차례로 형성하는 단계와, 상기 전도막 및 게이트산화막을 선택적으로 제거하여 상기 트랜치 및 반도체 기판상에 게이트 라인을 형성하는 단계를 포함하여 형성함을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a trench having a predetermined depth in an active region of a semiconductor substrate in which an active region and a field region are defined, and a surface of the semiconductor substrate on both sides of the trench; Forming an insulating film deeper than a trench in the trench, sequentially forming a gate oxide film and a conductive film on the entire surface including the trench, and selectively removing the conductive film and the gate oxide film to form a gate line on the trench and the semiconductor substrate. It characterized by including the step of forming.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1e는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 1a에 도시한 바와 같이, 활성영역과 필드영역으로 정의된 반도체 기판(10)의 필드영역에 필드산화막(11)을 형성하고, 상기 반도체 기판(10) 전면에 버퍼산화막(12)을 형성한다.As shown in FIG. 1A, a field oxide film 11 is formed in a field region of a semiconductor substrate 10 defined as an active region and a field region, and a buffer oxide film 12 is formed over the semiconductor substrate 10. .
도 1b 및 1c에 도시한 바와 같이, 전면에 포토레지스트(13)를 도포하여 노광 및 현상공정을 통해 패터닝을 하고, 상기 패터닝된 포토레지스트(13)를 마스크로 버퍼산화막(12)을 선택적으로 제거하여 버퍼산화막 패턴(12a)을 형성한다.As shown in FIGS. 1B and 1C, the photoresist 13 is coated on the entire surface to be patterned through an exposure and development process, and the buffer oxide film 12 is selectively removed using the patterned photoresist 13 as a mask. The buffer oxide film pattern 12a is formed.
상기 버퍼산화막 패턴(12a)을 마스크로 상기 반도체 기판(10)의 활성영역을 선택적으로 제거하여 게이트 라인을 형성하기 위한 트랜치(14)를 형성하고, 상기 패터닝된 포토레지스트(13)는 제거한다.A trench 14 for forming a gate line is formed by selectively removing the active region of the semiconductor substrate 10 using the buffer oxide layer pattern 12a as a mask, and the patterned photoresist 13 is removed.
도 1d에 도시한 바와 같이, 상기 트랜치(14)의 내부 측벽과 트랜치(14) 내부 바닥의 구석까지 불순물 이온이 주입될 수 있도록 소오스/드레인 영역(도시되지 않음)과 다른 타입의 불순물 이온을 틸트(Tilt) 이온 주입을 통해 주입 한 후 열처리 공정을 진행하여 트랜치(14) 양측의 반도체 기판 표면내에 트랜치(14)보다 더 깊게, 즉 트랜치(14) 내부의 측벽 및 구석에 절연막(15)을 형성한다.As shown in FIG. 1D, the source / drain regions (not shown) and other types of impurity ions are tilted so that impurity ions can be implanted into the inner sidewall of the trench 14 and the corner of the bottom of the trench 14. After implanting through the (Tilt) ion implantation, a heat treatment process is performed to form the insulating film 15 deeper than the trench 14 in the semiconductor substrate surfaces on both sides of the trench 14, that is, in the sidewalls and corners of the trench 14. do.
상기 절연막(15)은 반도체 기판상의 게이트라인과 트랜치 내에 형성될 게이트라인 간을 절연시키는 역할을 한다.The insulating layer 15 serves to insulate the gate line on the semiconductor substrate from the gate line to be formed in the trench.
도 1e에 도시한 바와 같이, 상기 버퍼산화막 패턴(12a)을 제거한 후 상기 트랜치(14)를 포함한 전면에 게이트 산화막(16)을 형성하고, 상기 게이트 산화막(16)상에 게이트용 폴리 실리콘막을 형성한다.이어, 통상적인 포토 및 식각공정을 통해 상기 폴리 실리콘막 및 게이트 산화막(16)을 선택적으로 제거하여 상기 트랜치(14) 및 반도체 기판(10)상에 게이트 라인(17a,17b)을 형성한다.As shown in FIG. 1E, after the buffer oxide layer pattern 12a is removed, a gate oxide layer 16 is formed on the entire surface including the trench 14, and a gate polysilicon layer is formed on the gate oxide layer 16. Next, the polysilicon layer and the gate oxide layer 16 are selectively removed through a conventional photo and etching process to form gate lines 17a and 17b on the trench 14 and the semiconductor substrate 10. .
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조 방법에 있어서 트랜치를 형성하여 트랜치 내부 및 반도체 기판 표면을 모두 게이트 라인으로 사용할 수 있어 소자의 사이즈를 줄일 수 있는 효과가 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a trench may be formed, and both the inside of the trench and the surface of the semiconductor substrate may be used as gate lines, thereby reducing the size of the device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR10-2000-0022856A KR100370154B1 (en) | 2000-04-28 | 2000-04-28 | Method for manufacturing of semiconductor device |
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| KR10-2000-0022856A KR100370154B1 (en) | 2000-04-28 | 2000-04-28 | Method for manufacturing of semiconductor device |
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| KR20010104452A KR20010104452A (en) | 2001-11-26 |
| KR100370154B1 true KR100370154B1 (en) | 2003-01-29 |
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