KR100983514B1 - Method for fabrication of semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can reduce the complexity of the process and the increase in manufacturing costs due to a plurality of mask processes performed for bit line contact in the cell region and the peripheral region. That is, in the conventional process, a pattern and an etching process are performed by separating contact between a cell region and a peripheral region when forming a bit line contact. In the present invention, an active region (eg, an NMOS transistor) of a contact of a cell region and a peripheral region is performed. After contacting and patterning the contact connecting the source / drain region, and etching under a condition having a high selectivity, the contact connecting the gate conductive layer and the active region (eg, source / drain region) of the PMOS transistor After forming a separate mask pattern, the contact is etched under an etching condition having a selectivity to form an open portion, and subsequently, a boron ion implantation process is performed to reduce the contact resistance of the PMOS transistor, thereby performing ion implantation into the active region of the PMOS transistor. A separate mask forming step may be omitted. Therefore, the price competitiveness of the semiconductor device can be improved.

NMOS transistors, PMOS transistors, merge, bit line contacts.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}             

1A-1I are cross-sectional views illustrating a bit line contact forming process according to the prior art.

2A to 2G are cross-sectional views illustrating a bit line contact forming process according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 substrate 101 field insulating film

102 well 103 gate insulating film

104: first conductive film 105: second conductive film

106: hard mask 107: spacer

108: first insulating film 109: plug

110: second insulating film 118: ion implantation

112, 112, 115, 116, 117: open section for bit line contacts

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can simplify the process by reducing the mask pattern process.

As the pattern of the semiconductor device becomes finer, bit line contacts are separated from the cell region and the peripheral region, and the contact etching of the cell region is performed by etching only the oxide film used as the interlayer insulating layer. Therefore, since the etching target is small, the contact etching of the peripheral region has to be etched to the level of the nitride film used as the gate hard mask and the substrate as the active region. In addition, in the case of a P-type metal oxide semiconductor (PMOS) transistor, an additional ion implantation process is added to the contact region to reduce the contact resistance after the etching process for the bit line contact. In this case, ion implantation is mainly performed using boron.

1A to 1I are cross-sectional views illustrating a bit line contact forming process according to the prior art, and looks at the conventional bit line contact forming process in a cell region and a peripheral region with reference to the drawing.

The field insulating film 11 is locally formed on the substrate 10 on which various elements for forming a semiconductor device are formed. The field insulating film 11 may be formed using a shallow trench isolation (STI) or a LOCal oxidation of silicon (LOCOS) method, and is mainly formed using a silicon oxide film.

The well 12 is formed in the peripheral region, and is formed through etching, ion implantation, and thermal diffusion processes, and the specific formation process is well known and thus will be omitted. Here, a P-well is formed in a region where an N-type metal oxide semiconductor (NMOS) transistor is formed, and an N-well is formed in a region where a PMOS transistor is formed.

A gate electrode pattern having a structure in which the gate insulating layer 13, the first and second conductive layers 14 and 15, and the hard mask 16 are stacked on the substrate 10 is formed.

The gate insulating film 13 mainly uses an oxide film series, and the first and second conductive films 14 and 15 use a single or combined structure of polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like.

The hard mask 16 prevents the first and second conductive films 14 and 15 from being attacked in a subsequent process such as SAC etching, and also electrically shorts between the first and second conductive films 14 and 15 and the subsequent plug. Serves to prevent. For this purpose, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as the hard mask 16 material.

A buffer insulating layer is deposited along the profile in which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 17 on the side of the gate electrode pattern.

The spacer 17 forms an LDD structure source / drain in the substrate 10 or the well 12 on the side of the gate electrode pattern by ion implantation and prevents attack on the side of the gate electrode pattern during the SAC process.

Therefore, the nitride film is formed alone or in various structures such as an oxide film and a nitride film laminated or a nitride film / oxide film / nitride film structure. The nitride film used here includes a silicon oxynitride film or a silicon nitride film.                         

Source / drain regions (not shown) that extend from the surface of the substrate 10 to a predetermined depth are formed in the substrate 10 or the well 12 on the side of the gate electrode pattern by ion implantation and thermal diffusion.

In order to prevent the hot carrier effect due to the short channel, a low level impurity doping and a spacer 17 are formed, and then a high level impurity doping is performed again to form a conventional structure.

Subsequently, a first insulating layer 18 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed.

The first insulating layer 18 may be an oxide film such as a BOSG (Boro Phospho Silicate Glass) film, a BSG (Boro Silicate Glass) film, a PSG (Phospho Silicate Glass) film, a TEOS (Tetra Ethyl Ortho Silicate) film, or an HDP (High Density Plasma) oxide film. Use a series of materials.

Meanwhile, as the high integration increases, the vertical height of the gate electrode pattern increases, thereby increasing the aspect ratio between the gate electrode patterns, resulting in gap-fill defects when the first insulating layer 18 is deposited.

In order to prevent this, recently, an SOD film having excellent gap-fill characteristics is applied, and a heat treatment process is performed to densify the film.

Meanwhile, in order to prevent the spacer 17 from being lost in a subsequent SAC process before deposition of the first insulating layer 18, an etch stop layer may be further formed using a nitride-based material.

Subsequently, an SAC forming photoresist pattern (not shown) is formed on the first insulating layer 18 to form a plug to be electrically connected to the source / drain regions in the cell region.

Meanwhile, a hard mask may be additionally formed between the first insulating layer 18 and the photoresist pattern. In this case, since the wavelength of the exposure source is shortened due to the high integration, the thickness of the photoresist must be thin to transmit short wavelengths in order to form a pattern, thereby compromising the weakening of the function of the photoresist pattern as an etching mask. It is for.

The hard mask material film has a low thickness because the etching process is performed with a thickness of a thin photoresist pattern. However, since the etching selectivity is required for the oxide film material mainly used for interlayer insulation, the nitride film material film is mainly used. .

Next, an open portion (not shown), that is, a contact hole, which exposes the source / drain region of the side of the gate electrode pattern in the cell region by performing a SAC etching process to etch the first insulating layer 18 using the photoresist pattern as an etching mask. To form. In the SAC process, an underlying layer (ie, the first insulating layer 18) is etched using an oxide film and a nitride film having an etching selectivity with respect to a fluorine-based gas. Subsequently, a photoresist strip process is performed to remove the photoresist pattern. Meanwhile, the photoresist strip process may be performed after the SAC etching process.

Subsequently, a plug forming conductive film is deposited on the entire surface of the open portion, or the open portion is buried by using selective epitaxial growth (hereinafter referred to as SEG) to be electrically connected to the source / drain region of the exposed cell region. do.                         

Subsequently, the plugs 19 isolated from each other are removed by performing a local surface etching or chemical mechanical polishing (CMP) process only in the cell region to remove the conductive film so as to planarize with the upper portion of the hard mask 16. Form.

Here, a polysilicon film is mainly used as the conductive film for forming the plug 19, and in addition, a tungsten film, a Ti film, a TiN film, or the like can be used.

The process of forming the plug 19 is also referred to as a landing plug contact (hereinafter referred to as LPC) -1 process, and some of the plugs 19 are connected to the bit line contacts by a subsequent process. It is connected to a storage node contact.

The second insulating layer 20 is formed on the entire surface including the cell region and the peripheral region. The second insulating layer 20 uses an oxide film-based material film similar to the first insulating layer 18 described above. 1A shows a process cross section in which the second insulating film 20 is formed.

As shown in FIG. 1B, a photoresist pattern 21 for forming bit line contacts in the cell region is formed on the second insulating layer 20, and a conventional photolithography process is applied.

As shown in FIG. 1C, the second insulating layer 20 is selectively etched using the photoresist pattern 21 as an etch mask to open the plug 19 to expose the plug 19 of the plug 19 in the cell region. The part 22 is formed.

Subsequently, a photoresist strip process may be performed to remove the photoresist pattern 21, and then an etch byproduct is removed through a cleaning process.

As shown in FIG. 1D, a photoresist is applied to the entire surface of the bit line contact opening 22, and then the source / side of the side of the gate electrode pattern on which the bit line contact is to be made in the peripheral area through an exposure and development process. A photoresist pattern 23 is formed to expose the drain region and the second conductive film 15 of the gate electrode pattern.

As illustrated in FIG. 1E, the second insulating layer 20 and the first insulating layer 18 are etched using the photoresist pattern 23 as an etch mask, so that the source / drains on the side of the gate electrode pattern where the bit line contact is made in the peripheral region. Open portions 24a and 24c exposing the regions are formed, and at the same time, the second insulating layer 20 and the gate hard mask 16 are etched to form a bit line contact in the peripheral region. The open portions 24b and 24d exposing the 15 are formed.

Subsequently, the photoresist strip process may be performed to remove the photoresist pattern 23, and then the etching by-products are removed through the cleaning process.

FIG. 1F shows a process cross section in which a plurality of open portions 22, 24a to 24d are formed to form a bit line contact in a cell region and a peripheral region.

As shown in FIG. 1G, a photoresist is applied to the entire surface where the plurality of open parts 22, 24a to 24d are formed to form a bitline contact, and then a bitline contact of a peripheral area is made through an exposure and development process. A photoresist pattern 25, which is a mask for selective ion implantation, is formed in a region corresponding to the PMOS transistor in the region. Therefore, only the open portions 24c and 24d in the PMOS transistor region are exposed.

As shown in FIG. 1H, a selective ion implantation 26 process is performed on the open portions 24c and 24d in the PMOS transistor region using the photoresist pattern 25 as an ion implantation mask.

One of the most troublesome things in developing semiconductor devices is the manufacture of PMOS transistors. This is because the only P-type dopant is boron (B), which is the root of all problems. In the periodic table of elements, in addition to boron, Group 3 elements include Al (Aluminum) and In (Indium). However, Al and In have low solubility. For example, when Al is implanted, it does not mix well with silicon, but after annealing, they do not do high doping because they stick together. In addition, since Al lowers the breakdown voltage of the silicon oxide film when it acts on the silicon oxide film, it is not possible to use it as a dopant in the PMOS transistor since the absolute temperature should not be increased after Al is covered.

In addition, In has high solubility as well as ionization energy, and, for example, when doping 100, only 10 of them generate holes, and thus the activation rate is low. However, it may be used for low doping such as threshold voltage (Vt) ion implantation.

Therefore, it is no exaggeration to say that only boron is used as a P-type dopant. Boron has good solubility and ionization rate, but has an atomic number of 5, which makes the particles small and light. Therefore, even if you want to inject lightly into the surface during the ion implantation, when hitting the ion implanter into the depth of the substrate, even if a little heat is applied, the diffusion rate (Diffusibity) is large, the deep diffusion will enter. In addition, P or As, which are N-type dopants, do not diffuse any more when they encounter silicon oxide, but boron passes through.

Therefore, the impurity concentration of boron in the source / drain region of the PMOS transistor is reduced during the series of processes after forming the source / drain region of the PMOS transistor and the etching process for forming the open portion 24c. Since the contact resistance is proportional to the impurity concentration, the concentration of boron eventually causes an increase in the contact resistance.

In order to prevent such an increase in contact resistance, boron ion implantation is separately performed.

Subsequently, as shown in FIG. 1I, the photoresist strip process is performed to remove the photoresist pattern 25, and then the etching by-products are removed through the cleaning process. Here, reference numeral 27 denotes a source / drain region of the PMOS transistor in which the impurity concentration of boron is increased by additional boron ion implantation.

Meanwhile, in the above-described conventional process, three mask processes are required in both the cell region and the peripheral region for the bit line contact, and thus, not only the process is complicated but also the manufacturing cost is increased.

The present invention is proposed to solve the above problems of the prior art, a semiconductor that can reduce the complexity of the process and the increase in manufacturing costs due to a plurality of mask process for the bit line contact in the cell region and the peripheral region It aims at providing the manufacturing method of an element.

In order to achieve the above object, the present invention comprises the steps of forming a gate electrode pattern in which a conductive film and a hard mask are sequentially stacked on each region of the substrate in which the cell region and the peripheral region are defined; Forming a first source / drain region for an NMOS transistor and a second source / drain region for a PMOS transistor in a substrate of the peripheral region; Forming a first insulating film on the entire surface of the substrate; Etching the first insulating layer to form a plurality of contact holes exposing the substrate of the cell region; Forming a plurality of plugs filling the contact holes; Forming a second insulating film on an entire surface of the substrate including the plug; Forming a first open portion through which the plug is exposed by etching the second insulating layer by using a first photoresist pattern as an etch mask, and etching the second insulating layer and the first insulating layer to expose the first source / drain region. Forming a second open portion; Removing the first photoresist pattern; The second insulating layer and the hard mask are etched using a second photoresist pattern as an etch mask to form a third open portion exposing the conductive film of the gate electrode pattern in the peripheral area, and the second insulating layer and the first insulating layer are etched. Forming a fourth open portion exposing the second source / drain region; Implanting ions into the third and fourth open portions using the second photoresist pattern as an ion implantation mask; And it provides a semiconductor device manufacturing method comprising the step of removing the second photoresist pattern.

In the conventional process scheme, when forming a bit line contact, the contact between the cell region and the peripheral region is separated and the pattern and etching process is performed separately. In the present invention, the active region of the contact of the cell region and the NMOS transistor of the peripheral region ( For example, after merging and patterning a contact connecting the source / drain region, the wafer is etched under a condition having a high selectivity, and then an active region (eg, source / drain) of the contact and the PMOS transistor connected to the gate conductive layer. The contacts connecting the regions) are etched under an etching condition having a selectivity after forming a separate mask pattern to form an open portion, and subsequently performing a boron ion implantation process to reduce the contact resistance of the PMOS transistor. It is possible to omit a separate mask forming process for ion implantation into the region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2G are cross-sectional views illustrating a bit line contact forming process according to an exemplary embodiment of the present invention, with reference to which a bit line contact forming process in a cell region and a peripheral region of the present invention will be described.

The field insulating film 101 is locally formed on the substrate 100 on which various elements for forming a semiconductor device are formed. The field insulating film 101 may be formed using an STI or LOCOS method, and is mainly formed using a silicon oxide film.

Subsequently, the well 102 is formed in the peripheral region where the NMOS transistor and the PMOS transistor are to be formed. The well 102 is formed through etching, ion implantation, and thermal diffusion processes, and the specific formation process is well known and thus will be omitted. Here, the P-well is formed in the region where the NMOS transistor is formed, and the N-well is formed in the region where the PMOS transistor is formed.

A gate electrode pattern having a structure in which the gate insulating layer 103, the first and second conductive layers 104 and 105, and the hard mask 106 are stacked on the substrate 100 is formed.

The gate insulating film 103 mainly uses an oxide film series, and the first and second conductive films 104 and 105 use a single or combined structure of polysilicon, tungsten, tungsten silicide, tungsten nitride, or the like.

The hard mask 106 prevents the first and second conductive films 104 and 105 from being attacked in a subsequent process such as SAC etching, and also an electrical short between the first and second conductive films 104 and 105 and the subsequent plug. Serves to prevent. For this purpose, a silicon oxynitride film, a silicon oxide film, or a silicon nitride film is mainly used as a hard mask 106 material.

A buffer insulating layer is deposited along the profile on which the gate electrode pattern is formed, and then the entire surface is etched to form a spacer 107 on the side of the gate electrode pattern.

The spacer 107 is to form a source / drain region of the LDD structure in the substrate 100 or the well 102 on the side of the gate electrode pattern by ion implantation and to prevent the attack on the side of the gate electrode pattern during the SAC process. .                     

Therefore, the nitride film is formed alone or in various structures such as an oxide film and a nitride film laminated or a nitride film / oxide film / nitride film structure. The nitride film used here includes a silicon oxynitride film or a silicon nitride film.

Here, the reason why the stacked structure including the oxide film is formed is that the oxide film has a lower dielectric constant than the nitride film, so that the parasitic capacitance is low, thereby improving the refresh characteristics.

Source / drain regions (not shown) extended from the surface of the substrate 100 to a predetermined depth by ion implantation and thermal diffusion are formed in the substrate 100 (cell region) and the well 102 (peripheral region) on the side of the gate electrode pattern. .

In order to prevent the hot carrier effect due to the short channel, a low level impurity doping and a spacer 107 are formed, followed by a high level impurity doping to form a conventional structure.

Accordingly, the transistor forming process including the gate electrode pattern and the source / drain regions in the cell region and the peripheral region, respectively, is completed.

Subsequently, a first insulating film 108 for interlayer insulation is formed on the entire structure where the gate electrode pattern is formed.

The first insulating layer 108 may be formed of an oxide film-based material such as a BPSG film, a BSG film, a PSG film, a TEOS film, or an HDP oxide film.

On the other hand, as the high integration increases the vertical height of the gate electrode pattern, the aspect ratio between the gate electrode patterns increases, resulting in gap-fill defects when the first insulating layer 108 is deposited. In order to prevent this, recently, an SOD film having excellent gap-fill characteristics is applied, and a heat treatment process is performed to densify the film.

Meanwhile, in order to prevent the spacer 107 from being lost in a subsequent SAC process before deposition of the first insulating layer 108, an etch stop layer may be further formed using a nitride-based material.

Subsequently, an SAC forming photoresist pattern (not shown) is formed on the first insulating layer 108 to form a plug to be electrically connected to the source / drain regions in the cell region.

Meanwhile, a hard mask may be additionally formed between the first insulating layer 108 and the photoresist pattern. In this case, since the wavelength of the exposure source is shortened due to the high integration, the thickness of the photoresist must be thin to transmit short wavelengths in order to form a pattern, thereby compromising the weakening of the function of the photoresist pattern as an etching mask. It is for.

The hard mask material film has a low thickness because the etching process is performed with a thickness of a thin photoresist pattern. However, since the etching selectivity is required for the oxide film material mainly used for interlayer insulation, the nitride film material film is mainly used. .

Subsequently, an open portion (not shown), that is, a contact hole, exposing a source / drain region on the side of the gate electrode pattern in the cell region by performing a SAC etching process to etch the first insulating layer 108 using the photoresist pattern as an etching mask. To form. In the SAC process, an underlying layer (ie, the first insulating layer 108) is etched using an oxide film and a nitride film having an etching selectivity with respect to a fluorine-based gas. Subsequently, a photoresist strip process is performed to remove the photoresist pattern. Meanwhile, the photoresist strip process may be performed after the SAC etching process.

Subsequently, a plug forming conductive film is formed on the entire surface where the open portion is formed to be electrically connected to the source / drain region of the exposed cell region by embedding the open portion using a deposition or SEG method.

Subsequently, a plurality of plugs 109 isolated from each other are formed by performing a local front etch or CMP process only in the cell region to remove the conductive film so as to planarize with the top of the hard mask 106.

Here, a polysilicon film is mainly used as the conductive film for forming the plug 109. In addition, a tungsten film, a Ti film, a TiN film, or the like can be used.

The process of forming the plug 109 is also referred to as an LPC-1 process, and some of the plugs 109 are connected to the bit line contacts by a subsequent process, and others are connected to the storage node contacts.

The second insulating layer 110 is formed on the entire surface including the cell region and the peripheral region. The second insulating layer 110 uses an oxide-based material film similar to the first insulating layer 108 described above. 2A shows a process cross section in which the second insulating layer 110 is formed.

As shown in FIG. 2B, a photoresist pattern 111 is formed on the second insulating layer 110 to form a bit line contact in the cell region. A conventional photolithography process is applied.

Meanwhile, in the present invention, a process of opening an active region (eg, a source / drain region) of an NMOS transistor in a peripheral region is simultaneously performed in a process for forming a bit line contact in the cell region. To do this, the mask is merged to open the bit line contacts in both regions.

Subsequently, the second open layer 110 may be selectively etched using the photoresist pattern 111 as an etch mask in the cell region to expose the plug 109 in which the bit line contact of the plug 109 is to be made. At the same time, the second insulating layer 110 and the first insulating layer 108 are etched using the photoresist pattern 111 as an etch mask in the NMOS transistor formation region of the peripheral region, and the source on the side of the gate electrode pattern where the bit line contact is to be made. A second open portion 113 exposing the / drain region is formed. In this case, an etching process for increasing an etching selectivity between the hard mask 106 made of nitride film and the second insulating film made of oxide film is applied in the cell region, such as C ₄ F ₆ , C ₄ F ₈ , or C ₅ F ₈ . It is preferable to use gas.

Subsequently, a photoresist strip process may be performed to remove the photoresist pattern 111, and then an etching by-product is removed through a cleaning process.

FIG. 2C illustrates a process cross section in which first and second open portions 112 and 113 are formed to form bit line contacts in the source / drain regions of the NMOS transistors in the cell region and the peripheral region, respectively.

As shown in FIG. 2D, a photoresist is applied to the entire surface where the first and second open portions 112 and 113 for bit line contacts are formed in the cell region and the source / drain regions of the NMOS transistor, respectively, followed by an exposure and development process. The photoresist pattern 114 for exposing the source / drain regions of the side surfaces of the gate electrode patterns of the PMOS transistors and the second conductive films 105 of the gate electrode patterns of the NMOS transistors and the PMOS transistors to form bit line contacts in the peripheral region through ).

As shown in FIG. 2E, the second insulating layer 110 and the first insulating layer 108 are etched using the photoresist pattern 114 as an etch mask, so that the source / drain of the side of the gate electrode pattern where the bit line contact is made in the PMOS transistor. A fourth open portion 116 is formed to expose the region, and at the same time, the second insulating layer 110 and the gate hard mask 106 of the NMOS transistor and the PMOS transistor are etched to form a second line of the gate electrode pattern for bit line contact. Third open portions 115 and 117 exposing the conductive film 105 are formed.

As shown in FIG. 2F, the photoresist pattern 114 is used as a mask for selective ion implantation in a region corresponding to the PMOS transistor among the regions where the bit line contact is to be made without removing the photoresist pattern 114. Using the resist pattern 114 as an ion implantation mask, a selective ion implantation 118 process using boron is performed to the third open portions 115 and 117 in the PMOS transistor region.

At this time, ion implantation is also performed in the second conductive film 105 of the gate electrode of the NMOS transistor, but it does not affect the conduction characteristics at all.

Subsequently, as shown in FIG. 2G, the photoresist strip process is performed to remove the photoresist pattern 114, and then the etching by-products are removed through the cleaning process. Here, reference numeral 119 denotes an area where the impurity concentration of boron is increased by additional boron ion implantation.

According to the present invention, the bit line contact in the cell region and the bit line contact in the source / drain region of the NMOS transistor in the peripheral region are performed with one mask, and the source / drain region of the PMOS transistor in the peripheral region is provided. By performing the bit line contact of the gate electrode and the gate electrode of the NMOS transistor and the boron additional ion implantation of the PMOS transistor with one mask, three mask processes are required in both the cell region and the peripheral region for the bit line contact in the conventional process. Through the embodiment it was found that can be reduced to a process using only two mask patterns.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the bit line contact forming process is taken as an example. In addition, the present invention may be applied to a contact forming process required simultaneously in the cell region and the peripheral region.

As described above, the present invention can reduce the mask process, and ultimately, it can be expected to have an excellent effect of improving the price competitiveness of semiconductor devices.

Claims (6)

Forming a gate electrode pattern in which a conductive film and a hard mask are sequentially stacked on each area of the substrate where the cell region and the peripheral region are defined; Forming a first source / drain region for an NMOS transistor and a second source / drain region for a PMOS transistor in a substrate of the peripheral region; Forming a first insulating film on the entire surface of the substrate; Etching the first insulating layer to form a plurality of contact holes exposing the substrate of the cell region; Forming a plurality of plugs filling the contact holes; Forming a second insulating film on an entire surface of the substrate including the plug; Forming a first open portion through which the plug is exposed by etching the second insulating layer by using a first photoresist pattern as an etch mask, and etching the second insulating layer and the first insulating layer to expose the first source / drain region. Forming a second open portion; Removing the first photoresist pattern; The second insulating layer and the hard mask are etched using a second photoresist pattern as an etch mask to form a third open portion exposing the conductive film of the gate electrode pattern in the peripheral area, and the second insulating layer and the first insulating layer are etched. Forming a fourth open portion exposing the second source / drain region; Implanting ions into the third and fourth open portions using the second photoresist pattern as an ion implantation mask; And Removing the second photoresist pattern Semiconductor device manufacturing method comprising a. The method of claim 1, And the first to fourth open parts are open parts for bit line contacts. The method of claim 1, At the time of the ion implantation, ion implantation using boron (B) as a dopant. The method of claim 1, The gate electrode pattern formed in the peripheral region includes a gate electrode pattern of an NMOS transistor and a gate electrode pattern of a PMOS transistor. The method of claim 1, In the step of forming the first and second open portion, a semiconductor device manufacturing method characterized in that using any one of C ₄ F ₆ , C ₄ F ₈ or C ₅ F ₈ gas. The method of claim 1, The first insulating film and the second insulating film is a semiconductor device manufacturing method, characterized in that the oxide film series.

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