KR20040000681A - Method of manufacturing Bi-CMOS transistor - Google Patents

Abstract

PURPOSE: A Bi-CMOS(Bipolar-Complementary Metal Oxide Semiconductor) transistor manufacturing method, is provided to be capable of securing the performance of the Bi-CMOS transistor and simplifying manufacturing processes. CONSTITUTION: After forming a substrate(1) having isolation layers(5), the first to third well(7a,7b,7c) are formed at the inner portion of the substrate. The first and second silicon epitaxial layer(8,9) are selectively formed at the upper portion of the first well. A plurality of gate electrodes(11) are formed at a CMOS transistor forming region. At this time, a polysilicon pattern(11a) is formed at the upper portion of the second silicon epitaxial layer of a bipolar transistor forming region. A P type source/drain region(14) is formed at the surface of the third well and a P+ type impurity region(14a) is simultaneously formed at the bipolar transistor forming region. Then, an N type source/drain region(16) is formed at the surface of the second well and an N+ impurity region(16a) is simultaneously formed at the bipolar transistor forming region. An interlayer dielectric(17) is thickly deposited on the entire surface of the resultant structure.

Description

Bi-CMOS transistor manufacturing method {Method of manufacturing Bi-CMOS transistor}

The present invention relates to a bi-MOS transistor manufacturing method, and more particularly, to a bi-MOS transistor manufacturing method that can obtain a process simplification while ensuring the performance of the bipolar transistor.

Bi-CMOS transistors utilize the advantages of CMOS transistors and the advantages of Bipolar transistors to provide high density CMOS transistors, high-speed driving capability, low power consumption, As a semiconductor device incorporating a high-precision bipolar transistor, it is suitable for implementing high-speed VLSI and is widely used for cache memories and the like.

Such Bi-CMOS has CMOS transistors composed of NMOS and PMOS in one area of the substrate, and emitter, base, and collector in other areas of the substrate. The bipolar transistor consisting of) is integrated, wherein the CMOS transistor and the bipolar transistor are simultaneously integrated through a series of processes.

However, although not shown and described, in the conventional Bi-CMOS transistor, as the design rule of the semiconductor device decreases, the scale down of the MOS transistor is rapidly progressing, so that the current gain of the bipolar transistor is increased. In addition, there is a limit to increase the drive current (drive current), so, there is a difficulty in securing performance.

In addition, conventional Bi-CMOS transistors, as is well known to those skilled in the art, simultaneously produce a bipolar transistor and a CMOS transistor through a series of processes, so that the manufacturing process is very complicated due to the inclusion of many process steps.

Accordingly, an object of the present invention is to provide a method for manufacturing a Bi-CMOS transistor that can achieve process simplification while securing the performance of a bipolar transistor.

1A to 1G are cross-sectional views illustrating processes for manufacturing a Bi-CMOS transistor according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 silicon substrate 2 pad oxide film

3: pad nitride film 4: trench

4a: groove 5: device isolation film

6: buffer oxide film 7a, 7b, 7c: well

8: first silicon epi layer 9: second silicon epi layer

10 gate oxide film 11 gate electrode

11a: polysilicon pattern 12: spacer

13: first ion implantation mask 14: P-type source / drain region

14a: P-type impurity region 15: second ion implantation mask

16: N-type source / drain region 16a: N-type impurity region

17: interlayer insulating film 18: contact plug

19a, 19b, 19c, 19d, 19e, 19f, 19g: wiring

In order to achieve the above object, the present invention comprises the steps of providing a silicon substrate having a first region in which the bipolar transistor is to be formed and the second and third regions in which the CMOS transistor is to be formed; Forming trenches and grooves in portions corresponding to device isolation regions of the substrate and in the center of the first region of the substrate; Embedding an oxide film in the trenches and the groove to form the trench isolation device; A buffer oxide layer is formed on the substrate, and a first conductive type well is formed by ion implanting impurities of a first conductivity type into the first and third regions of the substrate, and a second conductive type is formed in the second region of the substrate. Implanting impurities into the second conductive wells; Patterning the buffer oxide layer to expose the groove of the first region and a portion adjacent thereto, and removing the oxide layer in the exposed groove; Growing a first silicon epi layer doped with a first conductive type as a collector and a base material and a second silicon epi layer doped with a second conductive type on the groove and the substrate surface adjacent thereto; Removing the buffer oxide film; Forming a gate oxide layer on the second and third regions of the substrate; Forming a polysilicon film on the substrate including the gate oxide film; Patterning the polysilicon layer and the gate oxide layer to form gate electrodes on the second and third regions of the substrate, and simultaneously forming a polysilicon pattern as an emitter material on the second silicon epi layer of the first region; ; Forming spacers on both sidewalls of the gate electrode, the polysilicon pattern, and the stacked layer of the first silicon epi layer and the second silicon epi layer; Forming a first ion implantation mask on the substrate resultant to cover the first region and the second region except for a portion of the first region including an end portion of the second silicon epilayer not adjacent to the second region of the substrate; Impurities of the second conductivity type are implanted into the substrate region not covered by the first ion implantation mask to form an impurity region of the second conductivity type on the exposed portion of the first region, and a second surface of the third region. Forming a conductive source / drain region; Removing the first ion implantation mask and forming a second ion implantation mask on the substrate to cover a region of the substrate not covered by the first ion implantation mask; The first conductive type impurity region is formed on the surface of the exposed first region portion by implanting impurities of the first conductivity type in the substrate region not covered by the second ion implantation mask, and the surface of the second region is formed on the surface of the second region. Forming a source / drain region of a first conductivity type; Removing the second ion implantation mask and forming an interlayer insulating film on the substrate; First and second conductive impurity regions of the first substrate and the polysilicon pattern, and first and second conductive source / drain regions of the second and third regions of the substrate; It provides a method of manufacturing a bi-MOS transistor comprising the step of forming each of the wiring contacts.

Here, the first conductive type is N type, and the second conductive type is P type, and the first well is formed deeper than the second and third wells.

In addition, the ion implantation of the impurities of the first and second conductivity types implants the first and second silicon epitaxial layers of the exposed first region.

According to the present invention, since the bipolar transistor is formed in a buried type, its performance can be ensured, and the process can be simplified because the emitter of the bipolar transistor is formed simultaneously with the gate electrode of the CMOS transistor.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating processes for manufacturing a Bi-CMOS transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a silicon substrate 1 having a bipolar transistor formation region and a CMOS transistor formation region composed of NMOS and PMOS is provided, and a pad oxide film 2 and a pad nitride film are formed on the substrate 1. (4) are formed in sequence. Subsequently, in a state in which a photoresist pattern (not shown) defining device isolation regions is formed on the pad nitride layer 3, the pad nitride layer and the pad oxide layer are etched using the photoresist layer as an etch barrier, and subsequently, an exposed substrate. The portions are etched to form trenches 4 in each of the isolation regions of the substrate 1. In this case, a trench 4a is formed in the bipolar transistor formation region during the trench formation so that the buried bipolar transistor can be formed.

Referring to FIG. 1B, in a state where the photoresist pattern, the pad nitride film, and the pad oxide film are removed, an oxide film is deposited on the entire region of the substrate 1 so that the trench 4 and the groove 4a are buried, and then the surface of the substrate The oxide film is subjected to chemical mechanical polishing (CMP) until the exposed portion to form the trench isolation device isolation layers 5. Next, a buffer oxide film 6 is deposited on the substrate 1 including the device isolation layers 5, and impurities of a predetermined conductivity type are implanted into the substrate 1 using a well mask (not shown). By doing so, the first, second and third wells 7a, 7b, and 7c are formed in place of the substrate 1.

At this time, the first well 7a formed in the bipolar transistor formation region of the substrate 1 and the third well 7c formed in the CMOS transistor formation region spaced apart from the first well 7a are first conductive type. And a second well 7b formed in the CMOS transistor formation region between the first well 7a and the third well 7c, for example, an N-well. Form into P-wells. In addition, the first well 7a is formed deeper than the second and third wells 7b and 7c.

Referring to FIG. 1C, the portion of the buffer oxide film deposited on the bipolar transistor formation region of the substrate 1 including the upper region of the groove 4a to form the buried bipolar transistor is removed by a known photolithography process, and then The oxide film embedded in the groove 4a is removed by wet etching.

Then, the first silicon epi layer 8 doped with the same conductivity type as the first well 7a, that is, N-type impurities, as a collector material of the bipolar transistor on the groove 4a and the substrate surface adjacent thereto. And a second doped on the first silicon epi layer 8 as a base material of a bipolar transistor and doped with an impurity opposite to the first silicon epi layer 8, that is, a P-type impurity. The silicon epi layer 9 is grown.

Referring to FIG. 1D, the gate oxide film 10 is deposited on the entire region of the substrate 1 in a state where the buffer oxide film is removed, and then on the bipolar transistor formation region A of the substrate 1 by a known method. The gate oxide film portion deposited on the etch is removed.

Then, a polysilicon film is deposited on the entire region of the substrate 1 including the gate oxide film 10, and then the polysilicon film and the gate oxide film are etched by using a gate mask (not shown). The gate electrode 11 is formed in the CMOS transistor formation region of (). At this time, during the etching of the polysilicon layer, the polysilicon pattern 11a is formed as an emitter material on the second silicon epitaxial layer 9 formed in the bipolar transistor formation region.

Subsequently, an insulating film for spacers is deposited on the entire region of the substrate 1, and then the poly-layer formed on both sidewalls of the gate electrode 11 formed in the CMOS transistor forming region by blanket etching the insulating film. Spacers 12 are formed on both sidewalls of the laminated film of the silicon pattern 11a and the first and second silicon epitaxial layers 8 and 9.

Referring to FIG. 1E, a photosensitive film is coated on the resultant up to the above step, and the photosensitive film is exposed and developed to form a first ion implantation mask 13 for implanting high concentration ions of P-type impurities. Here, the first ion implantation mask 13 may exclude the substrate region of the bipolar transistor formation region not adjacent to the second well 7b in the CMOS transistor formation region and the second silicon epi layer portion A adjacent thereto. The bipolar transistor forming region and the CMOS transistor forming region cover the second well 7b region.

Subsequently, a high concentration of P-type impurities are implanted into the exposed substrate regions using the first ion implantation mask 13, and thereby, P-type impurities are formed on the surface of the third well 7c of the CMOS transistor forming region. The P + impurity region 14a is formed on the surface of the exposed bipolar transistor formation region portion A while simultaneously forming the source / drain regions 14 of.

Referring to FIG. 1F, in a state in which a first ion implantation mask is removed, an inverted form of the first ion implantation mask is exposed on the substrate 1, that is, a region of the substrate covered by the first ion implantation mask is exposed. The second ion implantation mask 15 is formed. Then, N-type impurities are implanted at high concentration into the exposed substrate regions using the second ion implantation mask 15, whereby N-type impurities are formed on the surface of the second well 7b of the CMOS transistor forming region. Source / drain regions 16 are formed, and at the same time, N + impurity regions 16a are formed in the substrate portion B of the exposed bipolar transistor formation region. At this time, impurities are also doped in the exposed polysilicon pattern 11a, that is, the emitter of the bipolar transistor.

Referring to FIG. 1G, in a state in which the second ion implantation mask is removed, an interlayer insulating layer 17 is deposited on the resultant layer up to the above step, and the surface thereof is planarized through a CMP process. Then, predetermined portions of the planarized interlayer insulating film 17 are selectively etched to form a second silicon epi layer portion A, a P-type impurity region 14a, and a poly-doped P-type impurity in the bipolar transistor formation region. N-type and P-type source / drain regions 14 and 16 in the silicon pattern 11a, the second silicon epi layer portion B doped with the N-type impurity, and the N-type impurity region 16a and the CMOS transistor formation region. ), And then contact holes are formed on the interlayer insulating layer 17 to fill the contact holes, and then CMP is formed to form contact plugs.

Then, a conductive film is deposited on the interlayer insulating film 17, and then patterned to form first, second, and third wirings 19a, 19b, and 19c contacting the emitter, base, and collector portions of the bipolar transistor. Fourth and fifth wirings 19d and 19e in contact with the source / drain regions 16 of the NMOS transistor, and sixth and seventh wirings 19f and 19g in contact with the source / drain regions 14 of the PMOS transistor. ), And as a result, the Bi-CMOS transistor according to the present invention is completed.

In the method of the present invention as described above, the emitter of the bipolar transistor is simultaneously formed using polysilicon for the gate electrode of the CMOS transistor, so no separate process for forming the emitter is necessary.

In addition, the width of the base increases with respect to the bipolar transistor formed in a buried type, so that its performance can be improved over the conventional.

As described above, the present invention can increase the base width because the bipolar transistor is buried, and thus, in the trend of decreasing design rules, it is possible to prevent performance degradation of the bipolar transistor as the base width is reduced. Can be.

In addition, since the emitter of the bipolar transistor is simultaneously formed using the gate poly, the present invention can omit an additional step for forming the emitter, so that the process simplification can be obtained as compared with the prior art.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (5)

Providing a silicon substrate having a first region where a bipolar transistor is to be formed and a second and third region where a CMOS transistor is to be formed; Forming trenches and grooves in portions corresponding to device isolation regions of the substrate and in the center of the first region of the substrate; Embedding an oxide film in the trenches and the groove to form the trench isolation device; A buffer oxide layer is formed on the substrate, and a first conductive type well is formed by ion implanting impurities of a first conductivity type into the first and third regions of the substrate, and a second conductive type is formed in the second region of the substrate. Implanting impurities into the second conductive wells; Patterning the buffer oxide layer to expose the groove of the first region and a portion adjacent thereto, and removing the oxide layer in the exposed groove; Growing a first silicon epi layer doped with a first conductive type as a collector and a base material and a second silicon epi layer doped with a second conductive type on the groove and the substrate surface adjacent thereto; Removing the buffer oxide film; Forming a gate oxide layer on the second and third regions of the substrate; Forming a polysilicon film on the substrate including the gate oxide film; Patterning the polysilicon layer and the gate oxide layer to form gate electrodes on the second and third regions of the substrate, and simultaneously forming a polysilicon pattern as an emitter material on the second silicon epi layer of the first region; ; Forming spacers on both sidewalls of the gate electrode, the polysilicon pattern, and the stacked layer of the first silicon epi layer and the second silicon epi layer; Forming a first ion implantation mask on the substrate resultant to cover the first region and the second region except for a portion of the first region including an end portion of the second silicon epilayer not adjacent to the second region of the substrate; Impurities of the second conductivity type are implanted into the substrate region not covered by the first ion implantation mask to form an impurity region of the second conductivity type on the exposed portion of the first region, and a second surface of the third region. Forming a conductive source / drain region; Removing the first ion implantation mask and forming a second ion implantation mask on the substrate to cover a region of the substrate not covered by the first ion implantation mask; The first conductive type impurity region is formed on the surface of the exposed first region portion by implanting impurities of the first conductivity type in the substrate region not covered by the second ion implantation mask, and the surface of the second region is formed on the surface of the second region. Forming a source / drain region of a first conductivity type; Removing the second ion implantation mask and forming an interlayer insulating film on the substrate; And First and second conductive impurity regions and polysilicon patterns of the first and second conductive substrates and the first and second conductive source / drain regions of the second and third substrates, respectively, on the interlayer insulating layer. And forming wirings to be contacted. The method of claim 1, wherein the first conductive type is N type and the second conductive type is P type. The method of claim 1, wherein the first well is formed deeper than the second and third wells. The method of claim 1, wherein the implanting the impurity of the second conductivity type, A method of manufacturing a bi-MOS transistor according to claim 1, wherein ion implantation is also performed on the first and second silicon epitaxial portions of the exposed first region. The method of claim 1, wherein the ion implantation of the impurity of the first conductivity type, A method of manufacturing a bi-MOS transistor according to claim 1, wherein ion implantation is also performed on the first and second silicon epitaxial portions of the exposed first region.