KR100457222B1 - Method of manufacturing high voltage device - Google Patents

Abstract

The present invention discloses a method of manufacturing a high voltage device. The disclosed method includes etching first portions of a device isolation region and an active region of a semiconductor substrate on which a well is formed to form first and second trenches, and filling an insulating layer in the first and second trenches. Forming an isolation layer in the isolation region, forming a drift region by ion implanting impurities of a conductivity type opposite to the well in the active region of the substrate at a low concentration, and removing the insulating layer embedded in the second trench Forming a gate electrode on the second trench surface and the substrate surface adjacent thereto, forming a spacer on both sidewalls of the gate electrode, and forming a gate electrode on the substrate surface on both sides of the gate electrode including the spacer. Ion-implanting impurities of the same conductivity type as the drift region at a high concentration to form a source / drain region; Forming silicide on surfaces of the gate electrode and the source / drain regions. According to the present invention, since the trench channel is formed, the channel length on the layout can be reduced, and in particular, the junction depth can be reduced, thereby improving the electrical characteristics of the high voltage device.

Description

Manufacturing Method of High Voltage Device {METHOD OF MANUFACTURING HIGH VOLTAGE DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a high voltage device using a trenched channel.

Semiconductor devices generally use a low power supply of 3.3V or less as a power supply for reducing power consumption and ensuring reliability thereof, but are interconnected with other peripheral devices in one system, and the peripheral devices In connection with the use of a high voltage of 5 V or more as a power supply, the circuit includes a high voltage element for supporting an externally supplied high voltage input voltage.

The high voltage device has the same structure as a conventional MOS device, that is, a low voltage device, and is simultaneously integrated with the low voltage device through a series of processes.

Hereinafter, a manufacturing method of a semiconductor device including a high voltage device according to the prior art will be briefly described.

As a one-step process, N-wells and P-wells are formed in a substrate through a mask process for selectively blocking N-well formation regions and P-well formation regions and ion implantation processes of N-type and P-type impurities.

In a two-step process, impurities of opposite conductivity type and wells formed on the substrate are ion-implanted at low concentrations, respectively, to form N-drift regions and P-drift regions on the P-well and N-well surfaces.

As a three-step process, a device isolation mask is formed on the substrate to expose the device isolation region in accordance with a LOCOS process, followed by channel stop ion implantation, followed by field oxidation in the device isolation region of the substrate. Oxide films are formed.

As a four-step process, ion implantation is performed to adjust the threshold voltage of the high voltage PMOS, the low voltage NMOS, and the PMOS.

As a five-step process, a gate oxide film is formed on a substrate, and a gate electrode is formed by depositing and patterning the gate conductive film.

As a six-step process, LDD regions in low voltage NMOS and PMOS are formed through ion implantation, and source / drain regions in high voltage and low voltage devices are formed.

Thereafter, a series of subsequent processes, including contact and wiring processes, are performed.

However, the high voltage device manufactured according to the prior art has the following problems.

1 and 2 are cross-sectional views of high voltage devices according to the prior art, in which FIG. 1 is a high voltage device having a self aligned source / drain region, and FIG. 2 is a non-self aligned. ) A cross-sectional view of a high voltage device having a source / drain region. Reference numeral 1 denotes a semiconductor substrate, 2 a high voltage well, 3 a field oxide film, 4 a gate electrode, 5a and 5b are drift regions, and 6a and 6b are source / drain regions, respectively.

In the case of the high voltage device shown in FIG. In order to increase the offset with the?), The length overlapping with the gate electrode 4 should be increased. By the way, when the deep drift region 5a is formed, the breakdown voltage and punch-through characteristics of the high voltage element are deteriorated, and there is a limit in reducing the channel length, which makes high integration difficult.

On the other hand, the edge of the drift region 5a is rounded, and at this time, since the electric field characteristic at the rounded junction is worst due to the rounded junction characteristic, there is a limit in reducing the junction depth.

In addition, there is a limit in reducing the channel width due to the narrow width effect caused by bird's-beak in relation to the field oxide film formed according to the LOCOS process. It is undesirable in terms of cost as it must be done.

In the case of the high voltage device shown in FIG. 2, since the source / drain regions 6b are formed non-self-aligned, the drift region 5b overlapping with the gate electrode 4 is compared with the high voltage device shown in FIG. 1. The length can be reduced. However, it is difficult to reduce the design rule for the active region between the field oxide film 3 and the gate electrode 4. This is because the design rule should be larger than the high voltage device of FIG.

In addition, although the depth of the drift region 5b may be lower than that of the high voltage device of FIG. 1, there is a limit in reducing the channel depth because a deep junction must still be formed in order to maintain an appropriate breakdown voltage, and thus, high integration is difficult.

In addition, the drift resistance is large due to the application of the offset source / drain regions 6b, whereby the amount of current flowing is considerably small, which degrades the performance of the transistor.

In addition, the high voltage device of FIG. 2 has a limitation in reducing the junction depth with respect to the rounding characteristics of the drift region 5b similarly to the high voltage device of FIG. 1, and the field oxide film is formed according to the LOCOS process. In addition, there is a limit to reducing the channel width, and the field stop ion implantation is not preferable in terms of cost.

Accordingly, an object of the present invention is to provide a method for manufacturing a high voltage device capable of reducing the channel width while lowering the junction depth.

1 and 2 are cross-sectional views of high voltage devices according to the prior art.

3 is a layout diagram of a high voltage device according to an embodiment of the present invention;

Figures 4a to 4f is a cross-sectional view showing the process cut along the line A-A 'and line B-B' of FIG.

Explanation of symbols on the main parts of the drawings

31,45a: device isolation layer 32: active region

33,49 gate oxide film 34,50 gate electrode

35,47: drift region 36,52: source / drain region

37 channel region 41 silicon substrate

42: buffer oxide film 43: well

44 pad nitride film 45 insulating film

46 ion implantation mask 48 mask pattern

51 spacer 51a oxide film

51b: nitride film T1: first trench

T2: second trench

In order to achieve the above object, the present invention comprises the steps of forming a buffer oxide film and a pad nitride film on the well formed semiconductor substrate in turn and patterning to expose the center of the device isolation region and the active region; Etching the exposed substrate regions to form a first trench in an isolation region of a substrate and a second trench in a central portion of an active region of the substrate; Depositing an insulating film on a substrate to fill the first and second trenches; CMPing the insulating film until the pad nitride film is exposed, and then removing the pad nitride film and the buffer oxide film to form a device isolation film in each of the device isolation regions of the substrate; Forming a drift region by implanting impurities of opposite conductivity type into the active region of the substrate at a low concentration; Removing the insulating layer embedded in the second trench; Sequentially forming a gate oxide film and a gate conductive film on the entire surface of the substrate including the second trench surface; Patterning the gate conductive layer and the gate oxide layer to form a gate electrode on a second trench surface and a substrate surface adjacent thereto; Forming spacers on both sidewalls of the gate electrode; Forming a source / drain region by implanting impurities of the same conductivity type as that of the drift region at a high concentration on the substrate surfaces on both sides of the gate electrode including the spacer; And forming silicide on surfaces of the gate electrode and the source / drain regions.

The forming of the drift region may include forming an ion implantation mask exposing an active region on the substrate on which the device isolation layers are formed; Implanting impurities at a low concentration into the exposed substrate region, the impurities of the opposite conductivity type to the wells; Removing the ion implantation mask; And annealing the substrate product into which the impurities are ion implanted.

In addition, removing the insulating layer embedded in the second trench may include forming a mask pattern to expose the insulating layer embedded in the second trench on a substrate resultant in which the drift region is formed; Removing the exposed insulating layer by wet etching; Removing the mask pattern; Performing a sacrificial oxidation process to compensate for substrate damage generated during the wet etching; And removing the oxide film formed on the surface of the substrate during the sacrificial oxidation process.

According to the present invention, the channel width can be reduced because of the formation of the trench channel, while the substantial channel length can be increased, and the junction depth can be lowered.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a layout diagram of a high voltage device according to an exemplary embodiment of the present invention, wherein reference numeral 31 denotes an isolation layer, 32 an active region, 33 a gate oxide layer, 34 a gate electrode, 35 a drift region, and 36 a source / The drain region and 37 represent channel regions, respectively.

The high voltage device of the present invention has a suitable offset region in the active region, and thus has a completely independent channel region 37. This is because the device isolation layer is formed through a shallow trench isolation (STI) process rather than a LOCOS process, and the photoresist pattern is formed away from the field region in connection with the wet etching of the buried insulating layer so that there is no loss of the insulating layer embedded in the trench. Because.

In addition, although not shown, in the high voltage device of the present invention, the depth of the drift region 35 is smaller than the width of the channel region 37. This is to make the effective channel length at the channel edge larger than the middle region so that punch-through does not occur at the edge.

4A to 4F are cross-sectional views illustrating processes by cutting along the lines A-A 'and B-B' of FIG. 3 to explain a method of manufacturing a high voltage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a buffer oxide film 42 is formed on a semiconductor substrate 41. Then, after implanting P-type impurities or N-type impurities by an ion implantation process using a well-mask, annealing is performed to activate the ion-implanted impurities to form P-type or N-type wells 43 in the substrate 41. ).

Referring to FIG. 4B, a pad nitride film 45 is formed on the buffer oxide film 42. Thereafter, the pad nitride layer 44 and the buffer oxide layer 42 are patterned by a known photolithography process to expose the device isolation region and the center portion of the active region of the substrate 41, and then the exposed substrate regions are etched. First trenches T1 and second trenches T2 are formed in the device isolation regions and the centers of the active regions of the substrate 41, respectively. Next, the substrate 41 is filled with the trenches T1 and T2 to fill the trenches T1 and T2 in a state where a sacrificial oxidation process is performed to remove etch damage when the first and second trenches T1 and T2 are formed. An insulating film 45 such as an oxide film is deposited on the region.

Referring to FIG. 4C, after the insulating film 45 is chemical mechanical polished (CMP) until the pad nitride film is exposed, the pad nitride film and the buffer oxide film are removed to form trenches in each of the device isolation regions of the substrate 41. Device isolation layers 45a are formed. At this time, the second trenches T2 formed in the active region are filled with the insulating layer 45. Then, the substrate resultant is annealed to densify the insulating film 45 embedded in the trenches T1 and T2. Subsequently, an ion implantation mask 46 is formed on the substrate resultant to form a drift region according to a known photo process. The ion implantation mask 46 is formed to expose a portion of the device isolation layer 45a adjacent to the active region as shown in the left figure in consideration of the process margin, and is embedded in the second trench T2 as shown in the right figure. It forms so that the edge part of both sides of the insulating film 45 may be covered. Next, in the substrate region not covered by the ion implantation mask 46, impurities of a conductivity opposite to the wells are implanted at low concentration. In this case, the ion implantation depth is preferably similar to the depth of the trench, and the ion implantation depth can be easily explained by adjusting the ion implantation energy according to the trench depth.

Referring to FIG. 4D, after removing the ion implantation mask, annealing is performed to form the drift region 47 on the surface of the active region of the substrate 41. In this case, the drift region 47 is formed on the surface of the substrate between the device isolation layer 45a and the second trench T2. In particular, the drift region 47 is formed to have a depth similar to that of the bottom surface of the second trench T2. Then, a mask pattern 48 is formed on the substrate resultant according to a known photo process to expose the insulating film embedded in the second trench T2, and then wet etching using a cleaning solution such as hydrofluoric acid is performed. 2, the insulating film buried in the trench T2 is removed. Next, a sacrificial oxidation process is performed to remove the etch damage generated during the wet etching, and then the sacrificial oxide film formed on the substrate surface is removed in the sacrificial oxidation process.

Referring to FIG. 4E, after removing the mask pattern, a gate oxide layer 49 is formed on the substrate resultant including the second trench T2 and the drift region 47. In this case, the gate oxide film 49 is formed to have a uniform thickness through deposition and oxidation of the insulating film. Next, a gate conductive film, for example, a polysilicon film is deposited on the gate oxide film 49, and then doped with a predetermined impurity in the polysilicon film, followed by the polysilicon film and the gate according to a known photolithography process. The oxide film is etched to form the gate electrode 50. In this case, the gate electrode 50 may be formed on the surface of the first trench T1 and the substrate portion adjacent thereto. Then, a sacrificial oxidation process is performed to remove the etch damage generated during the etching, and subsequently, the sacrificial oxide film formed in the sacrificial oxidation process is removed.

Referring to FIG. 4F, an oxide film 51a and a nitride film 51b are sequentially formed on the substrate resultant up to the step, and the nitride film 51b and the oxide film 51a are blanket-etched to form spacers 51 on sidewalls of the gate electrode. ). Thereafter, an ion implantation mask (not shown) is used to ion implant impurities of the same conductivity type as that of the drift region 47 at a high concentration, so that the source / drain regions 52 are formed on the substrate surface on both sides of the gate electrode 50 including the spacers. ), Thereby forming a trenched channel. Then, silicide 53 is formed on the surfaces of the gate electrode 51 and the source / drain region 52 according to a non-salicide process.

Subsequently, although not shown, a series of subsequent processes including a contact and a wiring process are performed to complete the high voltage device according to the present invention.

According to the method of the present invention as described above, since the channel is formed in the form of a trench channel, the channel width, that is, the channel length on the layout, can be reduced while the actual channel length can be increased, and the substantial junction depth, That is, the depth of the drift region can be lower than that of the conventional one.

Therefore, the high voltage device of the present invention can realize a shallow junction depth, and can significantly improve the breakdown voltage and punch-through characteristics compared to the conventional one.

In addition, the method of the present invention forms the device isolation film through the STI process rather than the locos, it is possible to prevent the reduction of the channel width due to the field oxide film formation, in particular, the number of processes and the need to perform the field stop ion implantation Increasing costs can also be fundamentally prevented.

As described above, the present invention can implement a relatively shallow junction by forming a channel of the high voltage device in the form of a trench channel, so that the punch-through and breakdown voltage characteristics can be greatly improved, and thus, the high voltage device Stable electrical characteristics can be secured.

In addition, the present invention can reduce the channel width on the layout through the implementation of the trench channel, which can be very advantageously applied to scale-down due to high integration.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (5)

Forming a buffer oxide film and a pad nitride film sequentially on the well-formed semiconductor substrate, and then patterning the semiconductor substrate to expose center portions of the device isolation region and the active region; Etching the exposed substrate regions to form a first trench in an isolation region of a substrate and a second trench in a central portion of an active region of the substrate; Depositing an insulating film on a substrate to fill the first and second trenches; CMPing the insulating film until the pad nitride film is exposed, and then removing the pad nitride film and the buffer oxide film to form a device isolation film in each of the device isolation regions of the substrate; Forming a drift region by implanting impurities of opposite conductivity type into the active region of the substrate at a low concentration; Removing the insulating layer embedded in the second trench; Sequentially forming a gate oxide film and a gate conductive film on the entire surface of the substrate including the second trench surface; Patterning the gate conductive layer and the gate oxide layer to form a gate electrode on a second trench surface and a substrate surface adjacent thereto; Forming spacers on both sidewalls of the gate electrode; Forming a source / drain region by implanting impurities of the same conductivity type as that of the drift region at a high concentration on the substrate surfaces on both sides of the gate electrode including the spacer; And And forming silicide on surfaces of the gate electrode and the source / drain regions. delete The method of claim 1, wherein the forming of the drift region Forming an ion implantation mask exposing an active region on the substrate on which the device isolation layers are formed; Implanting impurities at a low concentration into the exposed substrate region, the impurities of the opposite conductivity type to the wells; Removing the ion implantation mask; And And annealing the resultant substrate into which the impurities are ion-implanted. The method of claim 1, wherein the removing of the insulating layer embedded in the second trench comprises: Forming a mask pattern on the substrate resultant on which the drift region is formed to expose an insulating layer embedded in the second trench; Removing the exposed insulating layer by wet etching; Removing the mask pattern; Performing a sacrificial oxidation process to compensate for substrate damage generated during the wet etching; And Removing the oxide film formed on the surface of the substrate during the sacrificial oxidation process. The method of manufacturing a high voltage device according to claim 1, wherein the spacer is formed of a laminated film of an oxide film and a nitride film.