KR20010057115A - Method of forming trench transistor or integrated circuit using trench sidewall as a channel - Google Patents

Abstract

PURPOSE: A method for manufacturing trench transistor using trench side wall as channel layer is provided to obtain a semiconductor element with a high integration by forming a vertical type channel layer through using trench side walls. CONSTITUTION: A method comprises the steps of forming a thin trench onto a silicon substrate(30); depositing a nitride film at the bottom surface of the silicon substrate, and etching the resultant structure so as to form a trench spacer at the side wall of the trench; forming an element isolation film(33B) at the silicon substrate and the lower portion of the trench by using the trench spacer as a barrier film; forming a P-well by implanting P-type impurity ion to one side wall of the trench, and an N-well by implanting N-type impurity ion to the other side wall of the trench; forming a channel area by implanting impurity ion to side walls of the trench, respectively, where the P-well and N-well are formed; forming a gate oxide film(34) at the bottom surface of the silicon substrate including the trench, depositing a gate conductive film in such a manner as to cover the trench area, and partially etching the resultant structure so as to form a gate electrode(35); implanting a low concentration impurity ion to the trench side wall where the gate electrode is not formed, so as to form a low concentration source/drain area; forming a gate spacer(36) at the side surface of the gate electrode, and implanting a high concentration impurity ion to the resultant structure so as to form a high concentration source/drain area; and depositing an inter-layer insulation film onto the silicon substrate in such a manner as to cover the gate electrode, and forming a connection wire(38) contacting the gate electrode.

Description

Method for manufacturing a trench transistor using a trench sidewall as a channel layer {METHOD OF FORMING TRENCH TRANSISTOR OR INTEGRATED CIRCUIT USING TRENCH SIDEWALL AS A CHANNEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit (IC), and more particularly to a method for manufacturing a trench transistor using sidewalls of a trench as a channel layer.

As semiconductor devices from simple transistors to very large scale integration (VLSI) have evolved, significant advances have been made in many areas, including manufacturing costs and performance. One of the reasons this development has been possible is to reduce the size of circuit elements.

The most basic of such a circuit device is a highly integrated device such as a metal oxide semiconductor transistor (MOS transistor) or an insulated-gate field effect transistor (IGFET). In particular, as the size of the MOS transistor is reduced, more precise and highly integrated circuits can be manufactured.

However, the limitation that arises in reducing the size of the MOS transistor as described above is due to the limitation that appears in reducing the size of the channel width. In the MOS transistor, the channel between the source region and the drain region is formed to be non-conductive or conductive in order to perform a specific operation such as a digital operation. As the channel width gradually decreases, precision manufacturing difficulty or small contamination is reduced. The shorting of the channel layer by the material may cause the normal operation of the device to be inhibited.

Moreover, the channel width of the transistor acts as a determinant of important electrical characteristics of the semiconductor device, one of which is the transconductance which determines the magnitude of the current between the source and drain while the gate voltage is applied. As the transconductance increases, the speed at which the transistor is switched increases, so that the semiconductor device having desirable electrical characteristics must be formed so that the channel of each transistor installed in the integrated circuit can be properly adjusted.

However, a transistor configured horizontally on a semiconductor substrate makes it difficult to reduce the size of the semiconductor device because the channel layer separating the source region and the drain region occupies a large portion in the semiconductor substrate region.

Today's integrated circuits are made up of millions of transistors and millions of memory cells. When configuring transistors in a horizontal form, there is a limit to the number of transistors placed in one integrated circuit.

Therefore, a method has been proposed in which the area occupied by the transistor in the vertical form can be reduced compared to the transistor in the horizontal form. However, such a method is difficult to actually implement on a semiconductor substrate, and it is difficult to form a contact or connection wiring with a logic element or a memory cell in a small area.

Therefore, a new type of transistor is required to be easy to manufacture, to be easy to design on a small substrate, and to be able to configure with higher integration.

1A to 1H illustrate cross-sectional views of respective processes for describing a method of manufacturing a conventional trench transistor in which a channel is formed in a vertical form in order to achieve the above object. 1A to 1H illustrate a case in which a PMOS transistor and an NMOS transistor are simultaneously formed. Referring to this, a method of manufacturing a conventional trench transistor is as follows.

First, as shown in FIG. 1A, N-type impurity ions are implanted into a portion of the P-type silicon substrate 10 to form an N-type diffusion layer 11 to serve as a drain electrode of the NMOS transistor.

Thereafter, as shown in FIG. 1B, after the surfaces of the P-type silicon substrate 10 and the diffusion layer 11 are washed, the silicon epitaxial layer 12 is grown on the surfaces of the silicon substrate 10 and the N-type diffusion layer 11. . At this time, the grown silicon epitaxial layer 12 has a similar or identical component to the silicon substrate 10.

Then, as shown in FIG. 1C, a P-type impurity is implanted into a part of the surface of the silicon epitaxial layer 12 to form a P-type diffusion layer 13 to serve as a drain region of the PMOS transistor on the N-type diffusion layer 11. In this way, the drain electrodes of the NMOS transistor and the PMOS transistor are brought into contact with each other.

Then, as shown in FIG. 1D, the silicon epitaxial layer 14 is grown thickly on the P-type diffusion layer 13 and the silicon substrate 10. In this case, the silicon epitaxial layer 14 may have a component similar to that of the lower silicon substrate 10.

Thereafter, N-type impurity ions are implanted into the region where the PMOS transistor is to be formed as shown in FIG. 1E to form the N well 15. At this time, the N well 15 to be formed is brought into contact with the P-type diffusion layer 13 which is a drain region of the lower portion.

Next, as shown in FIG. 1F, the trench 16 is formed to be adjacent to the N-type diffusion layer 11, the P-type diffusion layer 13, and the N well 15. In the case of forming a CMOS transistor in which a PMOS transistor and an NMOS transistor are connected in series, the trench 16 is formed such that a conductive film is later formed to connect to the gate electrode of the PMOS transistor and the NMOS transistor.

Thereafter, as shown in FIG. 1G, the gate oxide film 17 is formed on the bottom surface of the substrate including the trench 16, and the trench spacers 18 are formed on both sidewalls of the trench 16 in which the PMOS transistor and the NMOS transistor are formed.

Then, as shown in FIG. 1H, the plug 19 is formed to cover the trench, and the source region 21 of the NMOS transistor and the source region 20 of the PMOS transistor are implanted by injecting N-type impurities to inject the source region 20 of the PMOS transistor. Form in turn.

Afterwards, the spacer 18 of the trench sidewall is in contact with the gate electrode, the connection wiring is brought into contact with the ground power supply in the source region 21 of the NMOS transistor, and the connection is in contact with the power supply voltage in the source region 20 of the PMOS transistor. When the wirings are formed, the PMOS transistors and the NMOS transistors are formed as CMOS transistors.

The trench transistor having the above structure is formed such that a channel is vertically formed between the source and drain regions formed at the top and the bottom thereof, and the drain electrodes of the PMOS transistor and the NMOS transistor are in contact with each other.

Therefore, there is an advantage in that the integration degree can be increased than in the case of forming the transistor in the horizontal form, so that it is easy to manufacture a memory device having high integration. However, since the source / drain regions and the channel form a vertical shape, it is difficult to form wirings connected to the respective regions, and it is difficult to limit the drain regions of the PMOS transistors and the NMOS transistors adjacent to each other to the exact shape, and the adjacent impurities are different from each other. There is a point that it is difficult to control the precise operation of the semiconductor element by the junction between the regions.

In order to solve the above problems, the present invention provides a method of manufacturing a trench transistor that can produce a semiconductor device of high density by forming a conductive film for the gate electrode inside the trench, and forming a channel on the sidewall of the trench. have.

In addition, the present invention provides a method of manufacturing a trench transistor that can facilitate the formation of connection wiring by forming the source / drain regions in the horizontal direction, and reduce the leakage current by increasing the overlap margin of the gate electrode. The purpose is.

1A to 1H are cross-sectional views of respective processes for illustrating a method of manufacturing a conventional trench transistor;

2 is a circuit diagram of a general CMOS inverter;

3A to 3E are cross-sectional views of respective processes for illustrating a method of manufacturing a trench transistor according to an embodiment of the present invention;

4 is a plan view of the trench transistor of FIG. 3E.

(Name of the code for the main part of the drawing)

30: silicon substrate 31: trench

32: trench spacer 33: device isolation film

34: gate oxide film 35: gate electrode

36: gate spacer 37: interlayer insulating film

38: connecting wiring

PMOS: PMOS Transistor NMOS: NMOS Transistor

41: device isolation layer 42: gate oxide film

43: gate electrode 44: connection wiring

In order to achieve the above object, the method of manufacturing a trench transistor of the present invention comprises the steps of forming a trench to form a trench type isolation layer on a silicon substrate, and depositing a nitride film on the bottom surface of the silicon substrate including the trench and etching the same. Forming a spacer on the sidewalls of the trench; forming a device isolation layer on the silicon substrate and the trench lower region using the trench spacer as a barrier layer; and implanting impurity ions into the sidewalls of the trench; Forming an N well and a channel region, forming a gate oxide film on a bottom surface of the silicon substrate including the trench, depositing a gate conductive film so as to cover the trench region, and etching the portion to form a gate electrode; , Low concentration impurities on the trench sidewalls without gate electrodes Implanting ions to form a low concentration source / drain region, forming a gate spacer on the side of the gate electrode, and then implanting high concentration impurity ions to complete the source / drain region, and covering the gate electrode After depositing an interlayer insulating film on the silicon substrate, forming a connection line to be in contact with the gate electrode.

Injecting impurities into the sidewalls of the trench may include injecting impurities at an angle to the trench sidewalls.

The gate conductive film is formed so that a predetermined portion remains on the device isolation layer on the silicon substrate.

The source / drain region may be formed by implanting impurity ions into a sidewall of a trench region in which a gate electrode is not formed.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention forms a channel in the vertical direction on the sidewalls of the trench and the source / drain regions are formed in the same plane direction as the silicon substrate, thereby improving the degree of integration of the semiconductor device and making the process easier.

The present invention is applicable to a semiconductor device having a structure in which gate electrodes are connected to each other, for example, a CMOS inverter or a static random access memory (SRAM) device. Hereinafter, a case of manufacturing a CMOS inverter will be described.

2 illustrates a circuit diagram of a CMOS transistor in which a PMOS transistor and an NMOS transistor are connected in series. Referring to FIG. 2, in the CMOS transistor, a PMOS transistor (PMOS) having a source terminal connected to a power supply voltage Vcc and a drain of an NMOS transistor (NMOS) having a source terminal connected to a ground power supply Vss are connected to each other. Each input signal (Input) is provided through. The output signal Output is output through drain terminals connected to each other.

3A to 3E are cross-sectional views of respective processes for explaining the method of manufacturing the CMOS inverter of FIG. 2 according to an embodiment of the present invention.

First, as shown in FIG. 3A, a trench 31 having a predetermined width is formed on the silicon substrate 30. The trench 31 is formed in a taper shape that is slightly inclined during the formation process, and the bottom portion is slightly bent. As described above, the sidewalls of the trench 31 having a tapered shape are used as channel layers.

Thereafter, as illustrated in FIG. 3B, the trench spacer 32 is formed on the sidewall portion of the trench 31 through a blanket etching process after the nitride film is deposited to a predetermined thickness. The trench spacer 32 has a thin upper portion and a thicker lower portion.

3C, device isolation layers 33A and 33B are formed on the lower and upper trenches, respectively, using the trench spacer 32 as a barrier layer. At this time, the device isolation layer 33B in the lower portion of the trench is reduced by the trench spacer 32, and a bird's beak phenomenon is reduced, and the device isolation layer 33A in the upper portion of the trench is sufficiently thick to form an end cap of the gate. cap) Margin can be secured.

Thereafter, the trench spacer 32 is removed, and impurity ions are implanted into the trench sidewalls to form the N well of the PMOS transistor and the P well of the NMOS transistor. At this time, the impurity ions such as phosphorus (P) and boron (B) are inclined slightly so as to be easily implanted into the trench sidewalls. After the N well and the P well are formed, impurity ions are implanted in the same manner as above to form channel layers (not shown) of the PMOS transistor and the NMOS transistor.

Then, as shown in FIG. 3D, after the gate oxide film 34 is formed over the trench, the gate electrode conductive film is deposited to a predetermined thickness, and the gate electrode 35 is formed through a lithography process. At this time, the gate electrode 35 allows the end cap portion to rise above the device isolation layer 33A formed in the upper portion of the trench, thereby reducing the leakage current by ensuring an overlap margin. Then, low concentration impurity ions are implanted into the trench region where the gate electrode 35 is not formed, thereby forming a low concentration source / drain region (not shown). Then, by forming a gate spacer 36 in the gate electrode 35 on the trench, and implanting high concentration impurity ions using the gate spacer 36 as a barrier film, a high concentration source / drain region (not shown) ).

In the above, even in the case of forming the low concentration source / drain region and the high concentration source / drain region, impurity ions are implanted with a slight inclination so that impurities are easily injected into the trench sidewalls as in the case of forming the channel layer.

3E, an interlayer insulating film 37 is formed on the silicon substrate 30 to cover the gate electrode 35, and is connected to contact the gate electrode 35 and the source / drain regions. The wiring 38 is formed to complete the CMOS inverter.

4 shows a plan view of a CMOS inverter formed by the above method. Referring to FIG. 4, trenches are formed in a straight line in the device isolation layer 41 formed on the entire surface of the silicon substrate, and the trenches all cover the gate oxide layer 42. 4 illustrates a CMOS inverter structure in which a PMOS transistor and an NMOS transistor are connected, and a gate electrode 43 is formed so that gate terminals of the PMOS transistor and the NMOS transistor are connected to each other. The trench regions where the gate electrode 43 is not formed are source / drain regions of the PMOS transistor and the NMOS transistor, respectively.

Thereafter, connecting wirings 44 are formed to contact the gate electrode 43 and the source / drain regions, respectively. In the case of a CMOS inverter, metal wirings are formed such that the drain electrodes of the PMOS transistor and the NMOS transistor are connected to each other. do. In addition, an input line is connected to the gate electrode 43 to receive an input signal, and a source terminal of the PMOS transistor and a source terminal of the NMOS transistor are respectively used for the power supply voltage Vcc and the ground power supply Vss. Followed by wiring.

By forming the trench sidewalls as the channel layer as described above, it is possible to reduce the width of the channel, thereby forming a semiconductor device having a high integration. In addition, in the present invention, the source / drain regions are not designed in a vertical shape, but are formed on the trench sidewalls in the same manner as the channel layer, thereby simplifying the connection wiring and the manufacturing process.

In the above description, a case where the CMOS inverters connected with drain terminals are connected to each other has been described as an example.

Therefore, the manufacturing method of the present invention can be applied to a semiconductor device and a memory cell in which gate terminals are connected to each other.

As described above in detail, according to the method of manufacturing a trench transistor, a semiconductor device having a higher degree of integration can be manufactured by forming a channel layer in a vertical shape using trench sidewalls.

In addition, the source / drain regions may be formed using trench sidewalls in which the gate electrodes are not formed, thereby facilitating a manufacturing process such as connection wiring, rather than a vertical form.

In addition, the end-cap portion of the gate electrode is sufficiently raised to the upper portion of the substrate, thereby ensuring an overlap margin, thereby reducing leakage current and improving electrical characteristics of the semiconductor device.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (6)

Forming a shallow trench on the silicon substrate; Depositing a nitride film on a bottom surface of the silicon substrate including the trench and etching the nitride film to form trench spacers on sidewalls of the trench; Forming an isolation layer in the silicon substrate and the lower region of the trench by using the trench spacer as a barrier layer; Implanting P-type impurity ions into one sidewall of the trench to form a P well, and implanting N-type impurity ions into the other sidewall to form an N-well; Implanting impurity ions into the trench sidewalls formed with the P well and the N well to form a channel region; Forming a gate oxide film on a bottom surface of the silicon substrate including the trench, depositing a gate conductive film so as to cover the trench region, and etching the portion to form a gate electrode; Implanting low concentration impurity ions into the trench sidewalls where the gate electrode is not formed to form a low concentration source / drain region; Forming a source / drain region by implanting high concentration impurity ions after forming a gate spacer on a side of the gate electrode; And And depositing an interlayer insulating film on the silicon substrate so that the gate electrode is covered, and then forming a connection line to be in contact with the gate electrode. The method of claim 1, wherein the trench spacer Thin at the top of the trench, A method of manufacturing a trench transistor, characterized in that to form a thick under the trench. The method of claim 1, wherein the P well and N well and the channel layer A method of manufacturing a trench transistor, wherein the trench is formed by injecting impurities into the sidewall of the trench at an angle. The method of claim 1, wherein the gate electrode A method of manufacturing a trench transistor, characterized in that it is formed so that a predetermined portion remains on the device isolation layer formed on the silicon substrate. The method of claim 1, wherein the source / drain region is And forming impurity ions into the sidewall of the trench region where the gate electrode is not formed. The method of claim 5, wherein the source / drain region is A method of manufacturing a trench transistor, wherein the trench is formed by injecting impurities into the sidewall of the trench at an angle.