JP3164375B2 - Method of forming transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

This invention relates to the field of integrated circuit manufacturing. More specifically, the invention relates to the field of forming devices for bipolar / complementary field effect integrated circuits.

[0002]

BACKGROUND OF THE INVENTION Combining a bipolar transistor with a complementary field effect transistor is an attractive combination. Bipolar transistors can switch at much higher speeds than field effect transistors. However, bipolar transistors consume much more power than field effect transistor devices, and even more power than complementary field effect transistor circuits.

[0003] The manufacture of these types of circuits has been successful. See, for example, Tran et al., 8 ns BiCMOS 1 with sizable memory array dimensions, in ISSCC 89, pp. 36 and 37.
"Mb ECL SRAM" describes a 1 Mb SRAM using BiCMOS technology. However, due to the limitations of manufacturing bipolar and field effect transistors, usually transistors of the metal oxide semiconductor type, the type of transistor is limited to a certain number of transistors, and the process is very complicated. For example,
Bipolar transistors that can withstand high voltage operation have very specific doping levels that can be used to fabricate the components of the transistor and make high quality high speed bipolar transistors and MOS devices. Therefore, it is difficult to manufacture.

[0004]

SUMMARY OF THE INVENTION The presently described embodiments of the present invention have a high voltage bipolar transistor integrated in a bipolar complementary metal oxide semiconductor integrated circuit. High-voltage transistors are more standard BiCM
Manufactured using processing steps available to manufacture other components in the OS method. The collector of the transistor is
It is formed using a buried N-type region in a P-type substrate. On the buried N-type layer, a P-type well is formed instead of a normal N-type well. The collector contact for the buried N-type layer is made to surround the P-type well to provide a separate base region. Using a P + contact to this region, a highly doped P-type base region is formed. An N + type emitter is formed by outdiffusion from a heavily doped polysilicon layer formed in contact with the base region. By providing a lightly doped P-well at the interface between the collector and the base, the breakdown voltage of the collector / base junction is substantially increased, and thus the breakdown voltage from the collector to the emitter is also increased. Transistors made in this way are suitable for use in high voltage applications.

[0005]

1A to 15A are simplified side views illustrating the processing steps required to fabricate a BiCMOS integrated circuit using various aspects of the present invention. 6B to 11B, 13
B and 15B are simplified side views showing processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention. FIGS. 6B to 11B, 13B and 15B correspond to FIG.
In parallel with the manufacturing steps of the methods shown in FIGS. A to 15A, differences in the use of processing steps for manufacturing the embodiments described herein are shown.

Referring to FIG. 1A, the starting material for the fabrication method described herein is a P-type doped <10
0> oriented crystalline silicon. This is the substrate 10 shown in FIG. 1A. A silicon dioxide layer 12 is formed on the surface of the substrate 10 by thermal oxidation in an O ₂ atmosphere at a temperature of about 900 ° C. for about 250 minutes. Next, a low pressure chemical vapor deposition is used to deposit about 100
A zero thickness silicon nitride layer is formed. The silicon dioxide layer 12 and the silicon nitride layer 14 are then patterned using conventional photolithography techniques, resulting in the structure shown in FIG. 1A. The structure of FIG. 1A, in turn, has an energy of about 40-60 kiloelectron volts and is about 3 × 10 ¹⁵ ions / cm ²
Of N-type ions, such as antimony ions, having a density of This ion implantation results in the N-type regions 16 and 18 shown in FIG. 1A. Thereafter, the structure of FIG. 1A is subjected to a thermal oxidation in a N ₂ / O ₂ atmosphere at a temperature of about 1250 ° C. for about 30 minutes. By this oxidation step, thick oxide regions 20, 2 as shown in FIG.
2 is obtained. Further, the N + doped regions 16, 18 are driven into the substrate 10 and annealed.

Next, the silicon dioxide layer 20 is removed using an HF ₂ etchant. The remaining structure is subjected to implantation of boron ions having an energy of about 160 kiloelectron volts and a density of about 4 × 10 ¹² ions / cm ² , as shown in FIG. 3A. This ion implantation is
Forming regions 24, 26, 28 are formed. (Areas 24 and 2
Next, the surface of the structure shown in FIG. 3A is made flat, and a genuine silicon epitaxial layer 30 is formed on the surface of the substrate 10. The resulting structure is shown in FIG. 4A.

Buried doped regions 16, 18, 24, 2
6, 28, 1988 to form a more flat and improved structure.
No. 265,074, filed on Jan. 1, which is assigned to the assignee of the present application and assigned to the assignee of the present application. This application is cited here.

On the surface of the structure of FIG. 4A, by thermal oxidation in an O ₂ atmosphere at a temperature of about 900 ° C. for about 60 minutes,
A silicon dioxide layer 32 is formed. This structure is shown in FIG. 5A. Next, using low pressure chemical reaction vapor deposition,
A silicon nitride layer 34 is formed to a thickness of about 1000A.
Next, the silicon nitride layer 3 is formed using ordinary photoengraving technology.
4 is patterned to create the structure shown in FIG. 5A. Thereafter, the structure of FIG. 5A has an energy of about 70 electron kilovolts and an energy of 350 kiloelectron volts, both of which are implanted with arsenic ions having a density of about 2.2 × 10 ¹² ions / cm ^2. To This ion implantation forms N-type regions 36 and 38, as shown in FIG. 5A.

Next, the structure of FIG.
Subject to thermal oxidation in a steam atmosphere for minutes. This forms the thick oxide regions 40, 42 shown in FIG. 6A. Thereafter, the structure of FIG. 6A is subjected to boron ion implantation with an energy of about 50 kiloelectron volts and a density of about 1 × 10 ¹² ions / cm ² . This ion implantation forms the P-type regions 44, 46, 48 shown in FIG. 6A. The surface of the structure of FIG. 6A is planarized and the diffusions 36, 38, 44, 46, 48 are driven inward using an annealing process at a temperature of about 1000 ° C. for about 250 minutes in an O ₂ atmosphere. .
The resulting structure is shown in FIG. 7A.

Until this stage, the processing steps required to manufacture the high-voltage transistor according to one embodiment of the present invention are as follows:
It is the same as the process shown for FIGS. 1A to 5A. FIG.
As shown in FIG. 6B, an N + type region 116 is formed using the same method as described for the N type region 16 in FIG. 6A. Similarly, the P-type regions 26, P shown in FIGS.
Using the same processing steps used to fabricate the region 28, the epitaxial layer 30, the P-type region 48 and the silicon dioxide layer 40, the P + region 126, the P + region 12
8. Make epitaxial layer 30, P-type region 148 and oxide layer 140.

However, the P-type region 148 has a buried N + type layer 1
Note that it is formed above 16. FIG.
The P-type region 148 of B is formed by the diffusion portions 36, 38, 44, 4
Using the same anneal process used for the inward drive of 6,48, it is driven inward to form P-type region 148, as shown in FIG. 7B.

Next, as shown in FIG. 8A, a thin silicon dioxide layer 50 is grown on the surface of the structure of FIG. 7A using thermal oxidation in an O ₂ atmosphere. Silicon dioxide layer 5
A silicon nitride layer 52 is formed on the surface of No. 0 and patterned to create the structure shown in FIG. 8A. Thereafter, the structure is subjected to a thermal oxidation step at about 900 ° C. for about 500 minutes in an O ₂ atmosphere to form a silicon dioxide region 54 to a thickness of about 7000 A, as shown in FIG. 8A. A silicon dioxide layer 50 and a silicon nitride layer 52 are also formed over the structure of FIG. 7B. By patterning the silicon nitride layer 52,
As shown in FIG. 8B, the patterned silicon nitride layer 5
Make 2. As shown in FIG. 8A, the same thermal oxidation process used to form the thick silicon dioxide region 54 is used to form the silicon dioxide region 54 shown in FIG. 8B.

The silicon nitride layer 52 is removed using a wet chemical etch in phosphoric acid. Thereafter, a photoresist layer 56 is formed on the surface of the structure of FIG. 8A, as shown in FIG. 9A. A photoresist layer 56 is formed and patterned as shown in FIG. 9B.

The photoresist layer 56 is selected to have a thickness sufficient to provide a thick ion implantation mask for arsenic ion implantation with a density of about 1 × 10 ¹⁶ atoms / cm ² at an energy of about 150 kiloelectron volts. It is. When this ion implantation anneals, it forms an N + contact region 58, as shown in FIG. 9A. The collector contact 158 shown in FIG. 10B is also formed by ion implantation and annealing. The collector contact 158 is a P-type well 1
It is implanted to completely surround 59 and to isolate P well 159 from P region 148. P-type region 148 electrically isolates collector contact 158 from other devices formed adjacent to the transistors formed in FIGS. 6B-11B, 13B and 15B.

Thereafter, the photoresist layer 56 is removed by using an ordinary liquid removing method.

Next, on the surface of the structure of FIG.
A silicon nitride layer 60 as shown in FIG. The silicon nitride layer 60 is patterned and etched to expose the surface of the silicon dioxide layer 50 above the N-well 36. The structure is subjected to boron ion implantation having a density of about 6 × 10 ¹³ ions / cm ² and an energy of about 40 kiloelectron volts. Next, by thermal oxidation in an O ₂ atmosphere at a temperature of about 1000 ° C. for about 100 minutes,
Grow silicon dioxide layers 64,164. The silicon dioxide layers 64, 164 are grown to a thickness of about 1400. This is annealed to form a base region 62 shown in FIG. 10A.
To form When the base region 62 is formed, FIG.
As shown in B, a base region 162 is also formed.

Thereafter, the silicon nitride layer 60 is removed using a wet chemical etch in phosphoric acid. Next, a photomask (not shown) is formed and patterned to expose a portion of silicon dioxide layer 64. next,
The exposed portions of silicon dioxide layer 64 are removed using reactive ion etching. Thereafter, the photomask (not shown) is removed to form a polysilicon layer 66 on the surface of the structure of FIG. 11A. Polycrystalline silicon layer 66 is doped in N ++ form using one of several optional methods, such as ion implantation, in-situ doping, or any other suitable method. This photomask (not shown) is also used to pattern and etch the silicon dioxide layer 164 to create the structure of FIG. 11B. As described with respect to FIG. 11A, a polysilicon layer 66 is formed on the surface of the structure of FIG.
Is deposited and doped.

Thereafter, the polysilicon layer 66 is patterned to form an emitter contact 68, a gate 72, and a gate 74, as shown in FIG. 12A. In this method, part of the doping from the polysilicon layer 66 is
At two locations, it diffuses into the surface of substrate 10 to form N ++ emitter 76. During the same step, when N ++ emitter region 76 is driven inward, emitter region 176 is also driven inward. The polysilicon layer 66 is patterned to provide an emitter contact 168 and a collector contact 158 shown in FIG. 13B.

Next, using chemical vapor deposition, FIG.
On the surface of the structure of A, as shown in FIGS.
A silicon dioxide layer 78 is formed to a thickness of 000. A suitable etching mask 80 made of a material such as silicon nitride is formed over the surface of silicon dioxide layer 78. The etch mask 80 and the silicon dioxide layer 78 are patterned and etched to expose the surface of the P-well 48 not covered by the gate 74. The etch mask 80 and the silicon dioxide layer 78 are removed by reactive ion etching and anisotropic etching using a CHF ₃ etchant. As a result, a part of the silicon dioxide layer 78 remains as the sidewall oxide layer 82. Then, 150 electron kilovolts energy and about 3 × 10
Arsenic ion implantation with a density of ¹⁵ ions / cm ² is performed. This ion implanted portion was annealed to obtain FIG.
Are formed as shown in FIG.

Thereafter, the etch mask 80 is removed, and a second etch mask 86 is formed as shown in FIGS. 15A and 15B. The etch mask 86 is then patterned using conventional photolithography techniques to create the structure of the etch mask 86 shown in FIGS. 15A and 15B. Thereafter, the silicon dioxide layer 78 and the silicon dioxide layers 50, 150, 64 and 164 are etched using an etch mask 86,
Emitter contact 68, gate 72 and emitter contact 168
Alternatively, the surfaces of the N-wells 36 and 38 and the P-well 159 that are not covered by the structure of the etch mask 86 are exposed. The structures of FIGS. 15A and 15B are then ion implanted with boron ions having an energy of about 20 kiloelectron volts and a density of about 3 × 10 ¹⁵ ions / cm ² . Thus, a P-type source / drain region 90 and a base contact region 92 shown in FIG. 15A and a P + -type base contact region 192 shown in FIG. 15B are formed. Further, since the etching of the silicon dioxide layer 78 is performed using an anisotropic process,
Sidewall oxide regions 88 and 188 remain on the sides of emitter contact 68 and gate 72.

Thus, an NPN transistor 94, a P-channel transistor 96, an N-channel transistor 98 and an NPN transistor 200 are formed.
Additional steps such as silicidation of the surfaces of the emitter contacts 68, gates 72, 74, source / drain regions 84, source / drain regions 90, and base contact regions 92, 192 are performed to effect the resulting structure. The conductivity can be further improved.

Since P-well 159 has a lower doping level than base region 162, the junction between P-well region 159 and buried collector 116 and collector contact 158 is thicker, and is resistant to breakdown for high voltages. Has greater resistance. This is because the depletion region formed at the interface between the lightly doped regions is wider. Therefore, the collector-emitter breakdown voltage of transistor 200 is higher than the collector-emitter breakdown voltage of transistor 94 of FIG. 15A. Further, the high-voltage transistor 200 is formed without using any extra manufacturing steps in addition to the steps for forming the transistors 94, 96, 98.

While a particular embodiment of the invention has been described, it should not be construed as limiting the scope of the invention. The scope of the present invention is limited only by the claims.

In connection with the above description, the present invention has the following embodiments.

(1) In a method of forming a bipolar transistor and a complementary field effect transistor in a common substrate, the method has a P-type conductivity type, an N-channel transistor area, a P-channel transistor area, and a bipolar transistor.・ Prepare a substrate with a transistor area,
Forming a buried N-type layer remote from the surface of the substrate in the P-channel transistor area and the bipolar transistor area, and forming a buried P-type layer remote from the surface of the substrate in the N-channel area; Forming an N-type well in the P-channel transistor area extending from the buried N-type layer to the surface, and forming a P-type well in the N-channel transistor area and the bipolar transistor area; A P-well in the bipolar transistor area and the P-well formed to extend from the buried P-type layer in the area to the surface and to extend from the buried N-type layer in the bipolar transistor area to the surface. Introducing dopant atoms into the N-type well in the channel transistor area Forming a P-type base contact region, a P-type source and a P-type drain, and forming an N-type emitter in the bipolar transistor area by introducing dopant atoms into a P-type well in the bipolar transistor area. Introducing dopant atoms into the P-well of the N-channel transistor section,
Forming an N-type source and an N-type drain in the N-channel transistor area and forming a gate to control conduction between the source and the drain of the N-channel transistor area and the P-channel transistor area. .

(2) The method according to item (1), wherein the substrate is made of crystalline silicon.

(3) The method according to item (1), wherein the gate is separated from the substrate by an insulating layer.

(4) In the method described in (1), the buried N-type layer is formed by implanting dopant ions into the surface of the substrate, and forming an epitaxial layer on the surface of the substrate. Including methods.

(5) The method according to item (1), wherein the buried P-type layer is formed by implanting dopant ions into the surface of the substrate, and comprises forming an epitaxial layer on the surface of the substrate. Method.

(6) In the method described in item (4), N
The method wherein the wells are formed by implanting dopant ions into the epitaxial layer.

(7) In the method described in (4), P
The method wherein the wells are formed by implanting dopant ions into the epitaxial layer.

(8) In the method described in (5), N
The method wherein the wells are formed by implanting dopant ions into the epitaxial layer.

(9) In the method described in the item (5), P
The method wherein the wells are formed by implanting dopant ions into the epitaxial layer.

(10) The embodiment of the invention described herein shows a high-voltage bipolar transistor 200 integrated in a bipolar complementary metal oxide semiconductor integrated circuit. The high voltage transistors are manufactured using processing steps available to manufacture other components in a more standard BiCMOS method. The collector of the transistor is a P-type substrate 1
It is formed using a buried N-type region 116 in 0. Above the buried N-layer, a P-well 1 instead of a normal N-well
59 are formed. A collector contact 158 to the buried N-type layer is made surrounding the P-well to create a separate base region. Highly doped P-type base region 1
62 are formed using P + contacts 192 to this area. Out-diffusion from the heavily doped polysilicon layer 168 formed in contact with the base region forms an N + type emitter 176. By providing a lightly doped P-well as the interface between the collector and the base, the breakdown voltage at the collector / base junction is substantially higher, and therefore the collector-to-emitter breakdown voltage is also higher. The transistor thus made is suitable for high voltage.

[Brief description of the drawings]

FIG. 1A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit.

FIG. 2A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit.

FIG. 3A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit.

FIG. 4A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit.

FIG. 5A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit.

FIG. 6A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit. FIG. 6B is a simplified side view showing the processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention, which is parallel to the processing steps of the method shown in FIGS. 1A to 15A. The figure which shows the difference in the usage of the processing process to manufacture.

FIG. 7A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit. FIG. 7B is a simplified side view showing processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention, which is parallel to the processing steps of the method shown in FIGS. 1A to 15A. The figure which shows the difference in the usage of the processing process which performs.

FIG. 8A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit. FIG. 8B is a simplified side view showing processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention, which is parallel to the processing steps of the method shown in FIGS. 1A to 15A. The figure which shows the difference in the usage of the processing process which performs.

FIG. 9A illustrates BiC using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture a MOS integrated circuit. FIG. 9B is a simplified side view showing the processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention, which is parallel to the processing steps of the method shown in FIGS. 1A to 15A. The figure which shows the difference in the usage of the processing process which performs.

FIG. 10A illustrates B using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture an iCMOS integrated circuit. FIG. 10B is a simplified side view showing processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention, which is parallel to the processing steps of the method shown in FIGS. 1A to 15A. The figure which shows the difference in the usage of the processing process which performs.

FIG. 11A illustrates B using various aspects of the present invention.
FIG. 11B is a simplified side view showing processing steps required for manufacturing an iCMOS integrated circuit, and FIG. 11B is a simplified side view showing processing steps required for manufacturing a high-voltage transistor according to an embodiment of the present invention. 15A to 15A are views parallel to the processing steps of the method shown in FIGS.

FIG. 12A illustrates B using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture an iCMOS integrated circuit.

FIG. 13A illustrates B using various aspects of the present invention.
FIG. 13B is a simplified side view showing processing steps required to manufacture an iCMOS integrated circuit, and FIG. 13B is a simplified side view showing processing steps required to manufacture a high-voltage transistor according to an embodiment of the present invention. 15A to 15A are views parallel to the processing steps of the method shown in FIGS.

FIG. 14A illustrates B using various aspects of the present invention.
FIG. 4 is a simplified side view showing processing steps required to manufacture an iCMOS integrated circuit.

FIG. 15A illustrates B using various aspects of the present invention.
FIG. 15B is a simplified side view showing the processing steps required to manufacture an iCMOS integrated circuit, and FIG. 15B is a simplified side view showing the processing steps required to manufacture a high-voltage transistor according to one embodiment of the present invention. 15A to 15A are views parallel to the processing steps of the method shown in FIGS.

[Explanation of symbols]

 10 Substrate 116 Buried N-type region 159 P-type well 162 P-type base region 176 N-type emitter

──────────────────────────────────────────────────続 き Continued from the front page (56) References JP-A-63-240058 (JP, A) JP-A-61-245563 (JP, A) JP-A-61-182253 (JP, A) JP-A 64-64 66962 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8249 H01L 27/06 H01L 27/08 H01L 21/8222-21/8228 H01L 21/8232

Claims (1)

(57) [Claims] 1. A method for forming a high-voltage bipolar transistor and a complementary field effect transistor in a common substrate, comprising: a P-type transistor having an N-channel transistor area, a P-channel transistor area, and a bipolar transistor area. Providing a substrate, forming a buried N-type layer spaced from the surface of the substrate in the P-channel transistor area and the bipolar transistor area, and forming a buried P-type layer in the N-channel area separated from the surface of the substrate; Forming an N-type well in the P-channel transistor area, extending from the buried N-type layer to the surface, and forming a P-well in the N-channel transistor area and the bipolar transistor area. From the buried p-type layer in the n-channel transistor area to the surface Extending from the buried N-type layer in the bipolar transistor area to the surface, and having a dopant in the P-type well in the bipolar transistor area and the N-type well in the P-channel transistor area. The introduction of atoms forms a P-type base contact region, a P-type source and a P-type drain, and a P-type contact in the bipolar transistor area.
Forming an N-type emitter in said bipolar transistor area by introducing dopant atoms into the well.
An N-type source and an N-type drain are formed in the N-channel transistor area by introducing dopant atoms into the P-type well of the N-channel transistor area, and the N-channel transistor area and the P-channel transistor area are formed. Forming a gate that controls conduction between the source and the drain.